TL F 8582

DP8390DNS32490D

NIC

Network

Interface

Controller

July 1995

DP8390D NS32490D NIC Network Interface Controller

General Description

The DP8390D NS32490D Network Interface Controller
(NIC) is a microCMOS VLSI device designed to ease inter-
facing with CSMA CD type local area networks including
Ethernet Thin Ethernet (Cheapernet) and StarLAN The
NIC implements all Media Access Control (MAC) layer func-
tions for transmission and reception of packets in accord-
ance with the IEEE 802 3 Standard Unique dual DMA chan-
nels and an internal FIFO provide a simple yet efficient
packet management design To minimize system parts
count and cost all bus arbitration and memory support logic
are integrated into the NIC

The NIC is the heart of a three chip set that implements the
complete IEEE 802 3 protocol and node electronics as
shown below The others include the DP8391 Serial Net-
work Interface (SNI) and the DP8392 Coaxial Transceiver
Interface (CTI)

Features

Compatible with IEEE 802 3 Ethernet II Thin Ethernet
StarLAN

Interfaces with 8- 16- and 32-bit microprocessor
systems

Implements simple versatile buffer management

Requires single 5V supply

Utilizes low power microCMOS process

Includes

Two 16-bit DMA channels
16-byte internal FIFO with programmable threshold
Network statistics storage

Supports physical multicast and broadcast address
filtering

Provides 3 levels of loopback

Utilizes independent system and network clocks

Table of Contents

1 0 SYSTEM DIAGRAM

2 0 BLOCK DIAGRAM

3 0 FUNCTIONAL DESCRIPTION

4 0 TRANSMIT RECEIVE PACKET ENCAPSULATION

DECAPSULATION

5 0 PIN DESCRIPTIONS

6 0 DIRECT MEMORY ACCESS CONTROL (DMA)

7 0 PACKET RECEPTION

8 0 PACKET TRANSMISSION

9 0 REMOTE DMA

10 0 INTERNAL REGISTERS

11 0 INITIALIZATION PROCEDURES

12 0 LOOPBACK DIAGNOSTICS

13 0 BUS ARBITRATION AND TIMING

14 0 PRELIMINARY ELECTRICAL CHARACTERISTICS

15 0 SWITCHING CHARACTERISTICS

16 0 PHYSICAL DIMENSIONS

1 0 System Diagram

IEEE 802 3 Compatible Ethernet Thin Ethernet Local Area Network Chip Set

TL F 8582 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

2 0 Block Diagram

TL F 8582 2

FIGURE 1

3 0 Functional Description

(Refer to

Figure 1 )

RECEIVE DESERIALIZER

The Receive Deserializer is activated when the input signal
Carrier Sense is asserted to allow incoming bits to be shift-
ed into the shift register by the receive clock The serial
receive data is also routed to the CRC generator checker
The Receive Deserializer includes a synch detector which
detects the SFD (Start of Frame Delimiter) to establish
where byte boundaries within the serial bit stream are locat-
ed After every eight receive clocks the byte wide data is
transferred to the 16-byte FIFO and the Receive Byte Count
is incremented

The first six bytes after the SFD are

checked for valid comparison by the Address Recognition
Logic If the Address Recognition Logic does not recognize
the packet the FIFO is cleared

CRC GENERATOR CHECKER

During transmission the CRC logic generates a local CRC
field for the transmitted bit sequence The CRC encodes all
fields after the synch byte The CRC is shifted out MSB first
following the last transmit byte During reception the CRC
logic generates a CRC field from the incoming packet This
local CRC is serially compared to the incoming CRC ap-
pended to the end of the packet by the transmitting node If
the local and received CRC match a specific pattern will be
generated and decoded to indicate no data errors Trans-
mission errors result in a different pattern and are detected
resulting in rejection of a packet

TRANSMIT SERIALIZER

The Transmit Serializer reads parallel data from the FIFO
and serializes it for transmission The serializer is clocked by

the transmit clock generated by the Serial Network Interface
(DP8391) The serial data is also shifted into the CRC gen-
erator checker At the beginning of each transmission the
Preamble and Synch Generator append 62 bits of 1 0 pre-
amble and a 1 1 synch pattern After the last data byte of
the packet has been serialized the 32-bit FCS field is shifted
directly out of the CRC generator In the event of a collision
the Preamble and Synch generator is used to generate a
32-bit JAM pattern of all 1's

ADDRESS RECOGNITION LOGIC

The address recognition logic compares the Destination Ad-
dress Field (first 6 bytes of the received packet) to the Phys-
ical address registers stored in the Address Register Array
If any one of the six bytes does not match the pre-pro-
grammed physical address the Protocol Control Logic re-
jects the packet All multicast destination addresses are fil-
tered using a hashing technique (See register description )
If the multicast address indexes a bit that has been set in
the filter bit array of the Multicast Address Register Array
the packet is accepted otherwise it is rejected by the Proto-
col Control Logic Each destination address is also checked
for all 1's which is the reserved broadcast address

FIFO AND FIFO CONTROL LOGIC

The NIC features a 16-byte FIFO During transmission the
DMA writes data into the FIFO and the Transmit Serializer
reads data from the FIFO and transmits it During reception
the Receive Deserializer writes data into the FIFO and the
DMA reads data from the FIFO The FIFO control logic is
used to count the number of bytes in the FIFO so that after
a preset level the DMA can begin a bus access and write
read data to from the FIFO before a FIFO underflow

over-

flow occurs

3 0 Functional Description

(Continued)

Because the NIC must buffer the Address field of each in-
coming packet to determine whether the packet matches its
Physical Address Registers or maps to one of its Multicast
Registers the first local DMA transfer does not occur until 8
bytes have accumulated in the FIFO

To assure that there is no overwriting of data in the FIFO
the FIFO logic flags a FIFO overrun as the 13th byte is
written into the FIFO this effectively shortens the FIFO to
13 bytes In addition the FIFO logic operates differently in
Byte Mode than in Word Mode In Byte Mode a threshold is
indicated when the n

1 byte has entered the FIFO thus

with an 8-byte threshold the NIC issues Bus Request
(BREQ) when the 9th byte has entered the FIFO For Word
Mode BREQ is not generated until the n

2 bytes have

entered the FIFO Thus with a 4 word threshold (equivalent
to an 8-byte threshold) BREQ is issued when the 10th byte
has entered the FIFO

PROTOCOL PLA

The protocol PLA is responsible for implementing the IEEE
802 3 protocol including collision recovery with random
backoff The Protocol PLA also formats packets during
transmission and strips preamble and synch during recep-
tion

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control Logic is used to control two
16-bit DMA channels During reception the Local DMA
stores packets in a receive buffer ring located in buffer
memory During transmission the Local DMA uses pro-
grammed pointer and length registers to transfer a packet
from local buffer memory to the FIFO A second DMA chan-
nel is used as a slave DMA to transfer data between the
local buffer memory and the host system The Local DMA
and Remote DMA are internally arbitrated with the Local
DMA channel having highest priority Both DMA channels
use a common external bus clock to generate all required
bus timing External arbitration is performed with a standard
bus request bus acknowledge handshake protocol

4 0 Transmit Receive Packet
Encapsulation Decapsulation

A standard IEEE 802 3 packet consists of the following
fields preamble Start of Frame Delimiter (SFD) destination
address source address length data and Frame Check
Sequence (FCS) The typical format is shown in

Figure 2

The packets are Manchester encoded and decoded by the
DP8391 SNI and transferred serially to the NIC using NRZ
data with a clock All fields are of fixed length except for the
data field The NIC generates and appends the preamble
SFD and FCS field during transmission The Preamble and
SFD fields are stripped during reception (The CRC is
passed through to buffer memory during reception )

PREAMBLE AND START OF FRAME DELIMITER (SFD)

The Manchester encoded alternating 1 0 preamble field is
used by the SNI (DP8391) to acquire bit synchronization
with an incoming packet When transmitted each packet
contains 62 bits of alternating 1 0 preamble Some of this
preamble will be lost as the packet travels through the net-
work The preamble field is stripped by the NIC Byte align-
ment is performed with the Start of Frame Delimiter (SFD)
pattern which consists of two consecutive 1's The NIC
does not treat the SFD pattern as a byte it detects only the

two bit pattern This allows any preceding preamble within
the SFD to be used for phase locking

DESTINATION ADDRESS

The destination address indicates the destination of the
packet on the network and is used to filter unwanted pack-
ets from reaching a node There are three types of address
formats supported by the NIC physical multicast and
broadcast The physical address is a unique address that
corresponds only to a single node All physical addresses
have an MSB of ``0'' These addresses are compared to the
internally stored physical address registers Each bit in the
destination address must match in order for the NIC to ac-
cept the packet Multicast addresses begin with an MSB of
``1'' The DP8390D filters multicast addresses using a stan-
dard hashing algorithm that maps all multicast addresses
into a 6-bit value This 6-bit value indexes a 64-bit array that
filters the value If the address consists of all 1's it is a
broadcast address indicating that the packet is intended for
all nodes A promiscuous mode allows reception of all pack-
ets the destination address is not required to match any
filters Physical broadcast multicast and promiscuous ad-
dress modes can be selected

SOURCE ADDRESS

The source address is the physical address of the node that
sent the packet Source addresses cannot be multicast or
broadcast addresses This field is simply passed to buffer
memory

LENGTH FIELD

The 2-byte length field indicates the number of bytes that
are contained in the data field of the packet This field is not
interpreted by the NIC

DATA FIELD

The data field consists of anywhere from 46 to 1500 bytes
Messages longer than 1500 bytes need to be broken into
multiple packets Messages shorter than 46 bytes will re-
quire appending a pad to bring the data field to the minimum
length of 46 bytes If the data field is padded the number of
valid data bytes is indicated in the length field The NIC
does not strip or append pad bytes for short packets
or check for oversize packets

FCS FIELD

The Frame Check Sequence (FCS) is a 32-bit CRC field
calculated and appended to a packet during transmission to
allow detection of errors when a packet is received During
reception error free packets result in a specific pattern in
the CRC generator Packets with improper CRC will be re-
jected The AUTODIN II (X

polynomial is used for the CRC calculations

TL F 8582 3

FIGURE 2

5 0 Pin Descriptions

(Continued)

BUS INTERFACE PINS

(Continued)

Symbol

DIP Pin No

Function

Description

CHIP SELECT

Chip Select places controller in slave mode for mP access to

internal registers Must be valid through data portion of bus cycle RA0 RA3 are
used to select the internal register SWR and SRD select direction of data
transfer

MWR

O Z

MASTER WRITE STROBE

Strobe for DMA transfers active low during write

cycles (t2 t3 tw) to buffer memory Rising edge coincides with the presence of
valid output data TRI-STATE until BACK asserted

MRD

O Z

MASTER READ STROBE

Strobe for DMA transfers active during read cycles

(t2 t3 tw) to buffer memory Input data must be valid on rising edge of MRD
TRI-STATE until BACK asserted

SWR

SLAVE WRITE STROBE

Strobe from CPU to write an internal register selected

by RA0 RA3

SRD

SLAVE READ STROBE

Strobe from CPU to read an internal register selected

by RA0 RA3

ACK

ACKNOWLEDGE

Active low when NIC grants access to CPU Used to insert

WAIT states to CPU until NIC is synchronized for a register read or write
operation

RA0 RA3

45 48

These four pins are used to select a register to be read

or written The state of these inputs is ignored when the NIC is not in slave mode
(CS high)

PRD

PORT READ

Enables data from external latch onto local bus during a memory

write cycle to local memory (remote write operation) This allows asynchronous
transfer of data from the system memory to local memory

WACK

WRITE ACKNOWLEDGE

Issued from system to NIC to indicate that data has

been written to the external latch The NIC will begin a write cycle to place the
data in local memory

INT

INTERRUPT

Indicates that the NIC requires CPU attention after reception

transmission or completion of DMA transfers The interrupt is cleared by writing
to the ISR All interrupts are maskable

RESET

Reset is active low and places the NIC in a reset mode immediately no

packets are transmitted or received by the NIC until STA bit is set Affects
Command Register Interrupt Mask Register Data Configuration Register and
Transmit Configuration Register The NIC will execute reset within 10 BUSK
cycles

BREQ

BUS REQUEST

Bus Request is an active high signal used to request the bus for

DMA transfers This signal is automatically generated when the FIFO needs
servicing

BACK

BUS ACKNOWLEDGE

Bus Acknowledge is an active high signal indicating that

the CPU has granted the bus to the NIC If immediate bus access is desired
BREQ should be tied to BACK Tying BACK to V

will result in a deadlock

PRQ ADS1

O Z

PORT REQUEST ADDRESS STROBE 1

32-BIT MODE If LAS is set in the Data Configuration Register this line is
programmed as ADS1 It is used to strobe addresses A16 A31 into external
latches (A16 A31 are the fixed addresses stored in RSAR0 RSAR1 ) ADS1
will remain at TRI-STATE until BACK is received

16-BIT MODE If LAS is not set in the Data Configuration Register this line is
programmed as PRQ and is used for Remote DMA Transfers In this mode
PRQ will be a standard logic output

NOTE This line will power up as TRI-STATE until the Data Configuration
Register is programmed

READY

This pin is set high to insert wait states during a DMA transfer The NIC

will sample this signal at t3 during DMA transfers

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