TL F 10427
DP8392BNS32492B
Coaxial
Transceiver
Interface
July 1989
DP8392B NS32492B Coaxial Transceiver Interface
General Description
The DP8392B Coaxial Transceiver Interface (CTI) is a coax-
ial cable line driver receiver for Ethernet Thin Ethernet
(Cheapernet) type local area networks The CTI is connect-
ed between the coaxial cable and the Data Terminal Equip-
ment (DTE) In Ethernet applications the transceiver is usu-
ally mounted within a dedicated enclosure and is connected
to the DTE via a transceiver cable In Cheapernet applica-
tions the CTI is typically located within the DTE and con-
nects to the DTE through isolation transformers only The
CTI consists of a Receiver Transmitter Collision Detector
and a Jabber Timer The Transmitter connects directly to a
50 ohm coaxial cable where it is used to drive the coax
when transmitting During transmission a jabber timer is ini-
tiated to disable the CTI transmitter in the event of a longer
than legal length data packet Collision Detection circuitry
monitors the signals on the coax to determine the presence
of colliding packets and signals the DTE in the event of a
collision
The CTI is part of a three chip set that implements the com-
plete IEEE 802 3 compatible network node electronics as
shown below The other two chips are the DP8391 Serial
Network Interface (SNI) and the DP8390 Network Interface
Controller (NIC)
The SNI provides the Manchester encoding and decoding
functions whereas the NIC handles the Media Access Pro-
tocol and the buffer management tasks Isolation between
the CTI and the SNI is an IEEE 802 3 requirement that can
be easily satisfied on signal lines using a set of pulse trans-
formers that come in a standard DIP However the power
isolation for the CTI is done by DC-to-DC conversion
through a power transformer
Features
Y
Optimized for receive mode collision detection
Y
Compatible with Ethernet II IEEE 802 3 10Base5 and
10Base2 (Cheapernet)
Y
Integrates all transceiver electronics except signal
power isolation
Y
Innovative design minimizes external component count
Y
Jabber timer function integrated on chip
Y
Externally selectable CD Heartbeat allows operation
with IEEE 802 3 compatible repeaters
Y
Precision circuitry implements receive mode collision
detection
Y
Squelch circuitry at all inputs rejects noise
Y
Designed
for
rigorous
reliability
requirements
of
IEEE 802 3
Y
Standard Outline 16-pin DIP uses a special leadframe
that significantly reduces the operating die temperature
Table of Contents
1 0
System Diagram
2 0
Block Diagram
3 0
Functional Description
3 1
Receiver and Squelch
3 2
Transmitter and Squelch
3 3
Collision and Heartbeat
3 4
Jabber Timer
4 0
Connection Diagram
5 0
Pin Descriptions
6 0
Absolute Maximum Ratings
7 0
Electrical Characteristics
8 0
Switching Characteristics
9 0
Timing and Load Diagram
10 0 Physical Dimensions
1 0 System Diagram
TL F 10427 1
IEEE 802 3 Compatible Ethernet Cheapernet Local Area Network Chip Set
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
2 0 Block Diagram
TL F 10427 2
FIGURE 1 DP8392B Block Diagram
3 0 Functional Description
The CTI consists of four main logical blocks
a) the Receiver - receives data from the coax and sends it
to the DTE
b) the Transmitter - accepts data from the DTE and trans-
mits it onto the coax
c) the Collision Detect circuitry - indicates to the DTE any
collision on the coax
d) the Jabber Timer - disables the Transmitter in case of
longer than legal length packets
3 1 RECEIVER FUNCTIONS
The Receiver includes an input buffer a cable equalizer a
4-pole Bessel low pass filter a squelch circuit and a differ-
ential line driver
The buffer provides high input impedance and low input ca-
pacitance to minimize loading and reflections on the coax
The equalizer is a high pass filter which compensates for
the low pass effect of the cable The composite result of the
maximum length cable and the equalizer is a flatband re-
sponse at the signal frequencies to minimize jitter
The 4-pole Bessel low pass filter extracts the average DC
level on the coax which is used by both the Receiver
squelch and the collision detection circuits
The Receiver squelch circuit prevents noise on the coax
from falsely triggering the Receiver in the absence of the
signal At the beginning of the packet the Receiver turns on
when the DC level from the low pass filter is lower than the
DC squelch threshold However at the end of the packet a
quick Receiver turn off is needed to reject dribble bits This
is accomplished by an AC timing circuit that reacts to high
level signals of greater than typically 200 ns in duration The
Receiver then stays off only if within about 1 ms the DC
level from the low pass filter rises above the DC squelch
threshold
Figure 2 illustrates the Receiver timing
The differential line driver provides ECL compatible signals
to the DTE with typically 3 ns rise and fall times In its idle
state its outputs go to differential zero to prevent DC stand-
ing current in the isolation transformer
3 2 TRANSMITTER FUNCTIONS
The Transmitter has a differential input and an open collec-
tor output current driver The differential input common
mode voltage is established by the CTI and should not be
altered by external circuitry The transformer coupling of
TX
g
will satisfy this condition The driver meets all IEEE
802 3 Ethernet Specifications for signal levels Controlled
rise and fall times (25 ns V
g
5 ns) minimize the higher
harmonic components The rise and fall times are matched
to minimize jitter The drive current levels of the DP8392B
meet the tighter recommended limits of IEEE 802 3 and are
set by a built-in bandgap reference and an external 1% re-
sistor An on chip isolation diode is provided to reduce the
Transmitter's coax load capacitance For Ethernet compati-
ble applications an external isolation diode (see
Figure 4 )
may be added to further reduce coax load capacitance In
Cheapernet compatible applications the external diode is
not required as the coax capacitive loading specifications
are relaxed
The Transmitter squelch circuit rejects signals with pulse
widths less than typically 20 ns (negative going) or with
levels less than
b
175 mV The Transmitter turns off at the
end of the packet if the signal stays higher than
b
175 mV
for more than approximately 300 ns
Figure 3 illustrates the
Transmitter timing
2
3 0 Functional Description
(Continued)
3 3 COLLISION FUNCTIONS
The collision circuitry consists of two buffers two 4-pole
Bessel low pass filters (section 3 1) a comparator a heart-
beat generator a 10 MHz oscillator and a differential line
driver
Two identical buffers and 4-pole Bessel low pass filters ex-
tract the DC level on the center conductor (data) and the
shield (sense) of the coax These levels are monitored by
the comparator If the data level is more negative than the
sense level by at least the collision threshold (Vth) the colli-
sion output is enabled
At the end of every transmission the heartbeat generator
creates a pseudo collision for a short time to ensure that the
collision circuitry is properly functioning This burst on colli-
sion output occurs typically 1 1 ms after the transmission
and has a duration of about 1 ms This function can be dis-
abled externally with the HBE (Heartbeat Enable) pin to al-
low operation with repeaters
The 10 MHz oscillator generates the signal for the collision
and heartbeat functions It is also used as the timebase for
all the jabber functions It does not require any external
components
The collision differential line driver transfers the 10 MHz sig-
nal to the CD
g
pair in the event of collision jabber or
heartbeat conditions This line driver also features zero dif-
ferential idle state
3 4 JABBER FUNCTIONS
The Jabber Timer monitors the Transmitter and inhibits
transmission if the Transmitter is active for longer than
20 ms (fault) It also enables the collision output for the fault
duration After the fault is removed The Jabber Timer waits
for about 500 ms (unjab time) before re-enabling the Trans-
mitter The transmit input must stay inactive during the unjab
time
TL F 10427 3
FIGURE 2 Receiver Timing
TL F 10427 4
FIGURE 3 Transmitter Timing
3
4 0 Connection Diagram
TL F 10427 5
Note 1
T1 is a 1 1 pulse transformer L
e
100 mH
Top View
Pulse Engineering (San Diego) Part No 64103
Valor Electronics (San Diego)
Order Number DP8392BN
Part No 1101 or equivalent
See NS Package Number N16A
Note 2
This pin must be connected
to the coax shield
FIGURE 4
4
5 0 Pin Descriptions
Pin No
Name
I O
Description
1
CD
a
O
Collision Output
Balanced differential line driver outputs from the collision detect
circuitry The 10 MHz signal from the internal oscillator is transferred to these
2
CD
b
outputs in the event of collision excessive transmission (jabber) or during CD
Heartbeat condition These outputs are open emitters pulldown resistors to VEE
are required When operating into a 78X transmission line these resistors should
be 500X In Cheapernet applications where the 78X drop cable is not used
higher resistor values (up to 1 5k) may be used to save power
3
RX
a
O
Receive Output
Balanced differential line driver outputs from the Receiver These
outputs also require 500X pulldown resistors
6
RX
b
7
TX
a
I
Transmit Input
Balanced differential line receiver inputs to the Transmitter The
common mode voltage for these inputs is determined internally and must not be
8
TX
b
externally established Signals meeting Transmitter squelch requirements are
waveshaped and output at TXO
9
HBE
I
Heartbeat Enable
This input enables CD Heartbeat when grounded disables it
when connected to VEE
11
RR
a
I
External Resistor
A fixed 1k 1% resistor connected between these pins
establishes internal operating currents
12
RR
b
14
RXI
I
Receive Input
Connects directly to the coaxial cable Signals meeting Receiver
squelch requirements are equalized for inter-symbol distortion amplified and
outputted at RX
g
15
TXO
O
Transmit Output
Connects either directly (Cheapernet) or via an isolation diode
(Ethernet) to the coaxial cable
16
CDS
I
Collision Detect Sense
Ground sense connection for the collision detect circuit
This pin should be connected separately to the shield to avoid ground drops from
altering the receive mode collision threshold
10
GND
Positive Supply Pin
A 0 1 mF ceramic decoupling capacitor must be connected
across GND and VEE as close to the device as possible
4
VEE
Negative Supply Pins
In order to make full use of the 3 5W power dissipation
capability of this package these pins should be connected to a large metal frame
5
area on the PC board Doing this will reduce the operating die temperature of the
13
device thereby increasing the long term reliability
IEEE names for CD
g
e
CI
g
RX
g
e
DI
g
TX
g
e
DO
g
5 1 P C BOARD LAYOUT
The DP8392B package is uniquely designed to ensure that
the device meets the 1 million hour Mean Time Between
Failure (MTBF) requirement of the IEEE 802 3 standard In
order to fully utilize this heat dissipation design the three
V
EE
pins are to be connected to a copper plane which
should be included in the printed circuit board layout Refer
to National Semiconductor application note AN-442 (Ether-
net Cheapernet Physical Layer Made Easy) for complete
board layout instructions
5
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