TL F 8535
DP8402ADP8403DP8404DP8405
32-Bit
Parallel
Error
Detection
and
Correction
Circuits
(EDAC's)
PRELIMINARY
August 1989
DP8402A DP8403 DP8404 DP8405 32-Bit Parallel
Error Detection and Correction Circuits (EDAC's)
General Description
The DP8402A DP8403 DP8404 and DP8405 devices are
32-bit parallel error detection and correction circuits
(EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404
and DP8405 600-mil packages The EDACs use a modified
Hamming code to generate a 7-bit check word from a 32-bit
data word This check word is stored along with the data
word during the memory write cycle During the memory
read cycle the 39-bit words from memory are processed by
the EDACs to determine if errors have occurred in memory
Single-bit errors in the 32-bit data word are flagged and cor-
rected
Single-bit errors in the 7-bit check word are flagged and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location
Double bit errors are flagged but not corrected These er-
rors may occur in any two bits of the 39-bit word from mem-
ory (two errors in the 32-bit data word two errors in the 7-bit
check word or one error in each word) The gross-error
condition of all lows or all highs from memory will be detect-
ed Otherwise errors in three or more bits of the 39-bit word
are beyond the capabilities of these devices to detect
Read-modify-write (byte-control) operations can be per-
formed with the DP8402A and DP8403 EDACs by using out-
put latch enable LEDBO and the individual OEB0 thru
OEB3 byte control pins
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
DB and CB input latches These will determine if the failure
occurred in memory or in the EDAC
Features
Y
Detects and corrects single-bit errors
Y
Detects and flags double-bit errors
Y
Built-in diagnostic capability
Y
Fast write and read cycle processing times
Y
Byte-write capability
DP8402A and DP8403
Y
Fully pin and function compatible with TI's
SN74ALS632A thru SN74ALS635 series
System Environment
TL F 8535 1
TRI-STATE
is a registered trademark of National Semiconductor Corp
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
Simplified Functional Block and Connection Diagrams
TL F 8535 2
Device
Package
Byte-Write
Output
DP8402A
52-pin
yes
TRI-STATE
DP8403
52-pin
yes
Open-Collector
DP8404
48-pin
no
TRI-STATE
DP8405
48-pin
no
Open-Collector
Dual-In-Line Packages
TL F 8535 10
Top View
TL F 8535 3
Top View
Plastic Chip Carrier
TL F 8535 11
Top View
Order Number DP8402AV
See NS Package Number V68A
Order Number DP8402AD
DP8403D DP8404D or DP8405D
See NS Package Number D48A or D52A
2
Mode Definitions
DESCRIPTION
PIN NAME
MODE
S1
S0
MODE
OPERATION
0
L
L
WRITE
Input dataword and output
checkword
1
L
H
DIAGNOSTICS
Input various data words
against latched
checkword output valid
error flags
2
H
L
READ
FLAG
Input dataword and output
error flags
3
H
H
CORRECT
Latched input data and
checkword output
corrected data and
syndrome code
Pin Definitions
S0 S1
Control of EDAC mode see preceding
Mode Definitions
DB0 thru DB31 I O port for 32 bit dataword
CB0 thru CB6
I O port for 7 bit checkword Also output
port for the syndrome error code during
error correction mode
OEB0 thru
Dataword output buffer enable When high
OEB3
output buffers are at TRI-STATE Each pin
(DP8402A
controls 8 I O ports OEB0 controls DB0
DP8403)
thru DB7 OEB1 controls DB8 thru DB15
OEB2 controls DB16 thru DB23 and OEB3
controls DB24 thru DB31
LEDBO
Data word output Latch enable When high
(DP8402A
it inhibits input to the Latch Operates on all
DP8403)
32 bits of the dataword
OEDB
TRI-STATE control for the data I O port
(DP8404
When high output buffers are at
DP8405)
TRI-STATE
OECB
Checkword output buffer enable When
high the output buffers are in TRI-STATE
mode
ERR
Single error output flag a low indicates at
least a single bit error
MERR
Multiple error output flag a low indicates
two or more errors present
PCC Pin Definitions DP8402A
pin 1
V
CC
pin 35
OECB
2
LEDBO
36
CB3
3
MERR
37
CB2
4
ERR
38
CB1
5
DB0
39
CB0
6
DB1
40
DB16
7
DB2
41
DB17
8
NC
42
NC
9
NC
43
NC
10
NC
44
DB18
11
DB3
45
DB19
12
DB4
46
DB20
13
DB5
47
DB21
14
OEBO
48
OEB2
15
DB6
49
DB22
16
DB7
50
DB23
17
GND
51
GND
18
GND
52
GND
19
DB8
53
DB24
20
DB9
54
DB25
21
OEB1
55
OEB3
22
DB10
56
DB26
23
DB11
57
DB27
24
DB12
58
DB28
25
DB13
59
NC
26
DB14
60
NC
27
NC
61
NC
28
NC
62
NC
29
NC
63
DB29
30
DB15
64
DB30
31
NC
65
DB31
32
CB6
66
S0
33
CB5
67
S1
34
CB4
68
V
CC
TABLE I Write Control Function
Memory
EDAC
Control
DB Control
DB Output Latch
CB
Error Flags
Cycle
Function
S1
S0
Data I O
OEBn or
DP8402A DP8403
Check I O
Control
ERR
MERR
OEDB
LEDBO
OECB
Write
Generate
L
L
Input
H
X
Output
L
H
H
check word
check bits
See Table II for details on check bit generation
Memory Write Cycle Details
During a memory write cycle the check bits (CB0 thru CB6)
are generated internally in the EDAC by seven 16-input pari-
ty generators using the 32-bit data word as defined in Table
2 These seven check bits are stored in memory along with
the original 32-bit data word This 32-bit word will later be
used in the memory read cycle for error detection and cor-
rection
3
TABLE II Parity Algorithm
Check Word
32-Bit Data Word
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CB0
X
X
X
X
X
X
X
X
X
X
X X X X
X
X
CB1
X
X
X
X
X
X
X
X
X
X
X
X
X
X X
CB2
X
X
X
X
X
X
X
X
X
X
X X
X
X X X
X
CB3
X
X
X
X
X
X
X
X
X
X
X
X X X
X X
CB4
X
X
X
X
X
X
X
X
X
X
X X X X X X
CB5
X
X
X
X
X
X
X
X
X
X
X
X
X
X X X
CB6
X
X
X
X
X
X
X
X
X X X X X X X X
The seven check bits are parity bits derived from the matrix of data bits as indicated by ``X'' for each bit
Check bits 0 1 2 are odd parity or the exclusive NORing of the ``X''ed bits for the particular check bit Check bits 3 4 5 6 are even parity or the exclusive ORing of
the ``X''ed bits for the particular check bit
Memory Read Cycle (Error
Detection
Correction Details)
During a memory read cycle the 7-bit check word is re-
trieved along with the actual data In order to be able to
determine whether the data from the memory is acceptable
to use as presented on the bus the error flags must be
tested to determine if they are at the high level
The first case in Table III represents the normal no-error
conditions The EDAC presents highs on both flags The
next two cases of single-bit errors give a high on MERR and
a low on ERR which is the signal for a correctable error
and the EDAC should be sent through the correction cycle
The last three cases of double-bit errors will cause the
EDAC to signal lows on both ERR and MERR which is the
interrupt indication for the CPU
TABLE III Error Function
Total Number of Errors
Error Flags
Data Correction
32-Bit Data Word
7-Bit Check Word
ERR
MERR
0
0
H
H
Not applicable
1
0
L
H
Correction
0
1
L
H
Correction
1
1
L
L
Interrupt
2
0
L
L
Interrupt
0
2
L
L
Interrupt
The DP8402 check bit syndrome matrix can be seen in TA-
BLE II The horizontal rows of this matrix generate the
check bits by selecting different combinations of data bits
indicated by ``X''s in the matrix and generating parity from
them For instance parity check bit ``0'' is generated by
EXCLUSIVE NORing the following data bits together 31
29 28 26 21 19 18 17 14 11 9 8 7 6 4 and 0 For
example the data word ``00000001H'' would generate the
check bits CB6 0
e
48H (Check bits 0 1 2 are odd parity
and check bits 3 4 5 6 are even parity)
During a WRITE operation (mode 0) the data enters the
DP8402 and check bits are generated at the check bit in-
put output port Both the data word and the check bits are
then written to memory
During a READ operation (mode 2 error detection) the data
and check bits that were stored in memory now possibly in
error are input through the data and check bit I O ports
New check bits are internally generated from the data word
These new check bits are then compared by an EXCLU-
SIVE NOR operation with the original check bits that were
stored in memory The EXCLUSIVE NOR of the original
check bits that were stored in memory with the new check
bits is called the syndrome word If the original check bits
are the same as the new check bits a no error condition
then a syndrome word of all ones is produced and both
error flags (ERR and MERR) will be high The DP8402 ma-
trix encodes errors as follows
TABLE IV Read Flag and Correct Function
Memory
EDAC
Control
DB Control
DB Output Latch
CB
Error Flags
Cycle
Function
S1
S0
Data I O
OEBn or
DP8402A DP8403
Check I O
Control
ERR
MERR
OEDB
LEDBO
OECB
Read
Read
flag
H
L
Input
H
X
Input
H
Enabled
Latch input
Input
Input
Read
data and check
H
H
data
H
L
check word
H
Enabled
bits
latched
latched
Output
Output
Output
Read
corrected data
H
H
corrected
L
X
syndrome
L
Enabled
syndrome bits
data word
bits
See Table III for error description
See Table V for error location
4
Memory Read Cycle (Error Detection
Correction Details)
(Continued)
1) Single data bit errors cause 3 or 5 bits in the syndrome
word to go low The columns of the check bit syndrome
matrix (TABLE II) are the syndrome words for all single bit
data errors in the 32 bit word (also see TABLE V) The
data bit in error corresponds to the column in the check
bit syndrome matrix that matches the syndrome word
For instance the syndrome word indicating that data bit
31 is in error would be (CB6-CB0)
e
``0001010'' see the
column for data bit 31 in TABLE II or see TABLE V
During mode 3 (S0
e
S1
e
1) the syndrome word is
decoded during single data bit errors and used to invert
the bit in error thus correcting the data word The correct-
ed word is made available on the data I O port (DB0 thru
DB31) the check word I O port (CB0 thru CB6) presents
the 7-bit syndrome error code This syndrome error code
can be used to locate the bad memory chip
2) A single check bit error will cause that particular check bit
to go low in the syndrome word
3) A double bit error will cause an even number of bits in the
syndrome word to go low The syndrome word will then
be the EXCLUSIVE NOR of the two individual syndrome
words corresponding to the 2 bits in error The two-bit
error is not correctable since the parity tree can only
identify single bit errors
If any of the bits in the syndrome word are low the ``ERR''
flag goes low The ``MERR'' (dual error) flag goes low during
any double bit error conditions (See Table III)
Three or more simultaneous bit errors can cause the EDAC
to believe that no error a correctable error or an uncorrect-
able error has occurred and will produce erroneous results
in all three cases It should be noted that the gross-error
conditions of all lows and all highs will be detected
TABLE V Syndrome Decoding
Syndrome Bits
Error
6 5 4 3 2 1 0
L L L L L L L
unc
L L L L L L H
2-bit
L L L L L H L
2-bit
L L L L L H H
unc
L L L L H L L
2-bit
L L L L H L H
unc
L L L L H H L
unc
L L L L H H H
2-bit
L L L H L L L
2-bit
L L L H L L H
unc
L L L H L H L DB31
L L L H L H H
2-bit
L L L H H L L
unc
L L L H H L H
2-bit
L L L H H H L
2-bit
L L L H H H H DB30
L L H L L L L
2-bit
L L H L L L H
unc
L L H L L H L DB29
L L H L L H H
2-bit
L L H L H L L DB28
L L H L H L H
2-bit
L L H L H H L
2-bit
L L H L H H H DB27
L L H H L L L DB26
L L H H L L H
2-bit
L L H H L H L
2-bit
L L H H L H H DB25
L L H H H L L
2-bit
L L H H H L H DB24
L L H H H H L
unc
L L H H H H H
2-bit
CB X
e
error in check bit X
DB Y
e
error in data bit Y
2-bit
e
double-bit error
unc
e
uncorrectable multibit error
Syndrome Bits
Error
6 5 4 3 2 1 0
L H L L L L L
2-bit
L H L L L L H
unc
L H L L L H L
DB7
L H L L L H H
2-bit
L H L L H L L
DB6
L H L L H L H
2-bit
L H L L H H L
2-bit
L H L L H H H
DB5
L H L H L L L
DB4
L H L H L L H
2-bit
L H L H L H L
2-bit
L H L H L H H
DB3
L H L H H L L
2-bit
L H L H H L H
DB2
L H L H H H L
unc
L H L H H H H
2-bit
L H H L L L L
DB0
L H H L L L H
2-bit
L H H L L H L
2-bit
L H H L L H H
unc
L H H L H L L
2-bit
L H H L H L H
DB1
L H H L H H L
unc
L H H L H H H
2-bit
L H H H L L L
2-bit
L H H H L L H
unc
L H H H L H L
unc
L H H H L H H
2-bit
L H H H H L L
unc
L H H H H L H
2-bit
L H H H H H L
2-bit
L H H H H H H
CB6
Syndrome Bits
Error
6 5 4 3 2 1 0
H L L L L L L
2-bit
H L L L L L H
unc
H L L L L H L
unc
H L L L L H H
2-bit
H L L L H L L
unc
H L L L H L H
2-bit
H L L L H H L
2-bit
H L L L H H H
unc
H L L H L L L
unc
H L L H L L H
2-bit
H L L H L H L
2-bit
H L L H L H H DB15
H L L H H L L
2-bit
H L L H H L H
unc
H L L H H H L DB14
H L L H H H H
2-bit
H L H L L L L
unc
H L H L L L H
2-bit
H L H L L H L
2-bit
H L H L L H H DB13
H L H L H L L
2-bit
H L H L H L H DB12
H L H L H H L DB11
H L H L H H H
2-bit
H L H H L L L
2-bit
H L H H L L H DB10
H L H H L H L
DB9
H L H H L H H
2-bit
H L H H H L L
DB8
H L H H H L H
2-bit
H L H H H H L
2-bit
H L H H H H H
CB5
Syndrome Bits
Error
6 5 4 3 2 1 0
H H L L L L L
unc
H H L L L L H
2-bit
H H L L L H L
2-bit
H H L L L H H DB23
H H L L H L L
2-bit
H H L L H L H DB22
H H L L H H L DB21
H H L L H H H
2-bit
H H L H L L L
2-bit
H H L H L L H DB20
H H L H L H L DB19
H H L H L H H
2-bit
H H L H H L L DB18
H H L H H L H
2-bit
H H L H H H L
2-bit
H H L H H H H
CB4
H H H L L L L
2-bit
H H H L L L H DB16
H H H L L H L
unc
H H H L L H H
2-bit
H H H L H L L DB17
H H H L H L H
2-bit
H H H L H H L
2-bit
H H H L H H H
CB3
H H H H L L L
unc
H H H H L L H
2-bit
H H H H L H L
2-bit
H H H H L H H
CB2
H H H H H L L
2-bit
H H H H H L H
CB1
H H H H H H L
CB0
H H H H H H H none
5
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