TL F 8396
DP8417NS32817
841832818
841932819
8419X32819X
64k
256k
Dynamic
RAM
ControllerDrivers
PRELIMINARY
August 1989
DP8417 NS32817 8418 32818 8419 32819 8419X
32819X 64k 256k Dynamic RAM Controller Drivers
General Description
The DP8417 8418 8419 8419X represent a family of 256k
DRAM Controller Drivers which are designed to provide
``No-Waitstate'' CPU interface to Dynamic RAM arrays of up
to 2 Mbytes and larger Each device offers slight functional
variations of the DP8419 design which are tailored for differ-
ent system requirements All family members are fabricated
using National's new oxide isolated Advanced Low power
Schottky (ALS) process and use design techniques which
enable them to significantly out-perform all other LSI or dis-
crete alternatives in speed level of integration and power
consumption
Each device integrates the following critical 256k DRAM
controller functions on a single monolithic device ultra pre-
cise delay line 9-bit refresh counter fall-through row col-
umn and bank select input latches Row Column address
muxing logic on-board high capacitive-load RAS CAS and
Write Enable
Address output drivers and precise control
signal timing for all the above
There are four device options of the basic DP8419 Control-
ler The DP8417 is pin and function compatible with the
DP8419 except that its outputs are TRI-STATE
The
DP8418 changes one pin and is specifically designed to
offer an optimum interface to 32 bit microprocessors The
DP8419X is functionally identical to the DP8419 but is avail-
able in a 52-pin DIP package which is upward pin compati-
ble with National's new DP8429D 1 Mbit DRAM Controller
Driver
Each device is available in plastic DIP Ceramic DIP and
Plastic Chip Carrier (PCC) packaging (Continued)
TRI-STATE
is a registered trademark of National Semiconductor Corp
PAL
is a registered trademark of and used under license with Monolithic Memories Inc
Operational Features
Y
Makes DRAM Interface and refresh tasks appear virtu-
ally transparent to the CPU making DRAMs as easy to
use as static RAMs
Y
Specifically designed to eliminate CPU wait states up to
10 MHz or beyond
Y
Eliminates 15 to 20 SSI MSI components for significant
board real estate reduction system power savings and
the elimination of chip-to-chip AC skewing
Y
On-board ultra precise delay line
Y
On-board high capacitive RAS CAS WE and address
drivers (specified driving 88 DRAMs directly)
Y
AC specified for directly addressing up to 8 Megabytes
Y
Low power high speed bipolar oxide isolated process
Y
Upward pin and function compatible with new DP8428
DP8429 1 Mbit DRAM controller drivers
Y
Downward pin and function compatible with DP8408A
DP8409A 64k 256k DRAM controller drivers
Y
4 user selectable modes of operation for Access and
Refresh (2 automatic 2 external)
Contents
Y
System and Device Block Diagrams
Y
Recommended Companion Components
Y
Device Connection Diagrams and Pin Definitions
Y
Family Device Differences
(DP8419 vs DP8409A 8417 8418 8419X)
Y
Mode of Operation
(Descriptions and Timing Diagrams)
Y
Application Description and Diagrams
Y
DC AC Electrical Specifications Timing Diagrams and
Test Conditions
System Diagram
TL F 8396 25
C1995 National Semiconductor Corporation
RRD-B30M105 Printed in U S A
General Description
(Continued)
In order to specify each device for ``true'' worst case operat-
ing conditions all timing parameters are guaranteed while
the chip is driving the capacitive load of 88 DRAMs includ-
ing trace capacitance The chip's delay timing logic makes
use of a patented new delay line technique which keeps
A C skew to
g
3 ns over the full V
CC
range of
g
10% and
temperature range of
b
55 C to
a
125 C The DP8417
DP8418 DP8419 and DP8419X guarantee a maximum
RASIN to CASOUT delay of 80 ns or 70 ns even while driv-
ing a 2 Mbyte memory array with error correction check bits
included Speed selected options of these devices are
shown in the switching characteristics section of this docu-
ment
With its four independent RAS outputs and nine multiplexed
address outputs the DP8419 can support up to four banks
of 16k 64k or 256k DRAMs Two bank select pins B1 and
B0 are decoded to activate one of the RAS signals during
an access leaving the three non-selected banks in the
standby mode (less than one tenth of the operating power)
with data outputs in TRI-STATE
The DP8419 has two mode-select pins allowing for two re-
fresh modes and two access modes Refresh and access
timing may be controlled either externally or automatically
The automatic modes require a minimum of input control
signals
A refresh counter is on-chip and is multiplexed with the row
and column inputs Its contents appear at the address out-
puts of the DP8419 during any refresh and are incremented
at the completion of the refresh Row Column and bank
address latches are also on-chip However if the address
inputs to the DP8419 are valid throughout the duration of
the access these latches may be operated in the fall-
through mode
System Companion Components
Device
Function
DP84300
Programmable Refresh Timer for DP84xx DRAM Controller
DP84412
NS32008 16 32 to DP8409A 17 18 19 28 29 Interface
DP84512
NS32332 to DP8417 18 19 28 29 Interface
DP84322
68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 8 MHz)
DP84422
68000 08 10 to DP8409A 17 18 19 28 29 Interface (up to 12 5 MHz)
DP84522
68020 to DP8417 18 19 28 29 Interface
DP84432
8086 88 186 188 to DP8409A 17 18 19 28 29 Interface
DP84532
80286 to DP8409A 17 18 19 28 29 Interface
DP8400-2
16-bit Expandable Error Checker Corrector
DP8400-4
16-bit Expandable Error Checker Corrector
DP8402A
32-bit Error Detector and Corrector (EDAC)
2
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