TL F 8588

DP8420A21A22A

microCMOS

Programmable

256k1M4M

Dynamic

RAM

ControllerDrivers

July 1992

DP8420A 21A 22A microCMOS Programmable
256k 1M 4M Dynamic RAM Controller Drivers

General Description

The DP8420A 21A 22A dynamic RAM controllers provide a
low cost single chip interface between dynamic RAM and
all 8- 16- and 32-bit systems The DP8420A 21A 22A gen-
erate all the required access control signal timing for
DRAMs An on-chip refresh request clock is used to auto-
matically refresh the DRAM array Refreshes and accesses
are arbitrated on chip If necessary a WAIT or DTACK out-
put inserts wait states into system access cycles including
burst mode accesses RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge An additional fea-
ture of the DP8422A is two access ports to simplify dual
accessing Arbitration among these ports and refresh is
done on chip

Features

On chip high precision delay line to guarantee critical
DRAM access timing parameters

microCMOS process for low power

High capacitance drivers for RAS CAS WE and DRAM
address on chip

On chip support for nibble page and static column
DRAMs

Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic

Selection of controller speeds 20 MHz and 25 MHz

On board Port A Port B (DP8422A only) refresh arbitra-
tion logic

Direct interface to all major microprocessors (applica-
tion notes available)

4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)

of Pins

of Address

Largest

Direct Drive

Access

Control

(PLCC)

Outputs

DRAM

Memory

Ports

Possible

Capacity

Available

DP8420A

256 kbit

4 Mbytes

Single Access Port

DP8421A

1 Mbit

16 Mbytes

Single Access Port

DP8422A

4 Mbit

64 Mbytes

Dual Access Ports (A and B)

Block Diagram

DP8420A 21A 22A DRAM Controller

TL F 8588 5

FIGURE 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

Staggered Refresh

is a trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

Table of Contents

1 0 INTRODUCTION

2 0 SIGNAL DESCRIPTIONS

2 1 Address R W and Programming Signals

2 2 DRAM Control Signals

2 3 Refresh Signals

2 4 Port A Access Signals

2 5 Port B Access Signals (DP8422A)

2 6 Common Dual Port Signals (DP8422A)

2 7 Power Signals and Capacitor Input

2 8 Clock Inputs

3 0 PROGRAMMING AND RESETTING

3 1 External Reset

3 2 Programming Methods

3 2 1 Mode Load Only Programming

3 2 2 Chip Selected Access Programming

3 3 Internal Programming Modes

4 0 PORT A ACCESS MODES

4 1 Access Mode 0

4 2 Access Mode 1

4 3 Extending CAS with Either Access Mode

4 4 Read-Modify-Write Cycles with Either Access Mode

4 5 Additional Access Support Features

4 5 1 Address Latches and Column Increment

4 5 2 Address Pipelining

4 5 3 Delay CAS During Write Accesses

5 0 REFRESH OPTIONS

5 1 Refresh Control Modes

5 1 1 Automatic Internal Refresh

5 1 2 Externally Controlled Burst Refresh

5 1 3 Refresh Request Acknowledge

5 2 Refresh Cycle Types

5 2 1 Conventional Refresh

5 2 2 Staggered Refresh

5 2 3 Error Scrubbing Refresh

5 3 Extending Refresh

5 4 Clearing the Refresh Address Counter

5 5 Clearing the Refresh Request Clock

6 0 PORT A WAIT STATE SUPPORT

6 1 WAIT Type Output

6 2 DTACK Type Output

6 3 Dynamically Increasing the Number of Wait States

6 4 Guaranteeing RAS Low Time and RAS Precharge

Time

7 0 RAS AND CAS CONFIGURATION MODES

7 1 Byte Writing

7 2 Memory Interleaving

7 3 Address Pipelining

7 4 Error Scrubbing

7 5 Page Burst Mode

8 0 TEST MODE

9 0 DRAM CRITICAL TIMING PARAMETERS

9 1 Programmable Values of t

RAH

and t

ASC

9 2 Calculation of t

RAH

and t

ASC

10 0 DUAL ACCESSING (DP8422A)

10 1 Port B Access Mode

10 2 Port B Wait State Support

10 3 Common Port A and Port B Dual Port Functions

10 3 1 GRANTB Output

10 3 2 LOCK Input

11 0 ABSOLUTE MAXIMUM RATINGS

12 0 DC ELECTRICAL CHARACTERISTICS

13 0 AC TIMING PARAMETERS

14 0 FUNCTIONAL DIFFERENCES BETWEEN THE

DP8420A 21A 22A AND THE DP8420 21 22

15 0 DP8420A 21A 22A USER HINTS

1 0 Introduction

The DP8420A 21A 22A are CMOS Dynamic RAM control-
lers that incorporate many advanced features which include
address latches refresh counter refresh clock row column
and refresh address multiplexer delay line refresh access
arbitration logic and high capacitive drivers The program-
mable system interface allows any manufacturer's micro-
processor

bus

directly

interface

via

the

DP8420A 21A 22A to DRAM arrays up to 64 Mbytes in
size

After power up the user must first reset and program the
DP8420A 21A 22A before accessing the DRAM The chip
is programmed through the address bus

Reset

Due to the differences in power supplies the internal reset
circuit may not always reset correctly therefore an External
(hardware) Reset must be performed before programming
the chip

Programming

After resetting the chip the user can program the controller
by either one of two methods Mode Load Only Program-
ming or Chip Select Access Programming

Initialization Period

Once the DP8420A 21A 22A has been programmed for the
first time a 60 ms initialization period is entered During this
time the DRC performs refreshes to the DRAM array so
further warm up cycles are unnecessary The initialization
period is entered only after the first programming after a
reset

Accessing Modes

After

resetting

and

programming

the

chip

the

DP8420A 21A 22A is ready to access the DRAM There
are two modes of accessing with these controllers Mode 0
which indicates RAS synchronously and Mode 1 which indi-
cates RAS asynchronously

Refresh Modes

The DP8420A 21A 22A have expanded refresh capabilities
compared to previous DRAM controllers There are three
modes of refreshing available Internal Automatic Refresh-
ing Externally Controlled Burst Refreshing and Refresh Re-
quest Acknowledge Refreshing Any of these modes can
be used together or separately to achieve the desired re-
sults

Refresh Types

These controllers have three types of refreshing available
Conventional Staggered and Error Scrubbing Any refresh
control mode can be used with any type of refresh

Wait Support

The DP8420A 21A 22A have wait support available as
DTACK or WAIT Both are programmable DTACK Data
Transfer ACKnowledge is useful for processors whose wait
signal is active high WAIT is useful for those processors
whose wait signal is active low The user can choose either
at programming These signals are used by the on chip arbi-
ter to insert wait states to guarantee the arbitration between
accesses refreshes and precharge Both signals are inde-
pendent of the access mode chosen and both signals can
be dynamically delayed further through the WAITIN signal to
the DP8420A 21A 22A

Sequential Accesses (Static Column Page Mode)

The DP8420A 21A 22A have address latches used to
latch the bank row and column address inputs Once the
address is latched a COLumn INCrement (COLINC) feature
can be used to increment the column address The address
latches can also be programmed to be fall through COLINC
can be used for Sequential Accesses of Static Column
DRAMs Also COLINC in conjunction with ECAS inputs can
be used for Sequential Accesses to Page Mode DRAMs

RAS and CAS Configuration (Byte Writing)

The RAS and CAS drivers can be configured to drive a one
two or four bank memory array up to 32 bits in width The
ECAS signals can then be used to select one of four CAS
drivers for Byte Writing with no extra logic

Memory Interleaving

When configuring the DP820A 21A 22A for more than one
bank Memory Interleaving can be used By tying the low
order address bits to the bank select lines B0 and B1 se-
quential back to back accesses will not be delayed since
these controllers have separate precharge counters per
bank

Address Pipelining

The DP8420A 21A 22A are capable of performing Address
Pipelining In address pipelining the DRC will guarantee the
column address hold time and switch the internal multiple-
xor to place the row address on the address bus At this
time another memory access to another bank can be initiat-
ed

Dual Accessing

Finally the DP8422A has all the features previously men-
tioned and unlike the DP8420A 21A the DP8422A has a
second port to allow a second CPU to access the same
memory array The DP8422A has four signals to support
Dual Accessing these signals are AREQB ATACKB LOCK
and GRANTB All arbitration for the two ports and refresh is
done on chip by the controller through the insertion of wait
states Since the DP8422A has only one input address bus
the address lines must be multiplexed externally The signal
GRANTB can be used for this purpose

Terminology

The following explains the terminology used in this data
sheet The terms negated and asserted are used Asserted
refers to a ``true'' signal Thus ``ECAS0 asserted'' means
the ECAS0 input is at a logic 0 The term ``COLINC assert-
ed'' means the COLINC input is at a logic 1 The term negat-
ed refers to a ``false'' signal Thus ``ECAS0 negated''
means the ECAS0 input is at a logic 1 The term ``COLINC
negated'' means the input COLINC is at a logic 0 The table
shown below clarifies this terminology

Signal

Action

Logic Level

Active High

Asserted

High

Active High

Negated

Low

Active Low

Asserted

Low

Active Low

Negated

High

2 0 Signal Descriptions

Device (If not

Input

Description

Name

Applicable to All)

Output

2 1 ADDRESS R W AND PROGRAMMING SIGNALS

R0 10

DP8422A

ROW ADDRESS

These inputs are used to specify the row address during an access

to the DRAM They are also used to program the chip when ML is asserted (except

R0 9

DP8420A 21A

R10)

C0 10

DP8422A

COLUMN ADDRESS

These inputs are used to specify the column address during an

access to the DRAM They are also used to program the chip when ML is asserted

C0 9

DP8420A 21A

(except C10)

B0 B1

BANK SELECT

Depending on programming these inputs are used to select a group

of RAS and CAS outputs to assert during an access They are also used to program
the chip when ML is asserted

ECAS0 3

ENABLE CAS

These inputs are used to enable a single or group of CAS outputs

when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access The
ECAS signals can also be used to toggle a group of CAS outputs for page nibble
mode accesses They also can be used for byte write operations If ECAS0 is
negated during programming continuing to assert the ECAS0 while negating AREQ
or AREQB during an access will cause the CAS outputs to be extended while the
RAS outputs are negated (the ECASn inputs have no effect during scrubbing
refreshes)

WIN

WRITE ENABLE IN

This input is used to signify a write operation to the DRAM If

ECAS0 is asserted during programming the WE output will follow this input This
input asserted will also cause CAS to delay to the next positive clock edge if address
bit C9 is asserted during programming

COLINC

COLUMN INCREMENT

When the address latches are used and RFIP is negated

this input functions as COLINC Asserting this signal causes the column address to

(EXTNDRF)

be incremented by one When RFIP is asserted this signal is used to extend the
refresh cycle by any number of periods of CLK until it is negated

MODE LOAD

This input signal when low enables the internal programming register

that stores the programming information

2 2 DRAM CONTROL SIGNALS

Q0 10

DP8422A

DRAM ADDRESS

These outputs are the multiplexed output of the R0 9 10 and

C0 9 10 and form the DRAM address bus These outputs contain the refresh

Q0 9

DP8421A

address whenever RFIP is asserted They contain high capacitive drivers with 20X

Q0 8

DP8421A

series damping resistors

RAS0 3

ROW ADDRESS STROBES

These outputs are asserted to latch the row address

contained on the outputs Q0 8 9 10 into the DRAM When RFIP is asserted the
RAS outputs are used to latch the refresh row address contained on the Q0 8 9 10
outputs in the DRAM These outputs contain high capacitive drivers with 20X series
damping resistors

CAS0 3

COLUMN ADDRESS STROBES

These outputs are asserted to latch the column

address contained on the outputs Q0 8 9 10 into the DRAM These outputs have
high capacitive drivers with 20X series damping resistors

WRITE ENABLE

or REFRESH REQUEST This output asserted specifies a write

operation to the DRAM When negated this output specifies a read operation to the

(RFRQ)

DRAM When the DP8420A 21A 22A is programmed in address pipelining mode or
when ECAS0 is negated during programming this output will function as RFRQ
When asserted this pin specifies that 13 ms or 15 ms have passed If DISRFSH is
negated the DP8420A 21A 22A will perform an internal refresh as soon as possible
If DISRFRSH is asserted RFRQ can be used to externally request a refresh through
the input RFSH This output has a high capacitive driver and a 20X series damping
resistor

2 0 Signal Descriptions

(Continued)

Device (If not

Input

Description

Name

Applicable to All)

Output

2 3 REFRESH SIGNALS

RFIP

REFRESH IN PROGRESS

This output is asserted prior to a refresh cycle and is

negated when all the RAS outputs are negated for that refresh

RFSH

REFRESH

This input asserted with DISRFRSH already asserted will request a

refresh If this input is continually asserted the DP8420A 21A 22A will perform
refresh cycles in a burst refresh fashion until the input is negated If RFSH is asserted
with DISRFSH negated the internal refresh address counter is cleared (useful for
burst refreshes)

DISRFSH

DISABLE REFRESH

This input is used to disable internal refreshes and must be

asserted when using RFSH for externally requested refreshes

2 4 PORT A ACCESS SIGNALS

ADS

ADDRESS STROBE

or ADDRESS LATCH ENABLE Depending on programming

this input can function as ADS or ALE In mode 0 the input functions as ALE and

(ALE)

when asserted along with CS causes an internal latch to be set Once this latch is set
an access will start from the positive clock edge of CLK as soon as possible In Mode
1 the input functions as ADS and when asserted along with CS causes the access
RAS to assert if no other event is taking place If an event is taking place RAS will be
asserted from the positive edge of CLK as soon as possible In both cases the low
going edge of this signal latches the bank row and column address if programmed to
do so

CHIP SELECT

This input signal must be asserted to enable a Port A access

AREQ

ACCESS REQUEST

This input signal in Mode 0 must be asserted some time after

the first positive clock edge after ALE has been asserted When this signal is
negated RAS is negated for the access In Mode 1 this signal must be asserted
before ADS can be negated When this signal is negated RAS is negated for the
access

WAIT

or DTACK This output can be programmed to insert wait states into a CPU

access cycle With R7 negated during programming the output will function as a

(DTACK)

WAIT type output In this case the output will be active low to signal a wait condition
With R7 asserted during programming the output will function as DTACK In this
case the output will be negated to signify a wait condition and will be asserted to
signify the access has taken place Each of these signals can be delayed by a
number of positive clock edges or negative clock levels of CLK to increase the
microprocessor's access cycle through the insertion of wait states

WAITIN

WAIT INCREASE

This input can be used to dynamically increase the number of

positive clock edges of CLK until DTACK will be asserted or WAIT will be negated
during a DRAM access

2 0 Signal Descriptions

(Continued)

Device (If not

Input

Description

Name

Applicable to All)

Output

2 5 PORT B ACCESS SIGNALS

AREQB

DP8422A

PORT B ACCESS REQUEST

This input asserted will latch the row column and bank

address if programmed and requests an access to take place for Port B If the

only

access can take place RAS will assert immediately If the access has to be delayed
RAS will assert as soon as possible from a positive edge of CLK

ATACKB

DP8422A

ADVANCED TRANSFER ACKNOWLEDGE PORT B

This output is asserted when

the access RAS is asserted for a Port B access This signal can be used to generate

only

the appropriate DTACK or WAIT type signal for Port B's CPU or bus

2 6 COMMON DUAL PORT SIGNALS

GRANTB

DP8422A

GRANT B

This output indicates which port is currently granted access to the DRAM

array When GRANTB is asserted Port B has access to the array When GRANTB is

only

negated Port A has access to the DRAM array This signal is used to multiplex the
signals R0 8 9 10 C0 8 9 10 B0 1 WIN LOCK and ECAS0 3 to the DP8422A
when using dual accessing

LOCK

DP8422A

LOCK

This input can be used by the currently granted port to ``lock out'' the other

port from the DRAM array by inserting wait states into the locked out port's access

only

cycle until LOCK is negated

2 7 POWER SIGNALS AND CAPACITOR INPUT

POWER

Supply Voltage

GND

GROUND

Supply Voltage Reference

CAP

CAPACITOR

This input is used by the internal PLL for stabilization The value of the

ceramic capacitor should be 0 1 mF and should be connected between this input and
ground

2 8 CLOCK INPUTS

There are two clock inputs to the DP8420A 21A 22A CLK and DELCLK These two clocks may both be tied to the same clock
input or they may be two separate clocks running at different frequencies asynchronous to each other

CLK

SYSTEM CLOCK

This input may be in the range of 0 Hz up to 25 MHz This input is

generally a constant frequency but it may be controlled externally to change
frequencies or perhaps be stopped for some arbitrary period of time
This input provides the clock to the internal state machine that arbitrates between
accesses and refreshes This clock's positive edges and negative levels are used to
extend the WAIT (DTACK) signals Ths clock is also used as the reference for the
RAS precharge time and RAS low time during refresh
All Port A and Port B accesses are assumed to be synchronous to the system clock
CLK

DELCLK

DELAY LINE CLOCK

The clock input DELCLK may be in the range of 6 MHz to

20 MHz and should be a multiple of 2 (i e 6 8 10 12 14 16 18 20 MHz) to have
the DP8420A 21A 22A switching characteristics hold If DELCLK is not one of the
above frequencies the accuracy of the internal delay line will suffer This is because
the phase locked loop that generates the delay line assumes an input clock
frequency of a multiple of 2 MHz
For example if the DELCLK input is at 7 MHz and we choose a divide by 3 (program
bits C0 2) this will produce 2 333 MHz which is 16 667% off of 2 MHz Therefore the
DP8420A 21A 22A delay line would produce delays that are shorter (faster delays)
than what is intended If divide by 4 was chosen the delay line would be longer
(slower delays) than intended (1 75 MHz instead of 2 MHz) (See Section 10 for more
information )
This clock is also divided to create the internal refresh clock

3 0 Programming and Resetting

Due to the variety in power supplies power-up times the
internal power up reset circuit may not work in every design
therefore an EXTERNAL RESET must be performed before
the DRAM controller can be programmed and used

After

going

through

the

reset

procedure

the

DP8420A 21A 22A can be programmed by either of two
methods Mode Load Only Programming or Chip Select Ac-
cess Programming After programming the DRC for the first
time after reset the chip enters a 60 ms initialization period
during this period the controller performs refreshes every
13 ms or 15 ms this makes further DRAM warm up cycles
unnecessary

After this stage the chip can be repro-

grammed as many times as the user wishes and the 60 ms
period will not be entered into unless the chip is reset and
programmed again

During the 60 ms initialization period RFIP is asserted low
and RAS toggles every 13 ms or 15 ms depending on the
programming bit for refresh (C3) CAS will be inactive (logic
1) and the ``Q'' outputs will count from 0 to 2047 refreshing
the entire DRAM array The actual initialization time period
is given by the following formula T

4096 (Clock Divisor

Select) (Refresh Clock Fine Tune) (DELCLK Frq )

3 1 EXTERNAL RESET

At power up if the internal power up reset worked all inter-
nal latches and flip-flops are cleared and the part is ready to
be programmed The power up state can also be achieved
by performing an External Reset which is required to insure
proper operation External Reset is achieved by asserting
ML and DISRFSH for at least 16 positive clock edges In
order to perform simply a Reset the ML signal must be
negated before DISRFSH is negated as shown in

Figure 5a

This procedure will only reset the controller which now is
ready for programming

While performing an External Reset if the user negates
DISRFSH at least one clock period before negating ML as
shown in

Figure 5b

ML negated will program the

DP8420A 21A 22A with the values in R0 9 C0 9 B0 1
and ECAS0 The 60 ms initialization period will be entered
since it is the first programming after reset This is a good
way of resetting and programming the part at the same time
Make sure the right programming bits are on the address
lines before ML is negated

The DRC may be Reset and programmed any time on the
fly but the user must make sure that No Access or Refresh
is in progress

TL F 8588 E1

FIGURE 5a Chip Reset but Not Programmed

TL F 8588 E2

FIGURE 5b Chip Reset and Programmed

3 0 Programming and Resetting

(Continued)

3 2 PROGRAMMING METHODS

3 2 1 Mode Load Only Programming

To use this method the user asserts ML enabling the inter-
nal programming register After ML is asserted a valid pro-
gramming selection is placed on the address bus B0 B1
and ECAS0 inputs then ML is negated When ML is negat-
ed the programming bits are latched into the internal pro-
gramming register and the DP8420A 21A 22A is pro-
grammed see

Figure 6 When programming the chip the

controller must not be refreshing RFIP must be high (1) to
have a successful programming

3 2 2 Chip Selected Access Programming

The chip can also be programmed by performing a chip
selected access To program the chip using this method
ML is asserted then CS is asserted and a valid program-
ming selection is placed on the address bus When AREQ is
asserted the programming bits affecting the wait logic be-
come effective immediately then DTACK is asserted allow-
ing the access to terminate After the access ML is negated
and the rest of the programming bits take effect

TL F 8588 G3

FIGURE 6 ML Only Programming

TL F 8588 G4

FIGURE 7 CS Access Programming

3 0 Programming and Resetting

(Continued)

3 3 PROGRAMMING BIT DEFINITIONS

Symbol

Description

ECAS0

Extend CAS Refresh Request Select

The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8422A only) is negated
The WE output pin will function as write enable

The CASn outputs will be negated during an acccess (Port A (or Port B DP8422A only)) when their
corresponding ECASn inputs are negated This feature allows the CAS outputs to be extended beyond the RAS
outputs negating Scrubbing refreshes are NOT affected During scrubbing refreshes the CAS outputs will negate
along with the RAS outputs regardless of the state of the ECAS inputs

The WE output will function as ReFresh ReQuest (RFRQ) when this mode is programmed

Access Mode Select

ACCESS MODE 0

ALE pulsing high sets an internal latch On the next positive edge of CLK the access (RAS)

will start AREQ will terminate the access

ACCESS MODE 1

ADS asserted starts the access (RAS) immediately AREQ will terminate the access

Address Latch Mode

ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input row
column and bank address

The row column and bank latches are fall through

Delay CAS during WRITE Accesses

CAS is treated the same for both READ and WRITE accesses

During WRITE accesses CAS will be asserted by the event that occurs last CAS asserted by the internal delay
line or CAS asserted on the positive edge of CLK after RAS is asserted

Row Address Hold Time

25 ns minimum

Row Address Hold Time

15 ns minimum

Column Address Setup Time

10 ns miniumum

Column Address Setup Time

0 ns minimum

C6 C5 C4

RAS and CAS Configuration Modes Error Scrubbing during Refresh

0 0 0

RAS0 3 and CAS0 3 are all selected during an access ECASn must be asserted for CASn to be asserted
B0 and B1 are not used during an access Error scrubbing during refresh

0 0 1

RAS and CAS pairs are selected during an access by B1 ECASn must be asserted for CASn to be asserted
B1

0 during an access selects RAS0 1 and CAS0 1

1 during an access selects RAS2 3 and CAS2 3

B0 is not used during an Access
Error scrubbing during refresh

0 1 0

RAS and CAS singles are selected during an access by B0 1 ECASn must be asserted for CASn to be asserted
B1

0 B0

0 during an access selects RAS0 and CAS0

0 B0

1 during an access selects RAS1 and CAS1

1 B0

0 during an access selects RAS2 and CAS2

1 B0

1 during an access selects RAS3 and CAS3

Error scrubbing during refresh

0 1 1

RAS0 3 and CAS0 3 are all selected during an access ECASn must be asserted for CASn to be asserted
B1 B0 are not used during an access
No error scrubbing (RAS only refreshing)

1 0 0

RAS pairs are selected by B1 CAS0 3 are all selected ECASn must be asserted for CASn to be asserted
B1

0 during an access selects RAS0 1 and CAS0 3

1 during an access selects RAS2 3 and CAS0 3

B0 is not used during an access
No error scrubbing

3 0 Programming and Resetting

(Continued)

3 3 PROGRAMMING BIT DEFINITIONS

(Continued)

Symbol

Description

C6 C5 C4

RAS and CAS Configuration Modes

(Continued)

1 0 1

RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be asserted
B1

0 during an access selects RAS0 1 and CAS0 1

1 during an access selects RAS2 3 and CAS2 3

B0 is not used during an access
No error scrubbing

1 1 0

RAS singles are selected by B0 1 CAS0 3 are all selected ECASn must be asserted for CASn to be
asserted
B1

0 B0

0 during an access selects RAS0 and CAS0 3

0 B0

1 during an access selects RAS1 and CAS0 3

1 B0

0 during an access selects RAS2 and CAS0 3

1 B0

1 during an access selects RAS3 and CAS0 3

No error scrubbing

1 1 1

RAS and CAS singles are selected by B0 1 ECASn must be asserted for CASn to be asserted
B1

0 B0

0 during an access selects RAS0 and CAS0

0 B0

1 during an access selects RAS1 and CAS1

1 B0

0 during an access selects RAS2 and CAS2

1 B0

1 during an access selects RAS3 and CAS3

No error scrubbing

Refresh Clock Fine Tune Divisor

Divide delay line refresh clock further by 30 (If DELCLK Refresh Clock Clock Divisor

2 MHz

15 ms

refresh period)

Divide delay line refresh clock further by 26 (If DELCLK Refresh Clock Clock Divisor

2 MHz

13 ms

refresh period)

C2 C1 C0

Delay Line Refresh Clock Divisor Select

0 0 0

Divide DELCLK by 10 to get as close to 2 MHz as possible

0 0 1

Divide DELCLK by 9 to get as close to 2 MHz as possible

0 1 0

Divide DELCLK by 8 to get as close to 2 MHz as possible

0 1 1

Divide DELCLK by 7 to get as close to 2 MHz as possible

1 0 0

Divide DELCLK by 6 to get as close to 2 MHz as possible

1 0 1

Divide DELCLK by 5 to get as close to 2 MHz as possible

1 1 0

Divide DELCLK by 4 to get as close to 2 MHz as possible

1 1 1

Divide DELCLK by 3 to get as close to 2 MHz as possible

Refresh Mode Select

RAS0 3 will all assert and negate at the same time during a refresh

Staggered Refresh RAS outputs during refresh are separated by one positive clock edge Depending on the
configuration mode chosen either one or two RASs will be asserted

Address Pipelining Select

Address pipelining is selected The DRAM controller will switch the DRAM column address back to the row
address after guaranteeing the column address hold time

Non-address pipelining is selected The DRAM controller will hold the column address on the DRAM address
bus until the access RASs are negated

WAIT or DTACK Select

WAIT type output is selected

DTACK (Data Transfer ACKnowledge) type output is selected

Add Wait States to the Current Access if WAITIN is Low

WAIT or DTACK will be delayed by one additional positive edge of CLK

WAIT or DTACK will be delayed by two additional positive edges of CLK

3 0 Programming and Resetting

(Continued)

3 3 PROGRAMMING BIT DEFINITIONS

(Continued)

Symbol

Description

R5 R4

WAIT DTACK during Burst (See Section 5 1 2 or 5 2 2)

0 0

NO WAIT STATES If R7

0 during programming WAIT will remain negated during burst portion of access

If R7

1 programming DTACK will remain asserted during burst portion of access

0 1

1T If R7

0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted

WAIT will negate from the positive edge of CLK after the ECASs have been asserted
If R7

1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted

DTACK will assert from the positive edge of CLK after the ECASs have been asserted

1 0

T If R7

0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted

WAIT will negate on the negative level of CLK after the ECASs have been asserted
If R7

1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted

DTACK will assert from the negative level of CLK after the ECASs have been asserted

1 1

0T If R7

0 during programming WAIT will assert when the ECAS inputs are negated WAIT will negate when

the ECAS inputs are asserted
If R7

1 during programming DTACK will negate when the ECAS inputs are negated DTACK will assert when

the ECAS inputs are asserted

R3 R2

WAIT DTACK Delay Times (See Section 5 1 1 or 5 2 1)

0 0

NO WAIT STATES If R7

0 during programming WAIT will remain high during non-delayed accesses WAIT

will negate when RAS is negated during delayed accesses
NO WAIT STATES If R7

1 during programming DTACK will be asserted when RAS is asserted

0 1

T If R7

0 during programming WAIT will negate on the negative level of CLK after the access RAS

1T If R7

1 during programming DTACK will be asserted on the positive edge of CLK after the access RAS

1 0

NO WAIT STATES

T If R7

0 during programming WAIT will remain high during non-delayed accesses

WAIT will negate on the negative level of CLK after the access RAS during delayed accesses

T If R7

1 during programming DTACK will be asserted on the negative level of CLK after the access RAS

1 1

1T If R7

0 during programming WAIT will negate on the positive edge of CLK after the access RAS

T If R7

1 during programming DTACK will be asserted on the negative level of CLK after the positive edge

of CLK after the access RAS

R1 R0

RAS Low and RAS Precharge Time

0 0

RAS asserted during refresh

2 positive edges of CLK

RAS precharge time

1 positive edge of CLK

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422A)

0 1

RAS asserted during refresh

3 positive edges of CLK

RAS precharge time

2 positive edges of CLK

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422A)

1 0

RAS asserted during refresh

2 positive edges of CLK

RAS precharge time

2 positive edges of CLK

RAS will start from the first positive edge of CLK after GRANTB transitions (DP8422A)

1 1

RAS asserted during refresh

4 positive edges of CLK

RAS precharge time

3 positive edges of CLK

RAS will start from the second positive edge of CLK after GRANTB transitions (DP8422A)

4 0 Port A Access Modes

The DP8420A 21A 22A have two general purpose access
modes Mode 0 RAS synchronous and Mode 1 RAS asyn-
chronous One of these modes is selected at programming
through the B1 input A Port A access to DRAM is initiated
by two input signals ADS (ALE) and CS The access is al-
ways terminated by one signal AREQ These input signals
should be synchronous to the input clock

4 1 ACCESS MODE 0

Mode 0 synchronous access is selected by negating the
input B1 during programming (B1

0) To initiate a Mode 0

access ALE is pulse high and CS is asserted If precharge
time was met a refresh of DRAM or a Port B access was
not in progress the RAS (RASs) would be asserted on the

first rising edge of clock If a refresh or a Port B access is in
progress or precharge time is required the controller will
wait until these events have taken place and assert RAS
(RASs) on the next positive edge of clock

Sometime after the first positive edge of clock after ALE and
CS have been asserted the input AREQ must be asserted
In single port applications once AREQ is asserted CS can
be negated On the other hand ALE can stay asserted sev-
eral periods of clock however ALE must be negated before
or during the period of CLK in which AREQ is negated

The controller samples AREQ on the every rising edge of
clock after DTACK is asserted The access will end when
AREQ is sampled negated

TL F 8588 60

FIGURE 8a Access Mode 0

4 0 Port A Access Modes

(Continued)

4 2 ACCESS MODE 1

Mode 1 asynchronous access is selected by asserting the
input B1 during programming (B1

1) This mode allows ac-

cesses to start immediately from the access request input
ADS To initiate a Mode 1 access CS is asserted followed
by ADS asserted If precharge time was met a refresh of
the DRAM or a Port B access was not in progress the RAS
(RASs) would be asserted from ADS being asserted If a
refresh or Port B access is in progress or precharge time is
required the controller will wait until these events have tak-

en place and assert RAS (RASs) from the next rising edge
of clock

When ADS is asserted or sometime after AREQ must be
asserted At this time ADS can be negated and AREQ will
continue the access Also ADS can continue to be asserted
after AREQ has been asserted and negated however a
new access will not start until ADS is negated and asserted
again When address pipelining is not implemented ADS
and AREQ can be tied together

The access will end when AREQ is negated

TL F 8588 62

FIGURE 8b Access Mode 1

4 0 Port A Access Modes

(Continued)

4 4 READ-MODIFY-WRITE CYCLES WITH EITHER ACCESS MODE

There are 2 methods by which this chip can be used to do
read-modify-write access cycles The first method involves
doing a late write access where the WIN input is asserted
some delay after CAS is asserted The second method in-
volves doing a page mode read access followed by a page
mode write access with RAS held low (see

Figure 9c )

CASn must be toggled using the ECASn inputs and WIN has
to be changed from negated to asserted (read to write)
while CAS is negated This method is better than changing

WIN from negated to asserted in a late write access be-
cause here a problem may arise with DATA IN and DATA
OUT being valid at the same time This may result in a data
line trying to drive two different levels simultaneously The
page mode method of a read-modify-write access allows
the user to have transceivers in the system because the
data in (read data) is guaranteed to be high impedance dur-
ing the time the data out (write data) is valid

TL F 8588 G2

There may be idle states inserted here by the CPU

FIGURE 9c Read-Modify-Write Access Cycle

4 0 Port A Access Modes

(Continued)

4 5 ADDITIONAL ACCESS SUPPORT FEATURES

support

the

different

modes

accessing

the

DP8420A 21A 22A offer other access features These ad-
ditional features include Address Latches and Column In-
crement (for page burst mode support) Address Pipelining
and Delay CAS (to allow the user with a multiplexed bus to
ensure valid data is present before CAS is asserted)

4 5 1 Address Latches and Column Increment

The Address Latches can be programmed through pro-
gramming bit B0 They can be programmed to either latch
the address or remain in a fall-through mode If the address
latches are used to latch the address the controller will
function as follows

In Mode 0 the rising edge of ALE places the latches in fall-
through once ALE is negated the address present in the
row column and bank input is latched

In Mode 1 the address latches are in fall through mode until
ADS is asserted ADS asserted latches the address

Once the address is latched the column address can be
incremented with the input COLINC COLINC can be used
for sequential accesses of static column DRAMs COLINC
can also be used with the ECAS inputs to support sequen-
tial accesses to page mode DRAMs as shown in

Figure 10

COLINC should only be asserted when the signal RFIP is
negated during an access since this input functions as ex-
tended refresh when RFIP is asserted COLINC must be
negated (0) when the address is being latched (ADS falling
edge in Mode 1) If COLINC is asserted with all of the bits of
the column address asserted (ones) the column address
will return to zero

TL F 8588 C4

FIGURE 10 Column Increment

The address latches function differently with the DP8422A
The DP8422A will latch the address of the currently granted
port If Port A is currently granted the address will be
latched as described in Section 4 5 1 If Port A is not grant-
ed and requests an access the address will be latched on
the first or second positive edge of CLK after GRANTB has
been negated depending on the programming bits R0 R1

For Port B if GRANTB is asserted the address will be
latched with AREQB asserted If GRANTB is negated the
address will latch on the first or second positive edge of
CLK after GRANTB is asserted depending on the program-
ming bits R0 R1

4 0 Port A Access Modes

(Continued)

4 5 2 Address Pipelining

Address pipelining is the overlapping of accesses to differ-
ent banks of DRAM If the majority of successive accesses
are to a different bank the accesses can be overlapped
Because of this overlapping the cycle time of the DRAM
accesses are greatly reduced The DP8420A 21A 22A can
be programmed to allow a new row address to be placed on
the DRAM address bus after the column address hold time
has been met At this time a new access can be initiated
with ADS or ALE depending on the access mode while
AREQ is used to sustain the current access The DP8422A
supports address pipelining for Port A only This mode can-
not be used with page static column or nibble modes of
operations because the DRAM column address is switched
back to the row address after CAS is asserted This mode is
programmed through address bit R8 (see

Figures 11a and

11b ) In this mode the output WE always functions as

RFRQ

During address pipelining in Mode 0 shown in

Figure 11c

ALE cannot be pulsed high to start another access until
AREQ has been asserted for the previous access for at
least one period of CLK DTACK if programmed will be
negated once AREQ is negated WAIT if programmed to
insert wait states will be asserted once ALE and CS are
asserted

In Mode 1 shown in

Figure 11d ADS can be negated once

AREQ is asserted After meeting the minimum negated
pulse width for ADS ADS can again be asserted to start a
new access DTACK if programmed will be negated once
AREQ is negated WAIT if programmed will be asserted
once ADS is asserted

In either mode with either type of wait programmed the
DP8420A 21A 22A will still delay the access for precharge
if sequential accesses are to the same bank or if a refresh
takes place

TL F 8588 G0

FIGURE 11a Non-Address Pipelined Mode

TL F 8588 G1

FIGURE 11b Address Pipelined Mode

5 0 Refresh Options

The DP8420A 21A 22A support three refresh control mode
options

1 Automatic Internally Controlled Refresh

2 Externally Controlled Burst Refresh

3 Refresh Request Acknowledge

With each of the control modes above three types of re-
fresh can be performed

1 All RAS Refresh

2 Staggered Refresh

3 Error Scrubbing During All RAS Refresh

There are three inputs EXTNDRF RFSH and DISRFSH
and two outputs RFIP and RFRQ associated with refresh
There are also ten programming bits R0 1 R9 C0 6 and
ECAS0 used to program the various types of refreshing

Asserting the input EXTNDRF extends the refresh cycle for
a single or multiple integral periods of CLK

The output RFIP is asserted one period of CLK before the
first refresh RAS is asserted If an access is currently in
progress RFIP will be asserted up to one period of CLK
before the first refresh RAS after AREQ or AREQB is nega-
ted for the access (see

Figure 13 )

The DP8420A 21A 22A will increment the refresh address
counter automatically independent of the refresh mode
used The refresh address counter will be incremented once
all the refresh RASs have been negated

In every combination of refresh control mode and refresh
type the DP8420A 21A 22A is programmed to keep RAS
asserted a number of CLK periods The time values of RAS
low during refresh are programmed through programming
bits R0 and R1

5 1 REFRESH CONTROL MODES

5 1 1 Automatic Internal Refresh

The DP8420A 21A 22A have an internal refresh clock The
period of the refresh clock is generated from the program-
ming bits C0 3 Every period of the refresh clock an inter-
nal refresh request is generated As long as a DRAM ac-
cess is not currently in progress and precharge time has
been met the internal refresh request will generate an auto-
matic internal refresh If a DRAM access is in progress the
DP8420A 21A 22A on-chip arbitration logic will wait until
the access is finished before performing the refresh The
refresh access arbitration logic can insert a refresh cycle
between two address pipelined accesses However the re-
fresh arbitration logic can not interrupt an access cycle to
perform a refresh To enable automatic internally controlled
refreshes the input DISRFSH must be negated

TL F 8588 F8

Explanation of Terms

RFRQ

ReFresh ReQuest internal to the DP8420A 21A 22A RFRQ has the ability to hold off a pending access

RFSH

Externally requested ReFreSH

RFIP

ReFresh in Progress

ACIP

Port A or Port B (DP8422A only) ACcess in Progress This means that either RAS is low for an access or is in the process of
transitioning low for an access

FIGURE 13 DP8420A 21A 22A Access Refresh Arbitration State Program

5 0 Refresh Options

(Continued)

5 1 2 Externally Controlled Burst Refresh

To use externally controlled burst refresh the user must
disable the automatic internally controlled refreshes by as-
serting the input DISRFSH The user is responsible for gen-
erating the refresh request by asserting the input RFSH
Pulsing RFSH low sets an internal latch that is used to
produce the internal refresh request The refresh cycle will

take place on the next positive edge of CLK as shown in

Figure 14a If an access to DRAM is in progress or pre-

charge time for the last access has not been met the re-
fresh will be delayed Since pulsing RFSH low sets a latch
the user does not have to keep RFSH low until the refresh
starts When the last refresh RAS negates the internal re-
fresh request latch is cleared

TL F 8588 64

FIGURE 14a Single External Refreshes (2 Periods of RAS Low during Refresh Programmed)

By keeping RFSH asserted past the positive edge of CLK
which ends the refresh cycle as shown in

Figure 14b the

user will perform another refresh cycle Using this tech-
nique the user can perform a burst refresh consisting of any
number of refresh cycles Each refresh cycle during a burst
refresh will meet the refresh RAS low time and the RAS
precharge time (programming bits R0 1)

If the user desires to burst refresh the entire DRAM (all row
addresses) he could generate an end of count signal (burst
refresh

finished)

looking

one

the

DP8420A 21A 22A high address outputs (Q7 Q8 Q9 or
Q10) and the RFIP output The Qn outputs function as a
decode of how many row addresses have been refreshed
(Q7

128 refreshes Q8

256 refreshes Q9

512 re-

freshes Q10

1024 refreshes)

TL F 8588 65

FIGURE 14b External Burst Refresh (2 Periods of RAS Precharge

2 Periods of Refresh RAS Low during Refresh Programmed)

5 0 Refresh Options

(Continued)

5 1 3 Refresh Request Acknowledge

The DP8420A 21A 22A can be programmed to output in-
ternal refresh requests When the user programs ECAS0
negated (1) and or address pipelining mode is selected the
WE output functions as RFRQ RFRQ (WE) will be asserted
by one of two events

First when the external circuitry pulses low the input RFSH
which will request an external refresh

Second when the internal refresh clock has expired which
signals that another refresh is needed

An example of the first case where an external refresh is
requested while RFRQ is negated (1) is shown in

Figure

15a Notice that RFRQ will be asserted from a positive edge

of clock

On the second case when the RFRQ is asserted from the
expiration of the internal refresh clock the user has two
options

First if DISRFSH is negated an automatic internal refresh
will take place See

Figure 15b

Second with DISRFSH asserted RFRQ will stay asserted
until RFSH is pulsed low This option will cause an external-
ly requested burst refresh to take place See

Figure 15c

RFRQ will go high and then assert (toggle) if additional peri-
ods of the internal refresh clock have expired and neither an
externally controlled refresh nor an automatically controlled
internal refresh have taken place see

Figure 15d If a time

critical event or long accesses like page static column
mode can not be interrupted RFRQ pulsing high can be
used to increment a counter This counter can be used to
perform a burst refresh of the number of refreshes missed
(through the RFSH input)

TL F 8588 66

FIGURE 15a Externally Controlled Single and Burst Refresh with Refresh Request

(RFRQ) Output (2 Periods of RAS Low during Refresh Programmed)

TL F 8588 67

FIGURE 15b Automatic Internal Refresh with Refresh Request (3T of RAS Low during Refresh Programmed)

5 0 Refresh Options

(Continued)

5 2 REFRESH CYCLE TYPES

Three different types of refresh cycles are available for use
The three different types are mutually exclusive and can be
used with any of the three modes of refresh control The
three different refresh cycle types are all RAS refresh stag-
gered RAS refresh and error scrubbing during all RAS re-
fresh In all refresh cycle types the RAS precharge time is
guaranteed between the previous access RAS ending and
the refresh RAS0 starting between refresh RAS3 ending
and access RAS beginning between burst refresh RASs

5 2 1 Conventional RAS Refresh

A conventional refresh cycle causes RAS0 3 to all assert
from the first positive edge of CLK after RFIP is asserted as
shown in

Figure 16 RAS0 3 will stay asserted until the

number of positive edges of CLK programmed have passed
On the last positive edge RAS0 3 and RFIP will be negat-
ed This type of refresh cycle is programmed by negating
address bit R9 during programming

TL F 8588 69

FIGURE 16 Conventional RAS Refresh

5 2 2 Staggered RAS Refresh

A staggered refresh staggers each RAS or group of RASs
by a positive edge of CLK as shown in

Figure 17 The num-

ber of RASs which will be asserted on each positive edge
of CLK is determined by the RAS CAS configuration mode
programming bits C4 C6 If single RAS outputs are select-
ed during programming then each RAS will assert on suc-
cessive positive edges of CLK If two RAS outputs are se-
lected during programming then RAS0 and RAS1 will assert

on the first positive edge of CLK after RFIP is asserted
RAS2 and RAS3 will assert on the second positive edge of
CLK after RFIP is asserted If all RAS outputs were selected
during programming all RAS outputs would assert on the
first positive edge of CLK after RFIP is asserted Each RAS
or group of RASs will meet the programmed RAS low time
and then negate

TL F 8588 70

FIGURE 17 Staggered RAS Refresh

5 0 Refresh Options

(Continued)

5 2 3 Error Scrubbing during Refresh

The DP8420A 21A 22A support error scrubbing during all
RAS DRAM refreshes Error scrubbing during refresh is se-
lected through bits C4 C6 with bit R9 negated during pro-
gramming Error scrubbing can not be used with staggered
refresh (see Section 8 0) Error scrubbing during refresh al-
lows a CAS or group of CASs to assert during the all RAS
refresh as shown in

Figure 18 This allows data to be read

from the DRAM array and passed through an Error Detec-
tion And Correction Chip EDAC If the EDAC determines
that the data contains a single bit error and corrects that
error the refresh cycle can be extended with the input ex-

tend refresh EXTNDRF and a read-modify-write operation
can be performed by asserting WE It is the responsibility of
the designer to ensure that WE is negated The DP8422A
has a 24-bit internal refresh address counter that contains
the 11 row

11 column and 2 bank addresses

The

DP8420A 21A have a 22-bit internal refresh address coun-
ter that contains the 10 row 10 column and 2 bank address-
es These counters are configured as bank column row
with the row address as the least significant bits The bank
counter bits are then used with the programming selection
to determine which CAS or group of CASs will assert during
a refresh

TL F 8588 46

FIGURE 18 Error Scrubbing during Refresh

5 0 Refresh Options

(Continued)

5 3 EXTENDING REFRESH

The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple peri-
ods of CLK Only the all RAS (with or without error scrub-
bing) type of refresh can be extended To extend a refresh
cycle the input extend refresh EXTNDRF must be assert-
ed before the positive edge of CLK that would have negated
all the RAS outputs during the refresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown in

Figure 19 This will extend the refresh to

the next positive edge of CLK and EXTNDRF will be sam-
pled again The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK

5 4 CLEARING THE REFRESH ADDRESS COUNTER

The refresh address counter can be cleared by asserting
RFSH while DISRFSH is negated as shown in

Figure 20a

This can be used prior to a burst refresh of the entire memo-
ry array By asserting RFSH one period of CLK before
DISRFSH is asserted and then keeping both inputs assert-
ed the DP8420A 21A 22A will clear the refresh address
counter and then perform refresh cycles separated by the
programmed value of precharge as shown in

Figure 20b An

end-of-count signal can be generated from the Q DRAM
address outputs of the DP8420A 21A 22A and used to ne-
gate RFSH

TL F 8588 71

FIGURE 19 Extending Refresh with the Extend Refresh (EXTNDRF) Input

TL F 8588 72

FIGURE 20a Clearing the Refresh Address Counter

TL F 8588 73

FIGURE 20b Clearing the Refresh Counter during Burst

5 0 Refresh Options

(Continued)

5 5 CLEARING THE REFRESH REQUEST CLOCK

The refresh request clock can be cleared by negating
DISRFSH and asserting RFSH for 500 ns one period of the
internal 2 MHz clock as shown in

Figure 21 By clearing the

refresh request clock the user is guaranteed that an inter-
nal refresh request will not be generated for approximately
15 ms one refresh clock period from the time RFSH is neg-
ated This action will also clear the refresh address counter

TL F 8588 75

FIGURE 21 Clearing the Refresh Request Clock Counter

6 0 Port A Wait State Support

Wait states allow a CPU's access cycle to be increased by
one or multiple CPU clock periods The wait or ready input is
named differently by CPU manufacturers However any
CPU's wait or ready input is compatible with either the WAIT
or DTACK output of the DP8420A 21A 22A The user de-
termines whether to program WAIT or DTACK (R7) and
which value to select for WAIT or DTACK (R2 R3) depend-
ing upon the CPU used and where the CPU samples its wait
input during an access cycle

The decision to terminate the CPU access cycle is directly
affected by the speed of the DRAMs used The system de-
signer must ensure that the data from the DRAMs will be
present for the CPU to sample or that the data has been
written to the DRAM before allowing the CPU access cycle
to terminate

The insertion of wait states also allows a CPU's access cy-
cle to be extended until the DRAM access has taken place
The DP8420A 21A 22A insert wait states into CPU access
cycles due to guaranteeing precharge time refresh current-
ly in progress user programmed wait states the WAITIN
signal being asserted and GRANTB not being valid
(DP8422A only) If one of these events is taking place and
the CPU starts an access the DP8420A 21A 22A will insert
wait states into the access cycle thereby increasing the

length of the CPU's access Once the event has been com-
pleted the DP8420A 21A 22A will allow the access to take
place and stop inserting wait states

There are six programming bits R2 R7 an input WAITIN
and an output that functions as WAIT or DTACK

6 1 WAIT TYPE OUTPUT

With the R7 address bit negated during programming the
user selects the WAIT output As long as WAIT is sampled
asserted by the CPU wait states (extra clock periods) are
inserted into the current access cycle as shown in

Figure

22 Once WAIT is sampled negated the access cycle is

completed by the CPU WAIT is asserted at the beginning of
a chip selected access and is programmed to negate a
number of positive edges and or negative levels of CLK
from the event that starts the access WAIT can also be
programmed to function in page burst mode applications
Once WAIT is negated during an access and the ECAS
inputs are negated with AREQ asserted WAIT can be pro-
grammed to toggle following the ECAS inputs Once AREQ
is negated ending the access WAIT will stay negated until
the next chip selected access For more details about WAIT
Type Output see Application Note AN-773

TL F 8588 76

FIGURE 22 WAIT Type Output

6 0 Port A Wait State Support

(Continued)

6 2 DTACK TYPE OUTPUT

With the R7 address bit asserted during programming the
user selects the DTACK type output As long as DTACK is
sampled negated by the CPU wait states are inserted into
the current access cycle as shown in

Figure 23 Once

DTACK is sampled asserted the access cycle is completed
by the CPU DTACK which is normally negated is pro-
grammed to assert a number of positive edges and or neg-
ative levels from the event that starts RAS for the access
DTACK can also be programmed to function during page
burst mode accesses Once DTACK is asserted and the
ECAS inputs are negated with AREQ asserted DTACK can
be programmed to negate and assert from the ECAS inputs
toggling to perform a page burst mode operation Once
AREQ is negated ending the access DTACK will be negat-
ed and stays negated until the next chip selected access
For more details about DTACK type output see Application
Note AN-773

6 3 DYNAMICALLY INCREASING THE
NUMBER OF WAIT STATES

The user can increase the number of positive edges of CLK
before DTACK is asserted or WAIT is negated With the
input WAITIN asserted the user can delay DTACK asserting
or WAIT negating either one or two more positive edges of
CLK The number of edges is programmed through address
bit R6 If the user is increasing the number of positive edges
in a delay that contains a negative level the positive edges
will be met before the negative level For example if the user
programmed DTACK of

asserting WAITIN

pro-

grammed as 2T would increase the number of positive edg-
es resulting in DTACK of 2

T as shown in

Figure 24a Simi-

larly WAITIN can increase the number of positive edges in
a page burst access WAITIN can be permanently asserted
in systems requiring an increased number of wait states
WAITIN can also be asserted and negated depending on
the type of access As an example a user could invert the
WRITE line from the CPU and connect the output to
WAITIN This could be used to perform write accesses with
1 wait state and read accesses with 2 wait states as shown
in

Figure 24b

TL F 8588 97

FIGURE 23 DTACK Type Output

TL F 8588 C1

FIGURE 24a WAITIN Example (DTACK is Sampled at the ``T3'' Falling Clock Edge)

6 0 Port A Wait State Support

(Continued)

TL F 8588 C2

FIGURE 24b WAITIN Example (WAIT is Sampled at the End of ``T2'')

6 4 GUARANTEEING RAS LOW TIME
AND RAS PRECHARGE TIME

The DP8420A 21A 22A will guarantee RAS precharge time
between accesses between refreshes and between ac-
cess and refreshes The programming bits R0 and R1 are
used to program combinations of RAS precharge time and
RAS low time referenced by positive edges of CLK RAS
low time is programmed for refreshes only During an ac-
cess the system designer guarantees the time RAS is as-
serted through the DP8420A 21A 22A wait logic Since in-
serting wait states into an access increases the length of
the CPU signals which are used to create ADS or ALE and
AREQ the time that RAS is asserted can be guaranteed

The

precharge

time

also

guaranteed

the

DP8420A 21A 22A Each RAS output has a separate posi-

tive edge of CLK counter AREQ is negated setup to a posi-
tive edge of CLK to terminate the access That positive
edge is 1T The next positive edge is 2T RAS will not be
asserted until the programmed number of positive edges of
CLK have passed as shown in

Figure 25 Once the pro-

grammed precharge time has been met RAS will be assert-
ed from the positive edge of CLK However since there is a
precharge counter per RAS an access using another RAS
will not be delayed Precharge time before a refresh is al-
ways referenced from the access RAS negating before
RAS0 for the refresh asserting After a refresh precharge
time is referenced from RAS3 negating for the refresh to
the access RAS asserting

TL F 8588 C3

FIGURE 25 Guaranteeing RAS Precharge (DTACK is Sampled at the ``T2'' Falling Clock Edge)

7 0 RAS and CAS Configuration Modes

The DP8420A 21A 22A allow the user to configure the
DRAM array to contain one two or four banks of DRAM
Depending on the functions used certain considerations
must be used when determining how to set up the DRAM
array Programming address bits C4 C5 and C6 along with
bank selects B0 1 and CAS enables ECAS0 3 deter-
mine which RAS or group of RASs and which CAS or group
of CASs will be asserted during an access Different memo-
ry schemes are described The DP8420A 21A 22A is spec-
ified driving a heavy load of 72 DRAMs representing four
banks of DRAM with 16-bit words and 2 parity bits The
DP8420A 21A 22A can drive more than 72 DRAMs but the
AC timing must be increased Since the RAS and CAS out-
puts are configurable all RAS and CAS outputs should be
used for the maximum amount of drive

7 1 BYTE WRITING

By selecting a configuration in which all CAS outputs are
selected during an access the ECAS inputs enable a single
or group of CAS outputs to select a byte (or bytes) in a word
size of up to 32 bits In this case the RAS outputs are used
to select which of up to 4 banks is to be used as shown in

Figures 26a and 26b In systems with a word size of 16 bits

the byte enables can be gated with a high order address bit
to produce four byte enables which gives an equivalent to 8
banks of 16-bit words as shown in

Figure 26d If less memo-

ry is required each CAS should be used to drive each nibble
in the 16-bit word as shown in

Figure 26c

TL F 8588 C9

FIGURE 26a DRAM Array Setup for 32-Bit System (C6 C5 C4

1 1 0 during Programming)

TL F 8588 D0

FIGURE 26b DRAM Array Setup for 32-Bit 1 Bank System (C6 C5 C4

0 0 0 Allowing Error Scrubbing

or C6 C5 C4

0 1 1 No Error Scrubbing during Programming)

7 0 RAS and CAS Configuration Modes

(Continued)

7 2 MEMORY INTERLEAVING

Memory interleaving allows the cycle time of DRAMs to be
reduced by having sequential accesses to different memory
banks Since the DP8420A 21A 22A have separate pre-
charge counters per bank sequential accesses will not be
delayed if the accessed banks use different RAS outputs
To ensure different RAS outputs will be used a mode is
selected where either one or two RAS outputs will be as-
serted during an access The bank select or selects B0 and
B1 are then tied to the least significant address bits caus-
ing a different group of RASs to assert during each sequen-
tial access as shown in

Figure 27 In this figure there should

be at least one clock period of all RAS's negated between
different RAS's being asserted to avoid the condition of a
CAS before RAS refresh cycle

7 3 ADDRESS PIPELINING

Address pipelining allows several access RASs to be as-
serted at once Because RASs can overlap each bank re-
quires either a mode where one RAS and one CAS are used
per bank as shown in

Figure 28a or where two RASs and

two CASs are used per bank as shown in

Figure 28b Byte

writing can be accomplished in a 16-bit word system if two
RASs and two CASs are used per bank In other systems
WEs (or external gating on the CAS outputs) must be used
to perform byte writing If WEs are used separate data in
and data out buffers must be used If the array is not layed
out this way a CAS to a bank can be low before RAS which
will cause a refresh of the DRAM not an access To take
full advantage of address pipelining memory interleaving is
used To memory interleave the least significant address
bits should be tied to the bank select inputs to ensure that
all ``back to back'' sequential accesses are not delayed
since different memory banks are accessed

TL F 8588 D3

FIGURE 27 Memory Interleaving (C6 C5 C4

1 1 0 during Programming)

7 0 RAS and CAS Configuration Modes

(Continued)

7 5 PAGE BURST MODE

In a static column page or burst mode system the least
significant bits must be tied to the column address in order
to ensure that the page burst accesses are to sequential
memory addresses as shown in

Figure 30

In a nibble

mode system the least significant bits must be tied to the
highest column and row address bits in order to ensure that
sequential address bits are the ``nibble'' bits for nibble mode
accesses

(Figure 30) The ECAS inputs may then be tog-

gled with the DP8420A 21A 22A's address latches in fall-
through mode while AREQ is asserted The ECAS inputs
can also be used to select individual bytes When using nib-
ble mode DRAMS the third and fourth address bits can be
tied to the bank select inputs to perform memory interleav-
ing In page or static column modes the two address bits
after the page size can be tied to the bank select inputs to
select a new bank if the page size is exceeded

TL F 8588 D8

See table below for row column

bank address bit map A0 A1 are used for byte addressing in this example

Addresses

Nibble Mode

Page Mode Static Column Mode Page Size

256 Bits Page

512 Bits Page

1024 Bits Page

2048 Bits Page

Column

C9 R9 e A2 A3

C0 7 e A2 9

C0 8 e A2 10

C0 9 e A2 11

C0 10 e A2 12

Address

C0 8 e X

C8 10 e X

C9 10 e X

C10 e X

Row

Address

A10

A11

A12

A13

A11

A12

A13

A14

Assume that the least significant address bits are used for byte addressing Given a 32-bit system A0 A1 would be
used for byte addressing

DON'T CARE the user can do as he pleases

Nibble mode values for R and C assume a system using 1 Mbit DRAMs

FIGURE 30 Page Static Column Nibble Mode System

8 0 Test Mode

Staggered refresh in combination with the error scrubbing
mode places the DP8420A 21A 22A in test mode In this
mode the 24-bit refresh counter is divided into a 13-bit and
11-bit counter During refreshes both counters are incre-
mented to reduce test time

9 0 DRAM Critical Timing
Parameters

The two critical timing parameters shown in

Figure 31 that

must be met when controlling the access timing to a DRAM
are the row address hold time t

RAH

and the column ad-

dress setup time t

ASC

Since the DP8420A 21A 22A con-

tain a precise internal delay line the values of these param-
eters can be selected at programming time These values
will also increase and decrease if DELCLK varies from
2 MHz

9 1 PROGRAMMABLE VALUES OF t

RAH

AND t

ASC

The DP8420A 21A 22A allow the values of t

RAH

and t

ASC

to be selected at programming time For each parameter
two choices can be selected t

RAH

the row address hold

time is measured from RAS asserted to the row address
starting to change to the column address The two choices
for t

RAH

are 15 ns and 25 ns programmable through ad-

dress bit C8

ASC

the column address setup time is measured from the

column address valid to CAS asserted The two choices for
t

ASC

are 0 ns and 10 ns programmable through address bit

9 2 CALCULATION OF t

RAH

AND t

ASC

There are two clock inputs to the DP8420A 21A 22A
These two clocks DELCLK and CLK can either be tied to-
gether to the same clock or be tied to different clocks run-
ning asynchronously at different frequencies

The clock input DELCLK controls the internal delay line
and refresh request clock DELCLK should be a multiple of
2 MHz If DELCLK is not a multiple of 2 MHz t

RAH

and t

ASC

will change The new values of t

RAH

and t

ASC

can be calcu-

lated by the following formulas

If t

RAH

was programmed to equal 15 ns then t

RAH

30 (((DELCLK Divisor)

2 MHz (DELCLK Frequency))

15 ns

If t

RAH

was programmed to equal 25 ns then t

RAH

30 (((DELCLK Divisor)

2 MHz (DELCLK Frequency))

25 ns

If t

ASC

was programmed to equal 0 ns then t

ASC

((DELCLK Divisor) 2 MHz (DELCLK Frequency))

15 ns

If t

ASC

was programmed to equal 10 ns then t

ASC

((DELCLK Divisor) 2 MHz (DELCLK Frequency))

15 ns

Since the values of t

RAH

and t

ASC

are increased or de-

creased the time to CAS asserted will also increase or de-
crease These parameters can be adjusted by the following
formula

Delay to CAS

Actual Spec

Actual t

RAH

Programmed t

RAH

Actual t

ASC

Programmed t

ASC

TL F 8588 E3

FIGURE 31 t

RAH

and t

ASC

10 0 Dual Accessing (DP8422A)

The DP8422A has all the functions previously described In
addition to those features the DP8422A also has the capa-
bilities to arbitrate among refresh Port A and a second port
Port B This allows two CPUs to access a common DRAM
array DRAM refresh has the highest priority followed by the
currently granted port The ungranted port has the lowest
priority The last granted port will continue to stay granted
even after the access has terminated until an access re-
quest is received from the ungranted port (see

Figure 32a )

The dual access configuration assumes that both Port A
and Port B are synchronous to the system clock If they are
not synchronous to the system clock they should be exter-
nally synchronized (Ex By running the access requests
through several Flip-Flops see

Figure 34a )

10 1 PORT B ACCESS MODE

Port B accesses are initiated from a single input AREQB
When AREQB is asserted an access request is generated
If GRANTB is asserted and a refresh is not taking place or
precharge time is not required RAS will be asserted when
AREQB is asserted Once AREQB is asserted it must stay
asserted until the access is over AREQB negated negates
RAS as shown in

Figure 32b Note that if ECAS0

1 during

programming the CAS outputs may be held asserted (be-
yond RASn negating) by continuing to assert the appropri-
ate ECASn inputs (the same as Port A accesses) If Port B
is not granted the access will begin on the first or second
positive edge of CLK after GRANTB is asserted (See R0
R1 programming bit definitions) as shown in

Figure 32c as-

suming that Port A is not accessing the DRAM (CS ADS
ALE and AREQ) and RAS precharge for the particular bank

has completed It is important to note that for GRANTB to
transition to Port B Port A must not be requesting an ac-
cess at a rising clock edge (or locked) and Port B must be
requesting an access at that rising clock edge Port A can
request an access through CS and ADS ALE or CS and
AREQ Therefore during an interleaved access where CS
and ADS ALE become asserted before AREQ from the pre-
vious access is negated Port A will retain GRANTB

whether AREQB is asserted or not

Since there is no chip select for Port B AREQB must incor-
porate this signal This mode of accessing is similar to Mode
1 accessing for Port A

TL F 8588 F9

Explanation of Terms

AREQA

Chip Selected access request from Port A

AREQB

Chip Selected access request from Port B

LOCK

Externally controlled LOCKing of the Port

that is currently GRANTed

FIGURE 32a DP8422A Port A Port B Arbitration

State Diagram This arbitration may take place

during the ``ACCESS'' or ``REFRESH''

state (see

Figure 13a )

TL F 8588 E4

FIGURE 32b Access Request for Port B

TL F 8588 E5

FIGURE 32c Delayed Port B Access

10 0 Dual Accessing (DP8422A)

(Continued)

10 2 PORT B WAIT STATE SUPPORT

Advanced transfer acknowledge for Port B ATACKB is
used for wait state support for Port B This output will be
asserted when RAS for the Port B access is asserted as
shown in

Figures 33a and 33b Once asserted this output

will stay asserted until AREQB is negated With external
logic ATACKB can be made to interface to any CPU's wait
input as shown in

Figure 33c

10 3 COMMON PORT A AND PORT B DUAL PORT
FUNCTIONS

An input LOCK and an output GRANTB add additional
functionality to the dual port arbitration logic LOCK allows

Port A or Port B to lock out the other port from the DRAM
When a Port is locked out of the DRAM wait states will be
inserted into its access cycle until it is allowed to access
memory GRANTB is used to multiplex the input control sig-
nals and addresses to the DP8422A

10 3 1 GRANTB Output

The output GRANTB determines which port has current ac-
cess to the DRAM array GRANTB asserted signifies Port B
has access GRANTB negated signifies Port A has access
to the DRAM array

TL F 8588 E6

FIGURE 33a Non-Delayed Port B Access

TL F 8588 E7

FIGURE 33b Delayed Port B Access

TL F 8588 30

A Extend ATACK to

T (

Clock) after RAS goes low

TL F 8588 31

B Extend ATACK to 1T after RAS goes low

TL F 8588 32

C Synchronize ATACKB to CPU B Clock This is useful if CPU B runs asynchronous to the DP8422

FIGURE 33c Modifying Wait Logic for Port B

11 0 Absolute Maximum Ratings

(Note 1)

If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications

Temperature under Bias

0 C to

70 C

Storage Temperature

65 C to

150 C

All Input or Output Voltage

with Respect to GND

0 5V to

Power Dissipation

20 MHz

0 5W

ESD Rating to be determined

12 0 DC Electrical Characteristics

0 C to

70 C V

10% GND

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Logical 1 Input Voltage

Tested with a Limited

2 0

0 5

Functional Pattern

Logical 0 Input Voltage

Tested with a Limited

0 5

0 8

Functional Pattern

OH1

Q and WE Outputs

e b

10 mA

1 0

OL1

Q and WE Outputs

10 mA

0 5

OH2

All Outputs except Qs WE

e b

3 mA

1 0

OL2

All Outputs except Qs WE

3 mA

0 5

Input Leakage Current

or GND

IL ML

ML Input Current (Low)

GND

200

CC1

Standby Current

CLK at 8 MHz (V

or GND)

CC1

Standby Current

CLK at 20 MHz (V

or GND)

CC1

Standby Current

CLK at 25 MHz (V

or GND)

CC2

Supply Current

CLK at 8 MHz (Inputs Active)

LOAD

0) (V

or GND)

CC2

Supply Current

CLK at 20 MHz (Inputs Active)

LOAD

0) (V

or GND)

CC2

Supply Current

CLK at 25 MHz (Inputs Active)

LOAD

0) (V

or GND)

Input Capacitance

at 1 MHz

is not 100% tested

13 0 AC Timing Parameters

Two speed selections are given the DP8420A 21A 22A-20
and the DP8420A 21A 22A-25 The differences between
the two parts are the maximum operating frequencies of the
input CLKs and the maximum delay specifications Low fre-
quency applications may use the ``

25'' part to gain im-

proved timing

The AC timing parameters are grouped into sectional num-
bers as shown below These numbers also refer to the tim-
ing diagrams

1 36

Common parameters to all modes of operation

50 56

Difference parameters used to calculate
RAS low time
RAS precharge time
CAS high time and
CAS low time

100 121 Common dual access parameters used for Port

B accesses and inputs and outputs used only in
dual accessing

200 212 Refresh parameters

300 315 Mode 0 access parameters used in both single

and dual access applications

400 416 Mode 1 access parameters used in both single

and dual access applications

450 455 Special Mode 1 access parameters which super-

sede the 400 416 parameters when dual ac-
cessing

500 506 Programming parameters

Unless otherwise stated V

5 0V

10% 0

70 C the output load capacitance is typical for 4 banks of
18 DRAMs per bank including trace capacitance (see Note
2)

Two different loads are specified

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Note 1

``Absolute Maximum Ratings'' are the values beyond which the safety of the device cannot be guaranteed They are not meant to imply that the device

should be operated at these limits The table of ``Electrical Characteristics'' provides conditions for actual device operation

Note 2

Input pulse 0V to 3V tR

2 5 ns Input reference point on AC measurements is 1 5V Output reference points are 2 4V for High and 0 8V for Low

Note 3

AC Production testing is done at 50 pF

TL F 8588 E9

FIGURE 36 Clock DELCLK Timing

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Common Parameter

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Description

Min

Max

Min

Max

Min

Max

Min

Max

CLK

CLK Frequency

tCLKP

CLK Period

3 4

tCLKPW

CLK Pulse Width

fDCLK

DELCLK Frequency

tDCLKP

DELCLK Period

200

7 8

tDCLKPW

DELCLK Pulse Width

tPRASCAS0

RAS Asserted to CAS Asserted

(tRAH

15 ns tASC

0 ns)

tPRASCAS1

RAS Asserted to CAS Asserted

(tRAH

15 ns tASC

10 ns)

tPRASCAS2

(RAS Asserted to CAS Asserted

(tRAH

25 ns tASC

0 ns)

tPRASCAS3

(RAS Asserted to CAS Asserted

(tRAH

25 ns tASC

10 ns)

10a

tRAH

Row Address Hold Time (tRAH

15)

10b

tRAH

Row Address Hold Time (tRAH

25)

11a

tASC

Column Address Setup Time (tASC

11b

tASC

Column Address Setup Time (tASC

10)

tPCKRAS

CLK High to RAS Asserted

following Precharge

tPARQRAS

AREQ Negated to RAS Negated

tPENCL

ECAS0 3 Asserted to CAS Asserted

tPENCH

ECAS0 3 Negated to CAS Negated

tPARQCAS

AREQ Negated to CAS Negated

tPCLKWH

CLK to WAIT Negated

tPCLKDL0

CLK to DTACK Asserted
(Programmed as DTACK of 1 2 1 1

or if WAITIN is Asserted)

tPEWL

ECAS Negated to WAIT Asserted

during a Burst Access

tSECK

ECAS Asserted Setup to CLK High to
Recognize the Rising Edge of CLK

during a Burst Access

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Common Parameter

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Description

Min

Max

Min

Max

Min

Max

Min

Max

tPEDL

ECAS Asserted to DTACK
Asserted during a Burst Access

(Programmed as DTACK0)

tPEDH

ECAS Negated to DTACK

Negated during a Burst Access

tSWCK

WAITIN Asserted Setup to CLK

tPWINWEH

WIN Asserted to WE Asserted

tPWINWEL

WIN Negated to WE Negated

tPAQ

Row Column Address Valid to

Q0 8 9 10 Valid

tPCINCQ

COLINC Asserted to Q0 8 9 10

Incremented

tSCINEN

COLINC Asserted Setup to ECAS

Asserted to Ensure tASC

0 ns

29a

tSARQCK1

AREQ AREQB Negated Setup to CLK

High with 1 Period of Precharge

29b

tSARQCK2

AREQ AREQB Negated Setup to CLK High

with

1 Period of Precharge Programmed

tPAREQDH

AREQ Negated to DTACK Negated

tPCKCAS

CLK High to CAS Asserted

when Delayed by WIN

tSCADEN

Column Address Setup to ECAS

Asserted to Guarantee tASC

tWCINC

COLINC Pulse Width

34a

tPCKCL0

CLK High to CAS Asserted following

Precharge (tRAH

15 ns tASC

0 ns)

34b

tPCKCL1

CLK High to CAS Asserted following

Precharge (tRAH

15 ns tASC

10 ns)

34c

tPCKCL2

CLK High to CAS Asserted following

Precharge (tRAH

25 ns tASC

0 ns)

34d

tPCKCL3

CLK High to CAS Asserted following

101

109

Precharge (tRAH

25 ns tASC

10 ns)

tCAH

Column Address Hold Time

(Interleave Mode Only)

tPCQR

CAS Asserted to Row Address

Valid (Interleave Mode Only)

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Difference

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

Min

Max

Min

Max

tD1

(AREQ or AREQB Negated to RAS
Negated) Minus (CLK High to RAS

Asserted)

tD2

(CLK High to Refresh RAS Negated)

Minus (CLK High to RAS Asserted)

tD3a

(ADS Asserted to RAS Asserted
(Mode 1)) Minus (AREQ Negated

to RAS Negated)

tD3b

(CLK High to RAS Asserted (Mode 0))

Minus (AREQ Negated to RAS Negated)

tD4

(ECAS Asserted to CAS Asserted)

Minus (ECAS Negated to CAS Negated)

tD5

(CLK to Refresh RAS Asserted) Minus

(CLK to Refresh RAS Negated)

tD6

(AREQ Negated to RAS Negated)
Minus (ADS Asserted to RAS

Asserted (Mode 1))

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Common Dual Access

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

Min

Max

Min

Max

100

tHCKARQB

AREQB Negated Held from CLK High

101

tSARQBCK

AREQB Asserted Setup to CLK High

102

tPAQBRASL

AREQB Asserted to RAS Asserted

103

tPAQBRASH

AREQB Negated to RAS Negated

105

tPCKRASG

CLK High to RAS Asserted for

Pending Port B Access

106

tPAQBATKBL

AREQB Asserted to ATACKB Asserted

107

tPCKATKB

CLK High to ATACKB Asserted

for Pending Access

108

tPCKGH

CLK High to GRANTB Asserted

109

tPCKGL

CLK High to GRANTB Negated

110

tSADDCKG

Row Address Setup to CLK High That
Asserts RAS following a GRANTB

Change to Ensure tASR

0 ns for Port B

111

tSLOCKCK

LOCK Asserted Setup to CLK Low

to Lock Current Port

112

tPAQATKBH

AREQ Negated to ATACKB Negated

113

tPAQBCASH

AREQB Negated to CAS Negated

114

tSADAQB

Address Valid Setup to

AREQB Asserted

116

tHCKARQG

AREQ Negated Held from CLK High

117

tWAQB

AREQB High Pulse Width

to Guarantee tASR

0 ns

118a

tPAQBCAS0

AREQB Asserted to CAS Asserted

103

111

(tRAH

15 ns tASC

0 ns)

118b

tPAQBCAS1

AREQB Asserted to CAS Asserted

113

121

104

(tRAH

15 ns tASC

10 ns)

118c

tPAQBCAS2

AREQB Asserted to CAS Asserted

113

121

104

(tRAH

25 ns tASC

0 ns)

118d

tPAQBCAS3

AREQB Asserted to CAS Asserted

123

131

107

114

(tRAH

25 ns tASC

10 ns)

120a

tPCKCASG0

CLK High to CAS Asserted
for Pending Port B Access

113

121

103

(tRAH

15 ns tASC

0 ns)

120b

tPCKCASG1

CLK High to CAS Asserted
for Pending Port B Access

123

131

106

113

(tRAH

15 ns tASC

10 ns)

120c

tPCKCASG2

CLK High to CAS Asserted
for Pending Port B Access

123

131

106

113

(tRAH

25 ns tASC

0 ns)

120d

tPCKCASG3

CLK High to CAS Asserted
for Pending Port B Access

133

141

116

123

(tRAH

25 ns tASC

10 ns)

121

tSBADDCKG

Bank Address Valid Setup to CLK
High That Starts RAS

for Pending Port B Access

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Refresh Parameter

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Description

Min

Max

Min

Max

Min

Max

Min

Max

200

tSRFCK

RFSH Asserted Setup to CLK High

201

tSDRFCK

DISRFSH Asserted Setup to CLK High

202

tSXRFCK

EXTENDRF Setup to CLK High

204

tPCKRFL

CLK High to RFIP Asserted

205

tPARQRF

AREQ Negated to RFIP Asserted

206

tPCKRFH

CLK High to RFIP Negated

207

tPCKRFRASH

CLK High to Refresh RAS Negated

208

tPCKRFRASL

CLK High to Refresh RAS Asserted

209a

tPCKCL0

CLK High to CAS Asserted
during Error Scrubbing

RAH

15 ns t

ASC

0 ns)

209b

tPCKCL1

CLK High to CAS Asserted
during Error Scrubbing

100

RAH

15 ns t

ASC

10 ns)

209c

tPCKCL2

CLK High to CAS Asserted
during Error Scrubbing

100

RAH

25 ns t

ASC

0 ns)

209d

tPCKCL3

CLK High to CAS Asserted
during Error Scrubbing

102

110

100

RAH

25 ns t

ASC

10 ns)

210

tWRFSH

RFSH Pulse Width

211

tPCKRQL

CLK High to RFRQ Asserted

212

tPCKRQH

CLK High to RFRQ Negated

TL F 8588 F2

FIGURE 39 200 Refresh Timing

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Mode 0 Access

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

Min

Max

Min

Max

300

tSCSCK

CS Asserted to CLK High

301a

tSALECKNL

ALE Asserted Setup to CLK High
Not Using On-Chip Latches or

if Using On-Chip Latches and
B0 B1 Are Constant Only 1 Bank

301b

tSALECKL

ALE Asserted Setup to CLK High
if Using On-Chip Latches if B0 B1

Can Change More Than One Bank

302

tWALE

ALE Pulse Width

303

tSBADDCK

Bank Address Valid Setup to CLK High

304

tSADDCK

Row Column Valid Setup to
CLK High to Guarantee

tASR

0 ns

305

tHASRCB

Row Column Bank Address
Held from ALE Negated

(Using On-Chip Latches)

306

tSRCBAS

Row Column Bank Address
Setup to ALE Negated

(Using On-Chip Latches)

307

tPCKRL

CLK High to RAS Asserted

308a

tPCKCL0

CLK High to CAS Asserted

RAH

15 ns t

ASC

0 ns)

308b

tPCKCL1

CLK High to CAS Asserted

RAH

15 ns t

ASC

10 ns)

308c

tPCKCL2

CLK High to CAS Asserted

RAH

25 ns t

ASC

0 ns)

308d

tPCKCL3

CLK High to CAS Asserted

101

109

RAH

25 ns t

ASC

10 ns)

309

tHCKALE

ALE Negated Hold from CLK High

310

tSWINCK

WIN Asserted Setup to CLK High

to Guarantee CAS is Delayed

311

tPCSWL

CS Asserted to WAIT Asserted

312

tPCSWH

CS Negated to WAIT Negated

313

tPCLKDL1

CLK High to DTACK Asserted

(Programmed as DTACK0)

314

tPALEWL

ALE Asserted to WAIT Asserted

(CS is Already Asserted)

315

AREQ Negated to CLK High That Starts
Access RAS to Guarantee tASR

0 ns

(Non-Interleaved Mode Only)

316

tPCKCV0

CLK High to Column
Address Valid

RAH

15 ns t

ASC

0 ns)

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Mode 1 Access

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

Min

Max

Min

Max

400a

tSADSCK1

ADS Asserted Setup to CLK High

400b

tSADSCKW

ADS Asserted Setup to CLK
(to Guarantee Correct WAIT

or DTACK Output Doesn't Apply for DTACK0)

401

tSCSADS

CS Setup to ADS Asserted

402

tPADSRL

ADS Asserted to RAS Asserted

403a

tPADSCL0

ADS Asserted to CAS Asserted

(tRAH

15 ns tASC

0 ns)

403b

tPADSCL1

ADS Asserted to CAS Asserted

104

(tRAH

15 ns tASC

10 ns)

403c

tPADSCL2

ADS Asserted to CAS Asserted

104

(tRAH

25 ns tASC

0 ns)

403d

tPADSCL3

ADS Asserted to CAS Asserted

106

114

102

(tRAH

25 ns tASC

10 ns)

404

tSADDADS

Row Address Valid Setup to ADS

Asserted to Guarantee tASR

0 ns

405

tHCKADS

ADS Negated Held from CLK High

406

tSWADS

WAITIN Asserted Setup to ADS
Asserted to Guarantee DTACK0

Is Delayed

407

tSBADAS

Bank Address Setup to ADS Asserted

408

tHASRCB

Row Column Bank Address Held from

ADS Asserted (Using On-Chip Latches)

409

tSRCBAS

Row Column Bank Address Setup to

ADS Asserted (Using On-Chip Latches)

410

tWADSH

ADS Negated Pulse Width

411

tPADSD

ADS Asserted to DTACK Asserted

(Programmed as DTACK0)

412

tSWINADS

WIN Asserted Setup to ADS Asserted
(to Guarantee CAS Delayed during

Writes Accesses)

413

tPADSWL0

ADS Asserted to WAIT Asserted

(Programmed as WAIT0 Delayed Access)

414

tPADSWL1

ADS Asserted to WAIT Asserted

(Programmed WAIT 1 2 or 1)

415

tPCLKDL1

CLK High to DTACK Asserted
(Programmed as DTACK0

Delayed Access)

416

AREQ Negated to ADS Asserted
to Guarantee tASR

0 ns

(Non Interleaved Mode Only)

417

tPADSCV0

ADS Asserted to Column
Address Valid

RAH

15 ns t

ASC

0 ns)

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18 DRAMs

per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Mode 1 Dual Access

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

Min

Max

Min

Max

450

tSADDCKG

Row Address Setup to CLK High That
Asserts RAS following a GRANTB

Port Change to Ensure tASR

0 ns

451

tPCKRASG

CLK High to RAS Asserted

for Pending Access

452

tPCLKDL2

CLK to DTACK Asserted for Delayed

Accesses (Programmed as DTACK0)

453a

tPCKCASG0

CLK High to CAS Asserted
for Pending Access

101

109

RAH

15 ns t

ASC

0 ns)

453b

tPCKCASG1

CLK High to CAS Asserted
for Pending Access

111

119

103

RAH

15 ns t

ASC

10 ns)

453c

tPCKCASG2

CLK High to CAS Asserted
for Pending Access

111

119

103

RAH

25 ns t

ASC

0 ns)

453d

tPCKCASG3

CLK High to CAS Asserted
for Pending Access

121

129

106

113

RAH

25 ns t

ASC

10 ns)

454

tSBADDCKG

Bank Address Valid Setup to CLK High

that Asserts RAS for Pending Access

455

tSADSCK0

ADS Asserted Setup to CLK High

13 0 AC Timing Parameters

(Continued)

Unless otherwise stated V

5 0V

10% 0 C

70 C the output load capacitance is typical for 4 banks of 18

DRAMs per bank including trace capacitance (Note 2)

Two different loads are specified
C

50 pF loads on all outputs except

150 pF loads on Q0 8 9 10 and WE or

50 pF loads on all outputs except

125 pF loads on RAS0 3 and CAS0 3 and

380 pF loads on Q0 8 9 10 and WE

Programming

8420A 21A 22A-20

8420A 21A 22A-25

Number

Symbol

Parameter Description

Min

Max

Min

Max

Min

Max

Min

Max

500

tHMLADD

Mode Address Held from ML Negated

501

tSADDML

Mode Address Setup to ML Negated

502

tWML

ML Pulse Width

503

tSADAQML

Mode Address Setup to AREQ Asserted

504

tHADAQML

Mode Address Held from AREQ Asserted

505

tSCSARQ

CS Asserted Setup to

AREQ Asserted

506

tSMLARQ

ML Asserted Setup to AREQ Asserted

TL F 8588 F7

FIGURE 44 500 Programming

14 0 Functional Differences
between the DP8420A 21A 22A
and the DP8420 21 22

1 Extending the Column Address Strobe (CAS) after

AREQ Transitions High

The DP8420A 21A 22A allows CAS to be asserted for
an indefinite period of time beyond AREQ (or AREQB
DP8422A only Scrubbing refreshes are not affected ) be-
ing negated by continuing to assert the appropriate ECAS
inputs This feature is allowed as long as the ECAS0 input
was negated during programming The DP8420 21 22
does not allow this feature

2 Dual Accessing

The DP8420A 21A 22A asserts RAS either one or two
clock periods after GRANTB has been asserted or negat-
ed depending upon how the R0 bit was programmed dur-
ing the mode load operation The DP8420 21 22 will al-
ways start RAS one clock period after GRANTB is assert-
ed or negated The above statements assume that RAS
precharge has been completed by the time GRANTB is
asserted or negated

3 Refresh Request Output (RFRQ)

The DP8420A 21A 22A allows RFRQ (refresh request)
to be output on the WE output pin given that ECAS0 was
negated during programming or the controller was pro-
grammed to function in the address pipelining (memory
interleaving) mode

The DP8420 21 22 only allows

RFRQ to be output during the address pipelining mode

4 Clearing the Refresh Request Clock Counter

The DP8420A 21A 22A allows the internal refresh re-
quest clock counter to be cleared by negating DISRFSH
and

asserting

RFSH

for

least

500

The

DP8420 21 22 clears the internal refresh request clock
counter if DISRFSH remains low for at least 500 ns Once
the internal refresh request clock counter is cleared the
user is guaranteed that an internally generated RFRQ will
not be generated for at least 13 ms 15 ms (depending
upon how programming bits C0

3 were pro-

grammed)

15 0 DP8420A 21A 22A User Hints

1 All inputs to the DP8420A 21A 22A should be tied high

low or the output of some other device

Note One signal is active high COLINC (EXTNDRF) should be tied low

to disable

2 Each ground on the DP8420A 21A 22A must be decou-

pled to the closest on-chip supply (V

) with 0 1 mF ce-

ramic capacitor

This is necessary because these

grounds

are

kept

separate

inside

the

DP8420A 21A 22A The decoupling capacitors should
be placed as close as possible with short leads to the
ground and supply pins of the DP8420A 21A 22A

3 The output called ``CAP'' should have a 0 1 mF capacitor

to ground

4 The DP8420A 21A 22A has 20X series damping resis-

tors built into the output drivers of RAS CAS address
and WE RFRQ Space should be provided for external
damping resistors on the printed circuit board (or wire-

wrap board) because they may be needed The value of
these damping resistors (if needed) will vary depending
upon the output the capacitance of the load and the
characteristics of the trace as well as the routing of the
trace The value of the damping resistor also may vary
between the wire-wrap board and the printed circuit
board To determine the value of the series damping re-
sistor it is recommended to use an oscilloscope and look
at the furthest DRAM from the DP8420A 21A 22A The
undershoot of RAS CAS WE and the addresses should
be kept to less than 0 5V below ground by varying the
value of the damping resistor The damping resistors
should be placed as close as possible with short leads to
the driver outputs of the DP8420A 21A 22A

5 The circuit board must have a good V

and ground

plane connection If the board is wire-wrapped the V

and ground pins of the DP8420A 21A 22A the DRAM
associated logic and buffer circuitry must be soldered to
the V

and ground planes

6 The traces from the DP8420A 21A 22A to the DRAM

should be as short as possible

7 ECAS0 should be held low during programming if the user

wishes that the DP8420A 21A 22A be compatible with a
DP8420 21 22 design

8 Parameter Changes due to Loading

All A C parameters are specified with the equivalent load
capacitances including traces of 64 DRAMs organized
as 4 banks of 18 DRAMs each Maximums are based on
worst-case conditions If an output load changes then the
A C timing parameters associated with that particular
output must be changed For example if we changed our
output load to
C

250 pF loads on RAS0 3 and CAS0 3

760 pF loads on Q0 9 and WE

we would have to modify some parameters (not all calcu-
lated here)
$308a clock to CAS asserted
(t

RAH

15 ns t

ASC

0 ns)

A ratio can be used to figure out the timing change per
change in capacitance for a particular parameter by using
the specifications and capacitances from heavy and light
load timing

Ratio

$308a w Heavy Load

$308a w Light Load

(CAS)

79 ns

72 ns

125 pF

50 pF

7 ns

75 pF

$308a (actual)

(capacitance difference

ratio)

$308a (specified)

(250 pF

125 pF)

7 ns

75 pF

79 ns

11 7 ns

79 ns

90 7 ns

250 pF load

9 It is required that the user perform a hardware reset of

the DP8420A 21A 22A before programming and using
the chip A hardware reset consists of asserting both ML
and DISRFSH for a minimum of 16 positive edges of CLK
see Section 3 1

DP8420A21A22A

microCMOS

Programmable

256k1M4M

Dynamic

RAM

ControllerDrivers

Physical Dimensions

inches (millimeters)

Lit

103064

Plastic Chip Carrier (V)

Order Number DP8420AV-20 DP8420AV-25 DP8421AV-20 or DP8421AV-25

NS Package Number V68A

Plastic Chip Carrier (V)

Order Number DP8422AV-20 or DP8422AV-25

NS Package Number V84A

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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein

1 Life support devices or systems are devices or

2 A critical component is any component of a life

systems which (a) are intended for surgical implant

support device or system whose failure to perform can

into the body or (b) support or sustain life and whose

be reasonably expected to cause the failure of the life

failure to perform when properly used in accordance

support device or system or to affect its safety or

with instructions for use provided in the labeling can

effectiveness

be reasonably expected to result in a significant injury
to the user

National Semiconductor

Corporation

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Hong Kong Ltd

Japan Ltd

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Fax (a49) 0-180-530 85 86

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Tel 81-043-299-2309

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Tel (a49) 0-180-534 16 80

Fax (852) 2736-9960

National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DP8421AV-25

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DP8421AV-25