TL F 8588

DP8420A21A22A

microCMOS

Programmable

256k1M4M

Dynamic

RAM

ControllerDrivers

July 1992

DP8420A 21A 22A microCMOS Programmable
256k 1M 4M Dynamic RAM Controller Drivers

General Description

The DP8420A 21A 22A dynamic RAM controllers provide a
low cost single chip interface between dynamic RAM and
all 8- 16- and 32-bit systems The DP8420A 21A 22A gen-
erate all the required access control signal timing for
DRAMs An on-chip refresh request clock is used to auto-
matically refresh the DRAM array Refreshes and accesses
are arbitrated on chip If necessary a WAIT or DTACK out-
put inserts wait states into system access cycles including
burst mode accesses RAS low time during refreshes and
RAS precharge time after refreshes and back to back ac-
cesses are guaranteed through the insertion of wait states
Separate on-chip precharge counters for each RAS output
can be used for memory interleaving to avoid delayed back
to back accesses because of precharge An additional fea-
ture of the DP8422A is two access ports to simplify dual
accessing Arbitration among these ports and refresh is
done on chip

Features

On chip high precision delay line to guarantee critical
DRAM access timing parameters

microCMOS process for low power

High capacitance drivers for RAS CAS WE and DRAM
address on chip

On chip support for nibble page and static column
DRAMs

Byte enable signals on chip allow byte writing in a word
size up to 32 bits with no external logic

Selection of controller speeds 20 MHz and 25 MHz

On board Port A Port B (DP8422A only) refresh arbitra-
tion logic

Direct interface to all major microprocessors (applica-
tion notes available)

4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)

of Pins

of Address

Largest

Direct Drive

Access

Control

(PLCC)

Outputs

DRAM

Memory

Ports

Possible

Capacity

Available

DP8420A

256 kbit

4 Mbytes

Single Access Port

DP8421A

1 Mbit

16 Mbytes

Single Access Port

DP8422A

4 Mbit

64 Mbytes

Dual Access Ports (A and B)

Block Diagram

DP8420A 21A 22A DRAM Controller

TL F 8588 5

FIGURE 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

Staggered Refresh

is a trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

Table of Contents

1 0 INTRODUCTION

2 0 SIGNAL DESCRIPTIONS

2 1 Address R W and Programming Signals

2 2 DRAM Control Signals

2 3 Refresh Signals

2 4 Port A Access Signals

2 5 Port B Access Signals (DP8422A)

2 6 Common Dual Port Signals (DP8422A)

2 7 Power Signals and Capacitor Input

2 8 Clock Inputs

3 0 PROGRAMMING AND RESETTING

3 1 External Reset

3 2 Programming Methods

3 2 1 Mode Load Only Programming

3 2 2 Chip Selected Access Programming

3 3 Internal Programming Modes

4 0 PORT A ACCESS MODES

4 1 Access Mode 0

4 2 Access Mode 1

4 3 Extending CAS with Either Access Mode

4 4 Read-Modify-Write Cycles with Either Access Mode

4 5 Additional Access Support Features

4 5 1 Address Latches and Column Increment

4 5 2 Address Pipelining

4 5 3 Delay CAS During Write Accesses

5 0 REFRESH OPTIONS

5 1 Refresh Control Modes

5 1 1 Automatic Internal Refresh

5 1 2 Externally Controlled Burst Refresh

5 1 3 Refresh Request Acknowledge

5 2 Refresh Cycle Types

5 2 1 Conventional Refresh

5 2 2 Staggered Refresh

5 2 3 Error Scrubbing Refresh

5 3 Extending Refresh

5 4 Clearing the Refresh Address Counter

5 5 Clearing the Refresh Request Clock

6 0 PORT A WAIT STATE SUPPORT

6 1 WAIT Type Output

6 2 DTACK Type Output

6 3 Dynamically Increasing the Number of Wait States

6 4 Guaranteeing RAS Low Time and RAS Precharge

Time

7 0 RAS AND CAS CONFIGURATION MODES

7 1 Byte Writing

7 2 Memory Interleaving

7 3 Address Pipelining

7 4 Error Scrubbing

7 5 Page Burst Mode

8 0 TEST MODE

9 0 DRAM CRITICAL TIMING PARAMETERS

9 1 Programmable Values of t

RAH

and t

ASC

9 2 Calculation of t

RAH

and t

ASC

10 0 DUAL ACCESSING (DP8422A)

10 1 Port B Access Mode

10 2 Port B Wait State Support

10 3 Common Port A and Port B Dual Port Functions

10 3 1 GRANTB Output

10 3 2 LOCK Input

11 0 ABSOLUTE MAXIMUM RATINGS

12 0 DC ELECTRICAL CHARACTERISTICS

13 0 AC TIMING PARAMETERS

14 0 FUNCTIONAL DIFFERENCES BETWEEN THE

DP8420A 21A 22A AND THE DP8420 21 22

15 0 DP8420A 21A 22A USER HINTS

1 0 Introduction

The DP8420A 21A 22A are CMOS Dynamic RAM control-
lers that incorporate many advanced features which include
address latches refresh counter refresh clock row column
and refresh address multiplexer delay line refresh access
arbitration logic and high capacitive drivers The program-
mable system interface allows any manufacturer's micro-
processor

bus

directly

interface

via

the

DP8420A 21A 22A to DRAM arrays up to 64 Mbytes in
size

After power up the user must first reset and program the
DP8420A 21A 22A before accessing the DRAM The chip
is programmed through the address bus

Reset

Due to the differences in power supplies the internal reset
circuit may not always reset correctly therefore an External
(hardware) Reset must be performed before programming
the chip

Programming

After resetting the chip the user can program the controller
by either one of two methods Mode Load Only Program-
ming or Chip Select Access Programming

Initialization Period

Once the DP8420A 21A 22A has been programmed for the
first time a 60 ms initialization period is entered During this
time the DRC performs refreshes to the DRAM array so
further warm up cycles are unnecessary The initialization
period is entered only after the first programming after a
reset

Accessing Modes

After

resetting

and

programming

the

chip

the

DP8420A 21A 22A is ready to access the DRAM There
are two modes of accessing with these controllers Mode 0
which indicates RAS synchronously and Mode 1 which indi-
cates RAS asynchronously

Refresh Modes

The DP8420A 21A 22A have expanded refresh capabilities
compared to previous DRAM controllers There are three
modes of refreshing available Internal Automatic Refresh-
ing Externally Controlled Burst Refreshing and Refresh Re-
quest Acknowledge Refreshing Any of these modes can
be used together or separately to achieve the desired re-
sults

Refresh Types

These controllers have three types of refreshing available
Conventional Staggered and Error Scrubbing Any refresh
control mode can be used with any type of refresh

Wait Support

The DP8420A 21A 22A have wait support available as
DTACK or WAIT Both are programmable DTACK Data
Transfer ACKnowledge is useful for processors whose wait
signal is active high WAIT is useful for those processors
whose wait signal is active low The user can choose either
at programming These signals are used by the on chip arbi-
ter to insert wait states to guarantee the arbitration between
accesses refreshes and precharge Both signals are inde-
pendent of the access mode chosen and both signals can
be dynamically delayed further through the WAITIN signal to
the DP8420A 21A 22A

Sequential Accesses (Static Column Page Mode)

The DP8420A 21A 22A have address latches used to
latch the bank row and column address inputs Once the
address is latched a COLumn INCrement (COLINC) feature
can be used to increment the column address The address
latches can also be programmed to be fall through COLINC
can be used for Sequential Accesses of Static Column
DRAMs Also COLINC in conjunction with ECAS inputs can
be used for Sequential Accesses to Page Mode DRAMs

RAS and CAS Configuration (Byte Writing)

The RAS and CAS drivers can be configured to drive a one
two or four bank memory array up to 32 bits in width The
ECAS signals can then be used to select one of four CAS
drivers for Byte Writing with no extra logic

Memory Interleaving

When configuring the DP820A 21A 22A for more than one
bank Memory Interleaving can be used By tying the low
order address bits to the bank select lines B0 and B1 se-
quential back to back accesses will not be delayed since
these controllers have separate precharge counters per
bank

Address Pipelining

The DP8420A 21A 22A are capable of performing Address
Pipelining In address pipelining the DRC will guarantee the
column address hold time and switch the internal multiple-
xor to place the row address on the address bus At this
time another memory access to another bank can be initiat-
ed

Dual Accessing

Finally the DP8422A has all the features previously men-
tioned and unlike the DP8420A 21A the DP8422A has a
second port to allow a second CPU to access the same
memory array The DP8422A has four signals to support
Dual Accessing these signals are AREQB ATACKB LOCK
and GRANTB All arbitration for the two ports and refresh is
done on chip by the controller through the insertion of wait
states Since the DP8422A has only one input address bus
the address lines must be multiplexed externally The signal
GRANTB can be used for this purpose

Terminology

The following explains the terminology used in this data
sheet The terms negated and asserted are used Asserted
refers to a ``true'' signal Thus ``ECAS0 asserted'' means
the ECAS0 input is at a logic 0 The term ``COLINC assert-
ed'' means the COLINC input is at a logic 1 The term negat-
ed refers to a ``false'' signal Thus ``ECAS0 negated''
means the ECAS0 input is at a logic 1 The term ``COLINC
negated'' means the input COLINC is at a logic 0 The table
shown below clarifies this terminology

Signal

Action

Logic Level

Active High

Asserted

High

Active High

Negated

Low

Active Low

Asserted

Low

Active Low

Negated

High

2 0 Signal Descriptions

Device (If not

Input

Description

Name

Applicable to All)

Output

2 1 ADDRESS R W AND PROGRAMMING SIGNALS

R0 10

DP8422A

ROW ADDRESS

These inputs are used to specify the row address during an access

to the DRAM They are also used to program the chip when ML is asserted (except

R0 9

DP8420A 21A

R10)

C0 10

DP8422A

COLUMN ADDRESS

These inputs are used to specify the column address during an

access to the DRAM They are also used to program the chip when ML is asserted

C0 9

DP8420A 21A

(except C10)

B0 B1

BANK SELECT

Depending on programming these inputs are used to select a group

of RAS and CAS outputs to assert during an access They are also used to program
the chip when ML is asserted

ECAS0 3

ENABLE CAS

These inputs are used to enable a single or group of CAS outputs

when asserted In combination with the B0 B1 and the programming bits these
inputs select which CAS output or CAS outputs will assert during an access The
ECAS signals can also be used to toggle a group of CAS outputs for page nibble
mode accesses They also can be used for byte write operations If ECAS0 is
negated during programming continuing to assert the ECAS0 while negating AREQ
or AREQB during an access will cause the CAS outputs to be extended while the
RAS outputs are negated (the ECASn inputs have no effect during scrubbing
refreshes)

WIN

WRITE ENABLE IN

This input is used to signify a write operation to the DRAM If

ECAS0 is asserted during programming the WE output will follow this input This
input asserted will also cause CAS to delay to the next positive clock edge if address
bit C9 is asserted during programming

COLINC

COLUMN INCREMENT

When the address latches are used and RFIP is negated

this input functions as COLINC Asserting this signal causes the column address to

(EXTNDRF)

be incremented by one When RFIP is asserted this signal is used to extend the
refresh cycle by any number of periods of CLK until it is negated

MODE LOAD

This input signal when low enables the internal programming register

that stores the programming information

2 2 DRAM CONTROL SIGNALS

Q0 10

DP8422A

DRAM ADDRESS

These outputs are the multiplexed output of the R0 9 10 and

C0 9 10 and form the DRAM address bus These outputs contain the refresh

Q0 9

DP8421A

address whenever RFIP is asserted They contain high capacitive drivers with 20X

Q0 8

DP8421A

series damping resistors

RAS0 3

ROW ADDRESS STROBES

These outputs are asserted to latch the row address

contained on the outputs Q0 8 9 10 into the DRAM When RFIP is asserted the
RAS outputs are used to latch the refresh row address contained on the Q0 8 9 10
outputs in the DRAM These outputs contain high capacitive drivers with 20X series
damping resistors

CAS0 3

COLUMN ADDRESS STROBES

These outputs are asserted to latch the column

address contained on the outputs Q0 8 9 10 into the DRAM These outputs have
high capacitive drivers with 20X series damping resistors

WRITE ENABLE

or REFRESH REQUEST This output asserted specifies a write

operation to the DRAM When negated this output specifies a read operation to the

(RFRQ)

DRAM When the DP8420A 21A 22A is programmed in address pipelining mode or
when ECAS0 is negated during programming this output will function as RFRQ
When asserted this pin specifies that 13 ms or 15 ms have passed If DISRFSH is
negated the DP8420A 21A 22A will perform an internal refresh as soon as possible
If DISRFRSH is asserted RFRQ can be used to externally request a refresh through
the input RFSH This output has a high capacitive driver and a 20X series damping
resistor

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