TL F 11777

DP84910

(-36-50)

Integrated

Read

Channel

October 1994

DP84910 (-36 -50)
Integrated Read Channel

General Description

The DP84910 integrates most functions of the hard disk
read channel electronics onto a single 5V chip It incorpo-
rates a pulse servo detector a programmable integrated
channel filter a data synchronizer a frequency synthesizer
and a serial port interface The chip receives data from a
read preamplifier filters and peak detects the read pulses
for both data and embedded servo information and resyn-
chronizes the data with the system clock

The DP84910 is available in two versions DP84910VHG-36
and DP84910VHG-50 The DP84910VHG-36 is specified to
operate over a data rate range of 7 5 Mbits sec to
36 Mbits sec The other version DP84910VHG-50 will op-
erate over a data rate range of 13 7 Mbits sec to 50 Mbits
sec

This device is specifically designed to address zoned data
rate applications A channel filter with control register se-
lectable cutoff frequency and equalization is provided on-
chip This eliminates the need for multiple external channel
filters and allows for greater flexibility in the selection of
zone frequencies The frequency synthesizer provides cen-
ter frequency information for the data synchronizer and a
variable frequency write clock There is no need for any off-
chip frequency setting components or DACs

A four-bank control register is included to control zoning
operations and configure general chip functions At V

power-up the chip self-configures by presetting all bits in the
control register to predetermined operating setup condi-
tions

Independent power down control for all of the major blocks
within the chip is provided via three bits in the control
register

(SYNC

PWR

STH

PWR

and

PWR

DN) to manage power consumption In addi-

tion two pins (SLEEP and IDLE SERVO) are available to
control power management The sleep mode pin (SLEEP)
powers down all circuitry on the chip including the control
register In this mode the maximum power supply current is
2 mA the control register data must be reentered when
exiting this mode The idle servo mode pin (IDLE SERVO)
toggles the device between the idle and servo modes In the
idle mode only the control register and pulse detector bias-
ing circuitry necessary for a quick recovery are active In the
servo mode the pulse detector portions needed for servo
detection are active as well as the control register Less
than 15 ms is required for the pulse detector to recover from
the idle condition The control register data is not lost when
this pin is toggled The pin can be rapidly toggled (

15 ms)

to achieve average power consumption savings and will
keep the read write head on track Seventeen power and
ground pins are provided to isolate major functional blocks
and allow for independent supply voltage filtering thus en-
hancing noise immunity

(Continued)

TL F 11777 1

FIGURE 1 DP84910 in a Typical Disk Drive System

MICROWIRE

is a trademark of National Semiconductor Corporation

C1996 National Semiconductor Corporation

RRD-B30M116 Printed in U S A

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General Description

(Continued)

The pulse detector section detects the peaks of the analog
pulses from the read preamplifier and converts them to digi-
tal pulses whose leading edges represent the time position
of the analog pulses' peaks In order to not interpret noise
on the baseline as input data hysteresis is included The
hysteresis level for a data field is set at the SETHYSD pin
while the hysteresis level for a servo field is set at the
SETHYSS pin A third pin (SFIELD) is used to select be-
tween these two levels of hysteresis This allows for the
setting of different hysteresis levels for these two fields The
data field hysteresis level is also selectable in 8 steps
through bits in the control register (HYS

VTH0 HYS

VTH2) with the level set at the SETHYSD pin as the nominal
value

The pulse detector section includes an automatic gain con-
trol (AGC) circuit which normalizes the analog data signal to
a constant amplitude The response of the AGC is partially
controlled by one of the device's pins (VAGCIN) Two
VAGCIN pins (VAGCIND VAGCINS) are provided so that
different capacitor values can be selected to provide differ-
ent AGC time constants for data and servo field information
The switching between these pins capacitors is controlled
by the SFIELD pin The SERVO control register bit can en-
able (or disable) the SFIELD pin's ability to control the
amount of equalization provided to the on-chip channel fil-
ter When enabled the state of the SFIELD pin selects be-
tween two groups of control register bits (EQ0 EQ1 EQ2
and SERVO

EQ0 SERVO

EQ1 SERVO

EQ2) which

can separately determine the amount of equalization provid-
ed This feature allows for an adjustment of the channel
filter bandwidth in a servo field Thus the channel filter can
have different bandwidths in a servo field and a data field

The pulse detector section has a delayed low impedance
switch at the gain controlled amplifier inputs (AMPIN1 AM-
PIN2) which allows for rapid recovery from the write mode
The amount of delay (either 1 7 ms or 3 4 ms) coming out of
the low impedance mode is selectable through a bit in the
control register (SLOW) A pattern insensitive fast respond-
ing AGC circuit (with HOLD function) allows rapid head
switch settling and embedded servo normalization Select-
able delay (in four steps) in the qualification channel along
with a ``view internal signals'' mode allow the timing and
qualification channels to be optimally aligned Four gated
servo detectors are incorporated for recovery of quadrature
embedded servo information The four peak detected val-
ues are available at the SERVO CAPACITOR outputs
(SCAP1 4) Two servo difference amplifiers are provided
Each difference amplifier output (DIFFAMP1 2) provides
the difference between two of the servo peak detectors
centered about an external reference voltage (VDIFF)

The channel filter section is a seven-pole 0 05 degree error
equal ripple filter It utilizes the Kost pulse slimming tech-
nique similar to that which is employed on the DP8491 92
integrated read channel devices The amount of pulse slim-
ming is control register selectable in 8 steps up to a maxi-
mum of 9 dB measured from the base frequency The band-
width of the filter is derived from the XTLIN frequency from
this point the

3 dB frequency is selectable via 7 bits in the

control register (FILT

3 dB

0 FILT

3 dB

The data synchronizer section incorporates zero-phase-
start (ZPS) and digitally controlled window strobe functions
The voltage controlled oscillator (VCO) is fully integrated
requiring no external components and provides a wide dy-
namic range necessary for zoned data rate applications
Data windowing is based on precise VCO duty cycle sym-
metry (in contrast to delay line based centering) An internal
silicon delay line used to establish the phase detector re-
trace angle automatically tracks zoned data recording data
rate changes The charge pump output (CPO) and voltage
controlled oscillator input (VCOI) are provided as separate
pins allowing ample design flexibility in the external loop
filter Frequency lock may be employed within the synchro-
nization field Charge pump (phase detector) gain may be
selected to remain constant or to vary either by a factor of
two or four as instructed via the charge pump gain pin
(CPGAIN) and a bit in the control register (CPRATIO)

The frequency synthesizer section capable of producing a
large number of frequencies from a single external refer-
ence source generates the write clock and reference fre-
quency for the synchronizer This section includes a phase
locked loop (PLL) with selectable dividers at the input port
and in its feedback loop The values for the dividers are
controlled by two control words within the control register
The user has full control over both the input (five bit word
PDATA6 PDATA10) and feedback (six bit word PDATA0
PDATA5) divider selection The feedback divider has an ex-
tra bit when compared to previous NSC integrated read
channel circuits to improve the resolution of frequency set-
ting All blocks within the synthesizer except the RC loop
filter are fully integrated The loop filter resides external to
the chip giving the user full control over the phase locked
loop's dynamics

This device is available in an 80-pin 12 mm x 12 mm PQFP
package and operates off of a single

5V supply

Features

Operates at NRZ data rates up to 50 Mbits sec (equiv-
alent 2 3 (1 7) code data rate)

Operates with a single

5V power supply

Multiple power down modes available with dedicated
SLEEP and IDLE SERVO power down pins

Sleep mode included where I

2 mA maximum

Directly addresses zoned data recording requirements

Integrated channel filter with selectable equalization
and bandwidth eliminates multiple external filter ele-
ments
Fully integrated frequency synthesizer on-chip to pro-
vide write clock and center frequency for the syn-
chronizer

Selectable delay impedance switch (clamp) at pulse de-
tector input for rapid recovery from the write mode

Pattern insensitive fast AGC for rapid head switch set-
tling and embedded servo normalization

Built-in AGC hold for embedded servo

Two AGC control voltage pins provided

one for servo

field and one for data field

Four gated detectors for quadrature embedded servo
information

Two servo difference amplifiers on-chip

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Pin Definitions

(Continued)

Description

POWER SUPPLY AND GROUND PINS

(Continued)

PULSE DETECTOR ANALOG SUPPLY VOLTAGE (PAVCC)

10%

PULSE DETECTOR ANALOG GROUND (PAGND)

FILTER ANALOG SUPPLY VOLTAGE (FVCC)

10%

FILTER ANALOG GROUND (FGND)

SYNCHRONIZER PLL ANALOG SUPPLY VOLTAGE (SYCVCC)

10%

SYNCHRONIZER PLL ANALOG GROUND (SYCGND)

SYNTHESIZER PLL ANALOG SUPPLY VOLTAGE (STHVCC)

10%

SYNTHESIZER PLL ANALOG GROUND (STHGND)

TTL LEVEL LOGIC PINS

WRITE GATE INPUT (WG)

This pin receives the write mode control input signal from the controller The logic polarity

for WG assertion is selectable via a bit in the control register (INV

WG Bank (1 1) bit 5) WG is active low if the control

1) When WG is active the pulse detector inputs (AMPIN1 and AMPIN2) are

held in a low impedance state and the automatic gain control of the puIse detector is in the hold mode There are no
setup or hold timing restrictions on WG enabling or disabling

IDLE SERVO BAR POWER DOWN INPUT (IDLE SERVO)

This input controls the power status of the servo detection

circuitry in the pulse detector When high (idle mode) this pin powers down all pulse detector circuitry except for biasing
circuitry necessary for quick recovery (

15 ms) from this mode When low (servo mode) this pin powers on the circuitry

necessary for servo information detection in the puIse detector The synchronizer and synthesizer power are unaffected
by this pin The controI register power is also unaffected by the IDLE SERVO pin but its input buffers are The control
register's input's are only powered on when the IDLE SERVO pin is low Thus the controI register cannot be loaded
when the IDLE SERVO pin is high The contents of the controI register is not affected by the state of the IDLE SERVO
pin

SLEEP BAR POWER DOWN INPUT (SLEEP)

This active low input powers down aIl circuitry on the chip The control

register is powered down in this mode thus it does not retain its information The control register wiII be reset to the
initial power-on conditions when exiting the sleep mode The maximum supply current in the sleep mode is 2 mA

CONTROL REGISTER LATCH SHIFT BAR INPUT (CRL S)

A logical low on this input allows the CONTROL

REGISTER CLOCK input to shift data into the control register's shift register via the CONTROL REGISTER DATA input
A positive transition latches the data into the addressed bank of latches and issues the information to the appropriate
circuitry within the device To minimize power consumption this pin should be kept at a logical high state except when
shifting data into the control register The SLEEP and IDLE SERVO pins must be disabled (SLEEP

high and

IDLE SERVO

low) in order to shift data into the control register

CONTROL REGISTER DATA INPUT (CRD)

ControI register data input

CONTROL REGISTER CLOCK INPUT (CRC)

Positive-edge-active control register clock input

FREQUENCY LOCK CONTROL BAR INPUT (FLC)

This input enables or disables the frequency lock function during a

read operation It has no effect when READ GATE is disabled Frequency lock is automatically employed for the full
duration of the time READ GATE is disabled regardless of the level of this input When READ GATE is taken to a logical
high level while FLC is at a logical low level (frequency lock enabled) the PLL is forced to lock to the pattern frequency
(2T or 3T sync field) selected in the control register (PREAM

2T Bank (1 1) bit 4) When FLC is taken to a logical high

level the frequency lock action is terminated and the PLL employs a pulse gate to accommodate random disk data
patterns There are no setup or hold timing restrictions on the positive-going transition of FLC

PREAMBLE DETECTED OUTPUT (PDT)

This output issues a logical high state after the following sequence the

enabling of READ GATE the completion of the zero-phase-start sequence and the detection of approximately 16
sequential pulses of 2T or 3T preamble Following preamble detection this output remains latched high until READ
GATE is disabled This output will be at a logical low state whenever READ GATE is inactive (low)

READ GATE INPUT (RG)

This input receives the read mode control input signal from the controller active high for a

read operation There are no setup or hold timing restrictions on RG enabling or disabling

DELAY LINE OUTPUT (DLO)

This active low open collector output pin issues encoded read data (ERD) delayed by

the selected value in the delay line at the input to the synchronizing latch By viewing this signal's phase the user can
directly view the amount of window movement as the control register's strobe bits are changed

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