TL F 9338

DP8520ADP8521ADP8522A

microCMOS

Programmable

256k1M4M

Video

RAM

ControllerDrivers

PRELIMINARY

May 1992

DP8520A DP8521A DP8522A microCMOS Programmable
256k 1M 4M Video RAM Controller Drivers

General Description

The DP8520A 21A 22A video RAM controllers provide a
low cost single chip interface between video RAM and all
8- 16- and 32-bit systems The DP8520A 21A 22A gener-
ate all the required access control signal timing for VRAMs
An on-chip refresh request clock is used to automatically
refresh the VRAM array Refreshes and accesses are arbi-
trated on chip If necessary a WAIT or DTACK output in-
serts wait states into system access cycles including burst
mode accesses RAS low time during refreshes and RAS
precharge time after refreshes and back to back accesses
are guaranteed through the insertion of wait states Sepa-
rate on-chip precharge counters for each RAS output can
be used for memory interleaving to avoid delayed back to
back accesses because of precharge An additional feature
of the DP8522A is two access ports to simplify dual access-
ing Arbitration among these ports and refresh is done on
chip

Features

On chip high precision delay line to guarantee critical
VRAM access timing parameters

microCMOS process for low power

High capacitance drivers for RAS CAS DT OE and
VRAM address on chip

On chip support for nibble page and static column
VRAMs

Byte enable signals on chip allow byte writing in a word
size up to 16 bits with no external logic

Selection of controller speeds 20 MHz and 25 MHz

On board Port A Port B (DP8522A only) refresh arbitra-
tion logic

Direct interface to all major microprocessors (applica-
tion notes available)

4 RAS and 4 CAS drivers (the RAS and CAS configura-
tion is programmable)

of Pins

of Address

Largest

Direct Drive

Access

Control

(PLCC)

Outputs

VRAM

Memory

Ports

Possible

Capacity

Available

DP8520A

256 kbit

4 Mbytes

Single Access Port

DP8521A

1 Mbit

16 Mbytes

Single Access Port

DP8522A

4 Mbit

64 Mbytes

Dual Access Ports (A and B)

Block Diagram

DP8520A 21A 22A VRAM Controller

TL F 9338 � 5

FIGURE 1

TRI-STATE

is a registered trademark of National Semiconductor Corporation

PAL

is a registered trademark of and is used under license from Monolithic Memories Inc

C1995 National Semiconductor Corporation

RRD-B30M105 Printed in U S A

Table of Contents

1 0 INTRODUCTION

2 0 SIGNAL DESCRIPTIONS

2 1 Address R W and Programming Signals

2 2 VRAM Control Signals

2 3 Refresh Signals

2 4 Port A Access Signals

2 5 Port B Access Signals (DP8522A)

2 6 Common Dual Port Signals (DP8522A)

2 7 Power Signals and Capacitor Input

2 8 Clock Inputs

3 0 PORT A ACCESS MODES

3 1 Access Mode 0

3 2 Access Mode 1

4 0 REFRESH OPTIONS

4 1 Refresh Control Modes

4 1 1 Automatic Internal Refresh

4 1 2 Externally Controlled Burst Refresh

4 1 3 Refresh Request Acknowledge

4 2 Refresh Cycle Types

4 2 1 Conventional Refresh

4 2 2 Staggered Refresh

4 2 3 Error Scrubbing Refresh

4 3 Extending Refresh

4 4 Clearing the Refresh Address Counter

4 5 Clearing the Refresh Request Clock

5 0 PORT A WAIT STATE SUPPORT

5 1 WAIT Type Output

5 2 DTACK Type Output

5 3 Wait State Support for VRAM Transfer Cycles

5 4 Dynamically Increasing the Number of Wait States

5 5 Guaranteeing RAS Low Time and RAS Precharge

Time

6 0 DP8520A 21A 22A VIDEO RAM SUPPORT

6 1 Support for VRAM Transfer Cycles

6 2 Support for VRAM Access Cycles through Port A

7 0 ADDITIONAL ACCESS SUPPORT FEATURES

7 1 Address Latches and Column Increment

7 2 Address Pipelining

7 3 Delay CAS During Write Accesses

8 0 RAS AND CAS CONFIGURATION MODES

8 1 Byte Writing

8 2 Memory Interleaving

8 3 Address Pipelining

8 4 Error Scrubbing

8 5 Page Burst Mode

9 0 PROGRAMMING AND RESETTING

9 1 Mode Load Only Programming

9 2 Chip Selected Access Programming

9 3 External Reset

9 4 Definition of Programming Bits

10 0 TEST MODE

11 0 VRAM CRITICAL TIMING OPTIONS

11 1 Programming Values of t

RAH

and t

ASC

11 2 Calculation of t

RAH

and t

ASC

12 0 DUAL ACCESSING (DP8522A)

12 1 Port B Access Mode

12 2 Port B Wait State Support

12 3 Common Port A and Port B Dual Port Functions

12 3 1 GRANTB Output

12 3 2 LOCK Input

13 0 ABSOLUTE MAXIMUM RATINGS

14 0 DC ELECTRICAL CHARACTERISTICS

15 0 AC TIMING PARAMETERS

16 0 FUNCTIONAL DIFFERENCES BETWEEN THE

DP8520A 21A 22A AND THE DP8520 21 22

17 0 DP8520A 21A 22A USER HINTS

18 0 DESCRIPTION OF A DP8522A DP8500

SYSTEM INTERFACE

1 0 Introduction

The DP8520A 21A 22A are CMOS Video RAM controllers
that incorporate many advanced features including the ca-
pabilities of address latches refresh counter refresh clock
row column and refresh address multiplexor delay line re-
fresh access VRAM transfer cycle arbitration logic and
high capacitive drivers The programmable system interface
allows any manufacturer's microprocessor or bus to directly
interface via the DP8520A 21A 22A to VRAM arrays up to
64 Mbytes in size

After power up the DP8520A 21A 22A must first be pro-
grammed before accessing the VRAM The chip is pro-
grammed through the address bus

There are two methods of programming the chip The first
method mode load only is accomplished by asserting the
signal mode load ML A valid programming selection is pre-
sented on the row column bank and ECAS inputs then ML
is negated When ML is negated the chip is programmed
with the valid programming bits on the address bus

The second method chip selected access is accomplished
by asserting ML and performing a chip selected access
When CS and AREQ are asserted for the access the chip is
programmed During this programming access the pro-
gramming bits affecting the wait logic become effective im-
mediately allowing the access to terminate After the ac-
cess ML is negated and the rest of the programming bits
take effect

Once the DP8520A 21A 22A has been programmed a
60 ms initialization period is entered During this time the
DP8520A 21A 22A controllers perform refreshes to the
VRAM array so further VRAM warm up cycles are unneces-
sary

The DP8520A 21A 22A can now be used to access the
VRAM There are two modes of accessing with the control-
ler The two modes are Mode 0 which initiates RAS syn-
chronously and Mode 1 which initiates RAS asynchronous-
ly

To access the VRAM using Mode 0 the signal ALE is as-
serted along with CS to ensure a valid VRAM access ALE
asserting sets an internal latch and only needs to be pulsed
and not held throughout the entire access On the next ris-
ing clock edge after the latch is set RAS will be asserted
for that access The DP8520A 21A 22A will place the row
address on the VRAM address bus guarantee the pro-
grammed value of row address hold time of the VRAM
place the column address on the VRAM address bus guar-
antee the programmed value of column address setup time
and assert CAS AREQ can be asserted anytime after the
clock edge which starts the access RAS RAS and CAS will
extend until AREQ is negated

The other access mode Mode 1 is asynchronous to the
clock

When ADS is asserted

RAS is asserted

The

DP8520A 21A 22A will place the row address on the
VRAM address bus guarantee the programmed value of
row address hold time place the column address on the
VRAM address bus guarantee the programmed value of
column address setup time and assert CAS AREQ can be
tied to ADS or can be asserted after ADS is asserted AREQ
negated will terminate the access

The DP8520A 21A 22A also provides full support for
VRAM transfer cycles

To begin the cycle

the input

AVSRLRQ Advanced Video Shift Register Load Request is

asserted and must precede the input VSRL Video Shift
Register Load asserting by enough CLK periods to guaran-
tee any access in progress or pending refresh can finish
VSRL asserting causes DT OE to transition low immediate-
ly Both VSRL and DT OE assert before RAS and CAS as-
sert for the transfer The cycle is ended by DT OE negating
This is caused by either VSRL negating or by four rising
edges of CLK from VSRL asserting whichever comes first

The DP8520A 21A 22A have greatly expanded refresh ca-
pabilities compared to other VRAM controllers There are
three modes of refreshing available These modes are inter-
nal automatic refreshing

externally controlled burst re-

freshing and refresh request acknowledge refreshing Any
of these modes can be used together or separately to
achieve the desired results In any combination of these
modes the programming of ECAS0 determines the use of
the RFIP (RFRQ) pin ECAS0 asserted during programming
causes this pin to function as RFIP which will assert just
prior to a refresh cycle and will negate when the refresh is
completed ECAS0 negated during programming causes
this pin to function as RFRQ which indicates an internal
refresh request when asserted

When using internal automatic refreshing the DP8520A
21A 22A will generate an internal refresh request from the
refresh request clock The DP8520A 21A 22A will arbitrate
between the refresh requests and accesses Assuming an
access is not currently in progress the DP8520A 21A 22A
will grant a refresh assert RFIP if programmed and on the
next positive clock edge refreshing will begin If an access
had been in progress the refresh will begin after the access
has terminated

To use externally controlled burst refresh the user disables
the

internal

refresh

request

asserting

the

input

DISRFRSH A refresh can now be externally requested by
asserting the input RFSH The DP8520A 21A 22A will arbi-
trate between the external refresh request and accesses
Assuming an access is not currently in progress

the

DP8520A 21A 22A will grant a refresh assert RFIP if pro-
grammed and on the next positive clock edge refreshing
will begin If an access had been in progress the refresh
would take place after the access has terminated

With refresh request acknowledge mode the DP8520A
21A 22A broadcasts the internal refresh request to the sys-
tem through the RFRQ output pin External circuitry can de-
termine when to refresh the VRAM through the RFSH input

The controllers have three types of refreshing available
conventional staggered and error scrubbing Any refresh
control mode can be used with any type of refresh In a
conventional refresh all of the RAS outputs will be asserted
and negated at once In a staggered refresh the RAS out-
puts will be asserted one positive clock edge apart Error
scrubbing is the same as conventional refresh except that a
CAS will be asserted during a refresh allowing the system to
run that data through an EDAC chip and write it back to
memory if a single bit error has occurred The refreshes
can be extended with the EXTEND REFRESH input
EXTNDRF

The DP8520A 21A 22A have wait support available as
DTACK or WAIT Both are programmable DTACK Data
Transfer ACKnowledge is useful for processors whose wait
signal is active high WAIT is useful for processors whose

1 0 Introduction

(Continued)

wait signal is active low The user can choose either at pro-
gramming These signals are used by the on-chip arbitor to
insert wait states to guarantee the arbitration between ac-
cesses and refreshes or precharge Both signals are inde-
pendent of the access mode chosen

DTACK will assert a programmed number of clock edges
from the event that starts the access RAS DTACK will be
negated when the access is terminated by AREQ being
negated DTACK can also be programmed to toggle with
the ECAS inputs during burst page mode accesses

WAIT is asserted during the start of the access (ALE and
CS or ADS and CS) and will negate a number of clock
edges from the event that starts the access RAS After
WAIT is negated it will stay negated until the next access
WAIT can also be programmed to toggle with ECAS inputs
during a burst page mode access

Both signals can be dynamically delayed further through the
WAITIN signal to the DP8520A 21A 22A

The DP8520A 21A 22A have address latches used to
latch the bank row and column address inputs Once the
address is latched a column increment feature can be used
to increment the column address The address latches can
also be programmed to be fall through

The RAS and CAS drivers can be configured to drive a one
two or four bank memory array up to 32 bits in width The
two ECAS signals can then be used to select one pair of
CAS drivers for byte writing with no external logic for sys-
tems with a word length of up to 16 bits

When configuring the DP8520A 21A 22A for more than
one bank memory interleaving can be used By tying the
low order address bits to the bank select lines B0 and B1
sequential back to back accesses will not be delayed since
the DP8520A 21A 22A have separate precharge counters
per bank The DP8520A 21A 22A are capable of perform-
ing address pipelining In address pipelining the DP8520A
21A 22A guarantee the column address hold time and
switch the internal multiplexor to place the row address on
the address bus At this time another memory access to
another bank can be initiated

The DP8522A has all the features previously mentioned
Unlike the DP8520A 21A the DP8522A has a second port
to allow a second CPU to access the memory array This
port Port B has two control signals to allow a CPU to ac-
cess the VRAM array These signals are access request for
Port B AREQB and Advanced Transfer ACKnowledge for
Port B ATACKB Two other signals are used by both Port A
and Port B for dual accessing purposes The signals are
lock LOCK and grant Port B GRANTB All arbitration for
the two ports and refresh is done on-chip by the DP8522A
through the insertion of wait states Since the DP8522A has
only one input address bus the address lines have to be
multiplexed externally The signal GRANTB can be used for
this purpose since it is asserted when Port B has access to
the VRAM array and negated when Port A has access to the
VRAM array Once a port has access to the array the other
port can be ``locked out'' by asserting the input LOCK
AREQB when asserted is used by Port B to request an
access ATACKB when asserted signifies that access RAS
has been asserted for the requested Port B access By us-
ing ATACKB the user can generate an appropriate WAIT or
DTACK like signal for the Port B CPU

The following explains the terminology used in this data
sheet The terms negated and asserted are used Asserted
refers to a ``true'' signal Thus ``ECAS0 asserted'' means
the ECAS0 input is at a logic 0 The term ``COLINC assert-
ed'' means the COLINC input is at a logic 1 The term negat-
ed refers to a ``false'' signal Thus ``ECAS0 negated''
means the ECAS0 input is at a logic 1 The term ``COLINC
negated'' means the input COLINC is at a logic 0 The table
shown below clarifies this terminology

Signal

Action

Logic Level

Active High

Asserted

High

Active High

Negated

Low

Active Low

Asserted

Low

Active Low

Negated

High

Электронный компонент: DP8520AV-25