TL H 10747

DS3875

Futurebus

Arbitration

Controller

November 1995

DS3875 Futurebus

Arbitration Controller

General Description

The DS3875 Futurebus

Arbitration Controller is a member

of National Semiconductor's Futurebus

chip set designed

specifically for the IEEE 896 1 Futurebus

standard The

DS3875 implements Distributed Arbitration and Distributed
Arbitration messages in a single chip

The DS3875 interfaces with Futurebus

through the

DS3885 BTL Arbitration Transceiver and the DS3884A BTL
Handshake Transceiver

The DS3885 BTL Arbitration

Transceiver incorporates the competition logic needed for
the Arbitration Number signal lines The DS3884A BTL
Handshake Transceiver has selectable Wired-OR receiver
glitch filtering The DS3884A is used for the Arbitration Se-
quencing and Arbitration Condition signal lines

Additional transceivers included in the Futurebus

chip set

are the DS3883A BTL 9-bit Data Transceiver and the
DS3886A BTL 9-bit Latching Data Transceiver

The

DS3886A transceiver features edge-triggered latches in the
driver which may be bypassed during a fall-through mode
and a transparent latch in the receiver The DS3883A trans-
ceiver has no latches in either direction

The Logical Interface Futurebus

Engine (LIFE) I O Proto-

col Controller with 64-bit Data Path incorporates the Com-
pelled Mode Futurebus

Parallel Protocol The Protocol

Controller handles all the handshaking signals between the
Futurebus

and the local bus interfaces and incorporates

a DMA Controller with built-in FIFOs for fast queueing

Features

The controller implements the complete requirements
of the IEEE 896 1 specification as a subset of its fea-
tures

Supports Arbitration message sending and receiving

Supports the two modes of operation (RESTRICTED
UNRESTRICTED)

Software configurable double single pass operation
slow fast

IBA Parking

and

restricted unrestricted

modes of arbitration

Built-in 1 ms timer for use in the arbitration cycle

User programmable 16 arbitration delays (8 slow and
8 fast)

Built-in PLL for accurate delays

The PLL accepts

clocks from 2 MHz to 40 MHz in steps of 1 MHz

Signal to unlock slave modules on transfer of tenure
Auto unlock through a dummy cycle if the current mas-
ter locked resources

Programmable delay for releasing ar

after issuing

COMPETE IBA

CMPT This is to ensure the assertion

of the arbitration number during competition before the
release of ar

Also this delay ensures there is suffi-

cient time to assert the AD DATA lines during Idle Bus
Arbitration before the release of ar

Read Write facility with data acknowledge for the host
to load arbitration numbers

an arbitration message

and control registers

On chip parity generator unloads the host of the addi-
tional parity generation function

Separate interrupts to indicate error occurrence and ar-
bitration message received Interrupts cleared on a reg-
ister write Error status is available in a separate status
register

A special output pin to indicate that a POWERFAIL
message was received

Hardwired register to hold the first word of the arbitra-
tion message

FIFO strobe provided to store more than one arbitration
message externally to prevent overrun

Idle Bus Arbitration (IBA) supported

Parking implemented

Bus initialization system reset and Live-insertion sup-
ported (The logic to detect these conditions must be
implemented externally )

Testability in the form of reading from key registers
which include the STATE MCW 1 ms timer and pro-
grammable input clock divider

TL H 10747 � 1

National's Futurebus

Chip Set Diagram

C1995 National Semiconductor Corporation

RRD-B30M115 Printed in U S A

Table of Contents

1 0 INTRODUCTION TO FUTUREBUS

2 0 INTRODUCTION TO FUTUREBUS

ARBITRATION

2 1 The Arbitration States

3 0 INTRODUCTION TO DS3875 ARBITRATION CONTROLLER

3 1 Using the DS3875 in 896 1 Compliant Mode

4 0 DS3875 INTERFACES

5 0 ARBITRATING FOR FUTUREBUS

5 1 Unrestricted Restricted Modes of Operation

5 2 The Arbitration Number and Arbitration Circuit

5 2 1 Priority Field (PR)

5 2 2 Round Robin Field (RR)

5 2 3 Unique Field (U)

5 3 Arbitration Categories

5 3 1 Competitor for the Parallel Bus

5 3 2 Competitor to Send a Message

5 3 2 1 Using an External FIFO to Store Messages

5 3 3 By-Stander

5 3 4 By-Stander who decides to invoke Preemption

5 3 5 Master

5 3 6 Master Elect

5 4 Futurebus

Optional Means of Arbitration

5 4 1 Idle Bus Arbitration (IBA)

5 4 1 1 Masters Support Circuitry to Enable IBA

5 4 1 2 Modules Support Circuitry to Participate in IBA

5 4 2 Parking

5 5 The Arbitration Phases

5 5 1 Phase 0 Idle Phase

5 5 1 1 Phase 0 Normal Arbitration Events That Cause a Transition to Phase 1

5 5 1 2 Phase 0 Idle Bus Arbitration Events That Cause a Transition to Phase 1

5 5 1 3 Phase 0 Parking

5 5 2 Phase 1 Decision Phase

5 5 2 1 Phase 1 Idle Bus Arbitration Events That Cause a Transition to Phase 2

5 5 3 Phase 2 Competition Phase

5 5 3 1 Phase 2 Idle Bus Arbitration Events That Cause a Transition to Phase 3

5 5 4 Phase 3 Error Check Phase

5 5 4 1 Phase 3 Idle Bus Arbitration Events That Cause a Transition to Phase 4

5 5 5 Phase 4 Master Release Phase

5 5 6 Phase 5 Tenure Transfer Phase

6 0 THE DS3875 ARBITRATION CONTROLLER SUPPORT OF LOCKING AND UNLOCKING

7 0 REGISTER DESCRIPTION

7 1 ALL1S

7 2 TCXN0

7 3 TCXN1

7 4 TXMSG

7 5 CTRL1

Pin Definition

of Pins

Type

Description

SIGNAL TO FROM THE HANDSHAKE TRANSCEIVER

APO

Arbitration handshake signal from the controller

AQO

Arbitration handshake signal from the controller

ARO

Arbitration handshake signal from the controller

AC0O

Arbitration condition signal from the controller

AC1O

Arbitration condition signal from the controller

API

Arbitration handshake signal from Futurebus

This signal is the filtered and inverted version

of the Futurebus

backplane signal AP

AQI

Arbitration handshake signal from Futurebus

This signal is the filtered and inverted version

of the Futurebus

backplane signal AQ

ARI

Arbitration handshake signal from Futurebus

This signal is the filtered and inverted version

of the Futurebus

backplane signal AR

AC0I

Arbitration condition signal from Futurebus

AC1I

Arbitration condition signal from Futurebus

SIGNAL TO FROM THE ARBITRATION TRANSCEIVER

(Note These pins are mapped to from the DS3885 Futurebus

Arbitration Transceiver )

CN(7 0)

I O

The bus to carry competition number to from the arbitration transceiver

CNp

Parity bit of the competition number

CMPT

Enables the Arbitration number onto Futurebus

Direction control for the competition number bus to from the transceiver

Latch enable for latching the Arbitration number from the controller into the transceiver

PER

PARITY ERROR

Indicates that a parity error was detected on the winner's arbitration number

WIN

Win signal when competing greater than signal when not competing (used to preempt)

ALL1

Indicates that all the arbitration number lines on the bus are asserted (used for messages)

SIGNALS TO FROM THE PARALLEL PROTOCOL CONTROLLER

BRQ

BUS REQUEST

Indicates to the controller to acquire the bus for the module's use

BGRNT

BUS GRANT

Signal asserted by the controller after the detection of a bus request The

module can start using the bus

RINT

Will put the arbitration controller in phase 0 and release all the bus lines except AR

selective reset is performed The rising edge will release controller from phase 0 This reset is
to be used for bus initialization

RST

Reset signal from the host An internal reset is performed All bus signals are released The
rising edge will put the controller in phase 0 (same as power-up reset)

HALT

Will halt the arbitration controller in phase 0 This signal is for use during live insertion

ENDT

END OF TENURE

Indicates the true end of bus tenure of the current master This line may be

asserted only after all the parallel protocol lines are released (Generated via external logic
from BRQ released )

Pin Definition

(Continued)

of Pins

Type

Description

SIGNALS TO FROM THE HOST

(CPU Plus External Interface Logic)

DATA(7 0)

I O

Data bus for the host to access the register bank of the controller

ADD(3 0)

Address bits for the register bank of the controller

CHIP SELECT

The host can read or write to from the controller

Read write signal from the host

DSACK

Data acknowledge pin for host read write

SEL

SELECT

Determines how the controller latches in data A ``1'' on the pin uses the rising

edge of CS

A ``0'' on the pin uses the falling edge of DSACK

MGRQ

MESSAGE REQUEST

Indicates to the controller to send an arbitration message

MGTX

MESSAGE TRANSMIT

Indicates the successful transmission of an arbitration message

ERINT

ERROR INTERRUPT

Indicates that an error occurred during the arbitration cycle

MGINT

MESSAGE INTERRUPT

Indicates the reception of an arbitration message

PFINT

POWER FAIL INTERRUPT

Indicates that a powerfail message was received

EXTERNAL LOGIC

IBA

CMPT

Signal to indicate that the Parallel Protocol controller may assert its bit on the ADDRESS
DATA bus if it is participating in an Idle Bus Arbitration

IBA

This signal indicates that IBA was successful If this module was a competitor in the IBA
competition ( BRQ ) then this module is the winner and now the bus master If this module
was the master but did not compete in the IBA competition and IBA was successful then the
M bit (Status register) is negated

CANCEL

Indicates the start of the disconnection phase of the current master or cancel the current
arbitration cycle

LKD

LOCKED

Signal to indicate that resources have been locked in the current tenure and

hence generate either a dummy cycle if current master or UNLK otherwise (Decoded from
Futurebus

Command port output from Data Path Unit )

UNLK

UNLOCK

Transfer of tenure indication to the parallel protocol controller for unlocking its

resources Generated only if the LKD signal is asserted (To external logic )

FSTR

FIFO STROBE

Signal generated to load an external FIFO for received arbitration messages

CLK

Clock input to the internal PLL

External capacitor input for PLL

0 1 mF

Электронный компонент: DS3875V