DS3893A
BTL TURBOTRANSCEIVER
TM
General Description
The TURBOTRANSCEIVER is designed for use in very high
speed bus systems. The bus terminal characteristics of the
TURBOTRANSCEIVER are referred to as "Backplane
Transceiver Logic" (BTL). BTL is a new logic signaling stan-
dard that has been developed to enhance the performance
of backplane buses. BTL compatible transceivers feature
low output capacitance drivers to minimize bus loading, a 1V
nominal signal swing for reduced power consumption and
receivers with precision thresholds for maximum noise im-
munity. This new standard eliminates the settling time de-
lays, that severely limit the TTL bus performance, to provide
significantly higher bus transfer rates.
The TURBOTRANSCEIVER is compatible with the require-
ments of the proposed IEEE 896 Futurebus draft standard. It
is similar to the DS3896/97 BTL TRAPEZOIDAL
TM
Trans-
ceivers but the trapezoidal feature has been removed to
improve the propagation delay. A stripline backplane is there-
fore required to reduce the crosstalk induced by the faster
rise and fall times. This device can drive a 10
load with a
typical propagation delay of 3.5 ns for the driver and 5 ns for
the receiver.
When multiple devices are used to drive a parallel bus, the
driver enables can be tied together and used as a common
control line to get on and off the bus. The driver enable delay
is designed to be the same as the driver propagation delay in
order to provide maximum speed in this configuration. The
low input current on the enable pin eases the drive required
for the common control line.
The bus driver is an open collector NPN with a Schottky
diode in series to isolate the transistor output capacitance
from the bus when the driver is in the inactive state. The
active output low voltage is typically 1V. The bus is intended
to be operated with termination resistors (selected to match
the bus impedance) to 2.1V at both ends. Each of the
resistors can be as low as 20
.
Features
n
Fast single ended transceiver (typical driver enable and
receiver propagation delays are 3.5 ns and 5 ns)
n
Backplane Transceiver Logic (BTL) levels (1V logic
swing)
n
Less than 5 pF bus-port capacitance
n
Drives densely loaded backplanes with equivalent load
impedances down to 10
n
4 transceivers in 20 pin PCC package
n
Specially designed for stripline backplanes
n
Separate bus ground returns for each driver to minimize
ground noise
n
High impedance, MOS and TTL compatible inputs
n
TRI-STATE
TM
control for receiver outputs
n
Built-in bandgap reference provides accurate receiver
threshold
n
Glitch free power up/down protection on all outputs
n
Oxide isolated bipolar technology
Connection and Logic Diagram
00869801
Order Number DS3893AV
See NS Package Number V20A
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
TRAPEZOIDAL
TM
and TURBOTRANSCEIVER
TM
are trademarks of National Semiconductor Corp.
March 1997
DS3893A
BTL
TURBOTRANSCEIVER
2004 National Semiconductor Corporation
DS008698
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage
6.5V
Control Input Voltage
5.5V
Driver Input and Receiver Output
5.5V
Driver Output Receiver Input Clamp
Current
15 mA
Power Dissipation at 70C
900 mW
Storage Temperature Range
-65C to +150C
Lead Temperature (Soldering, 3
sec.)
260C
Recommended Operating
Conditions
Min
Max
Units
Supply Voltage, V
CC
4.5
5.5
V
Bus Termination Voltage (V
T
)
2.0
2.2
V
Operating Free Air Temperature
0
70
C
Electrical Characteristics
(Notes 2, 3, 4)
T
A
= 0 to +70C, V
CC
= 5V
10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER AND CONTROL INPUT: (DE, RE , Dn)
V
IH
Input High Voltage
2.0
V
V
IL
Input Low Voltage
0.8
V
I
I
Input Leakage Current
DE = RE = Dn = V
CC
100
A
I
IH
Input High Current
DE = RE = Dn = 2.5V
20
A
I
IL
Dn Input Low Current
Dn = 0.5V, DE = V
CC
= Max
-200
A
DE Input Low Current
DE = 0.5V, Dn = V
CC
= Max
-500
A
RE Input Low Current
RE = 0.5V, V
CC
= Max
-100
A
V
CL
Input Diode Clamp Voltage
I
clamp
= -12 mA
-1.2
V
DRIVER OUTPUT/RECEIVER INPUT: (Bn)
V
OLB
Output Low Bus Voltage
Dn = DE = V
IH
(Figure 2)
0.75
1.0
1.2
V
R
T
= 10
, V
T
= 2.2V
Dn = DE = V
IH
(Figure 2)
0.75
1.0
1.1
V
R
T
= 18.5
, V
T
= 2.14
I
ILB
Output Bus Current (Power On)
Dn = DE = 0.8V, V
CC
= Max
-250
100
A
Bn = 0.75V
I
IHB
Output Bus Current (Power Off)
Dn = DE = 0.8V, V
CC
= 0V
100
A
Bn = 1.2V
V
OCB
Driver Output Positive Clamp
V
CC
= Max or 0V, Bn = 1 mA
2.9
V
V
CC
= Max or 0V, Bn = 10 mA
3.2
V
V
OHB
Output High Bus Voltage
V
CC
= Max, Dn = 0.8V (Figure 2)
1.90
V
V
T
= 2.0V, R
T
= 10
V
TH
Receiver Input Threshold
1.47
1.55
1.62
V
RECEIVER OUTPUT: (Rn)
V
OH
Voltage Output High
Bn = 1.2V, I
oh
= -3 mA, RE = 0.8V
2.5V
V
V
OL
Voltage Output Low
Bn = 2V, I
ol
= 6 mA, RE = 0.8V
0.35
0.5
V
I
OZ
TRI-STATE Leakage
V
o
= 2.5V, RE = 2V
20
A
V
o
= 0.5V, RE = 2V
-20
A
I
OS
Output Short Circuit Current
Bn = 1.2V, V
o
= 0V
-80
-120
-200
mA
(Note 5)
RE = 0.8V, V
CC
= Max
I
CC
Supply Current
Dn = DE = RE = V
IH
, V
CC
= Max
70
95
mA
Note 1: "Absolute maximum ratings" are those beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should
be operated at these limits. The table of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.
Note 3: All typicals are given for V
CC
= 5V and T
A
= 25C.
Note 4: Unused inputs should not be left floating. Tie unused inputs to either V
CC
or GND thru a resistor.
Note 5: Only one output at a time should be shorted.
DS3893A
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2
Switching Characteristics
T
A
= 0 to +70C, V
CC
= 5V
10%
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DRIVER: (Figure 3 and Figure 6)
t
PHL
Driver Input to Output
V
T
= 2V R
T
= 10
, C
L
= 30 pF, DE = 3V
1
3.5
7
ns
t
PLH
Driver Input to Output
V
T
= 2V, R
T
= 10
, C
L
= 30 pF, DE = 3V
1
3.5
7
ns
t
r
Output Rise time
V
T
= 2V, R
T
= 10
, C
L
= 30 pF, DE = 3V
1
2
5
ns
t
f
Output Fall Time
V
T
= 2V, R
T
= 10
, C
L
= 30 pF, DE = 3V
1
2
5
ns
t
skew
Skew Between Drivers
(Note 6)
1
ns
in Same Package
DRIVER ENABLE: (Figure 3 and Figure 6)
t
PHL
Enable Delay
V
T
= 2V, R
T
= 10
, C
L
= 30 pF, Dn = 3V
1
3.5
7
ns
t
PLH
Disable Delay
V
T
= 2V, R
T
= 10
, C
L
= 30 pF, Dn = 3V
1
3.5
7
ns
RECEIVER: (Figure 4 and Figure 7)
t
PHL
Receiver Input to Output
C
L
= 50 pF, RE = DE = 0.3V, S3 Closed
2
5
8
ns
t
PLH
Receiver Input to Output
C
L
= 50 pF, RE = DE = 0.3V, S3 Open
2
5
8
ns
t
skew
Skew Between Receivers
(Note 6)
1
ns
in Same Package
RECEIVER ENABLE: (Figure 5 and Figure 8)
t
ZL
Receiver Enable to
C
L
= 50 pF, R
L
= 500, DE = 0.3V
2
6
12
ns
Output Low
S2 Open
Bn = 2V
t
ZH
Receiver Enable to
C
L
= 50 pF, R
L
= 500, DE = 0.3V
2
5
12
ns
Output High
S1 OpenBn = 1V
t
LZ
Receiver Disable
C
L
= 50 pF, R
L
= 500, DE = 0.3V
1
5
8
ns
From Output Low
S2 OpenBn = 2V
t
HZ
Receiver Disable
C
L
= 50 pF, R
L
= 500, DE = 0.3V
1
4
8
ns
From Output High
S1 OpenBn = 1V
Note 6: t
D
and t
R
skew is an absolute value, defined as differences seen in propagation delays between each of the drivers or receivers in the same package of
the same delay, V
CC
, temperature and load conditions.
00869812
FIGURE 1. Equivalent Bus Output
00869802
Note: n = 1, 2, 3, 4
FIGURE 2. Driver Output Voltage
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3
AC Test Circuits
Switching Time Waveforms
00869803
FIGURE 3.
00869804
FIGURE 4.
00869805
Note:
Unless Otherwise Specified
The Switches are Closed
FIGURE 5.
00869806
FIGURE 6. Driver Propagation Delay
DS3893A
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4
Switching Time Waveforms
(Continued)
Typical Application
00869809
Application Information
Due to the high current and very high speed capability of the
TURBOTRANSCEIVER's driver output stage, circuit board
layout and bus grounding are critical factors that affect the
system performance.
Each of the TURBOTRANSCEIVER's bus ground pins
should be connected to the nearest backplane ground pin
with the shortest possible path. The ground pins on the
connector should be distributed evenly through its length.
Although the bandgap reference receiver threshold provides
sufficient DC noise margin (Figure 9), ground noise and
ringing on the data paths could easily exceed this margin if
the series inductance of the traces and connectors are not
kept to a minimum. The bandgap ground pin should be
returned to the connector through a separate trace that does
not carry transient switching currents. The transceivers
should be mounted as close as possible to the connector. It
should be noted that even one inch of trace can add a
significant amount of ringing to the bus signal.
00869807
FIGURE 7. Receiver Propagation Delay
00869808
Note: t
R
= t
F
4 ns From 10% to 90%
Note: n = 1, 2, 3, 4
FIGURE 8. Receiver Enable and Disable Times
00869810
FIGURE 9. Noise Margin
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