DS90C241/DS90C124
5-35MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS90C241/124 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths
that in turn reduce PCB layers, cable width, and connector
size and pins.
The DS90C241/124 incorporates LVDS signaling on the
high-speed I/O. LVDS provides a low power and low noise
environment for reliably transferring data over a serial trans-
mission path. By optimizing the serializer output edge rate
for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
n
5 MHz35 MHz clock embedded and DC-Balancing
1:24 and 24:1 data transmissions
n
User defined pre-emphasis driving ability through
external resistor on LVDS outputs and capable to drive
up to 10 meters shielded twisted-pair cable
n
User selectable clock edge for parallel data on both TX
and RX
n
Supports AC-coupling interface
n
Individual power-down controls for both TX and RX
n
Embedded clock CDR (clock and data recovery) on RX
and no external source of reference clock needed
n
All codes RDL (random data lock) to support
hot-pluggable applications
n
LOCK output flag to ensure data integrity at RX side
n
Balanced T
SETUP
/T
HOLD
between RCLK and RDATA on
RX side
n
PTO (progressive turn-on) LVTTL O/P to minimize the
SSO effects
n
All LVTTL inputs and control pins have internal pulldown
except PRE
n
On-chip filters for PLLs on TX and RX
n
48 pin TQFP package for both TX and RX
n
Pure CMOS .35 m process
n
Power supply range 3.3V
10%
n
Temperature range 40C to +105C
n
8 kV HBM ESD structure
Block Diagram
20171901
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
PRELIMINARY
January 2006
DS90C241/DS90C124
5-35MHz
DC-Balanced
24-Bit
L
VDS
Serializer
and
Deserializer
2006 National Semiconductor Corporation
DS201719
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
LVCMOS/LVTTL Input Voltage
-0.3V to (V
CC
+0.3V)
LVCMOS/LVTTL Output
Voltage
-0.3V to (V
CC
+0.3V)
LVDS Receiver Input Voltage
-0.3V to 3.9V
LVDS Driver Output Voltage
-0.3V to 3.9V
LVDS Output Short Circuit
Duration
10 ms
Junction Temperature
+150C
Storage Temperature
-65C to +150C
Lead Temperature
(Soldering, 4 seconds)
+260C
Maximum Package Power Dissipation Capacity Package
De-rating:
48L TQFP
1/
JA
CW above +25C
DS90C241
JA
45.8 (4L*); 75.4 (2L*) C/W
JC
21.0C/W
DS90C124
JA
45.4 (4L*); 75.0 (2L*)C/W
JC
21.1C/W
*JEDEC
ESD Rating (HBM)
>
8 kV
ESD Rating (ISO10605)
DS90C241 meets ISO 10605
Contact Discharge (D
OUT+
, D
OUT-
) to GND
10 kV
Air Discharge (D
OUT+
, D
OUT-
) to GND
30 kV
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (V
CC
)
3.0
3.3
3.6
V
Operating Free Air
Temperature (T
A
)
-40
+25
+105
C
Clock Rate
5
35
MHz
Supply Noise
100
mV
P-P
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
LVCMOS/LVTTL DC SPECIFICATIONS
V
IH
High Level Voltage
Tx: DIN[0:23], TCLK,
DEN, TRFB, DCAOFF,
DCBOFF, VODSEL
Rx: RRFB, REN
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-0.7
-1.2
V
I
IN
Input Current
V
IN
= 0V or 3.6V
-10
2
+10
A
Tx: TPWDNB
Rx: RPWDNB
-20
5
+20
A
V
OH
High Level Output Voltage
I
OH
= -2 mA
ROUT[0:23], RCLK,
LOCK
2.3
3.0
V
CC
V
V
OL
Low Level Output Voltage
I
OL
= +2 mA
GND
0.33
0.5
V
I
OS
Output Short Circuit Current
V
OUT
= 0V
-110
mA
I
OZ
TRI-STATE
Output Current
RPWRDN = 0.8V,
V
OUT
= 0V or V
CC
ROUT[0:23], RCLK,
LOCK
-15
0.4
+15
A
LVDS DC SPECIFICATIONS
V
TH
Differential Threshold High
Voltage
V
CM
= +1.2V
R
IN+
, R
IN-
+100
mV
V
TL
Differential Threshold Low
Voltage
-100
mV
I
IN
Input Current
V
IN
= 2.4V,
V
CC
= 3.6V or 0V
100
A
V
IN
= 0V, V
CC
= 3.6V or 0V
100
A
DS90C241/DS90C124
www.national.com
2
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
LVDS DC SPECIFICATIONS
V
OD
Output Differential Voltage
(D
OUT+
)(D
OUT-
) (Figure 16)
R
L
= 100
, w/o pre-emphasis
VODSEL = L
(VODSEL = H)
D
OUT+
, D
OUT-
250
(500)
400
(800)
600
(1200)
mV
V
OD
Output Differential Voltage
Unbalance
R
L
= 100
, w/o pre-emphasis
10
50
mV
V
OS
Offset Voltage
R
L
= 100
, w/o pre-emphasis
1.05
1.2
1.25
V
V
OS
Offset Voltage Unbalance
R
L
= 100
, w/o pre-emphasis
10
50
mV
I
OS
Output Short Circuit Current
DOUT = 0V, DIN = H,
TPWRDND = 2.4V
-35
-50
-70
mA
I
OZ
TRI-STATE Output Current
TPWRDND = 0.8V,
DOUT = 0V or V
DD
-10
1
10
A
SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs
I
CCT
Serializer (Tx)
Total Supply Current
(includes load current)
R
L
= 100
Pre-emphasis = OFF
Checker-board pattern
VODSEL=L (Figure 1)
f = 35 MHz
105
mA
R
L
= 100
RPRE = 6 k
Checker-board pattern
VODSEL=L (Figure 1)
f = 35 MHz
120
mA
Serializer (Tx)
Total Supply Current
(includes load current)
R
L
= 100
R
PRE
= OFF
Random pattern
VODSEL=L
f = 35 MHz
65
mA
R
L
= 100
R
PRE
= 6 k
Random pattern
VODSEL=L
f = 35 MHz
80
mA
I
CCTZ
Serializer (Tx)
Supply Current Power-down
TPWRDNB = 0.8V
200
500
A
I
CCR
Deserializer (Rx)
Total Supply Current
(includes load current)
C
L
= 8 pF
Checker-board pattern
LVTTL Output (Figure 2)
f = 35 MHz
180
mA
Deserializer (Rx)
Total Supply Current
(includes load current)
C
L
= 8 pF
Random pattern
LVTTL Output
f = 35 MHz
110
mA
I
CCRZ
Deserializer (Rx)
Supply Current Power-down
RPWRDND = 0.8V
500
750
A
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max Units
t
TCP
Transmit Clock Period
28.6
T
200
ns
t
TCIH
Transmit Clock High Time
0.4T
0.5T
0.6T
ns
t
TCIL
Transmit Clock Low Time
0.4T
0.5T
0.6T
ns
t
CLKT
TCLK Input Transition Time
3
6
ns
t
JIT
TCLK Input Jitter
(Note 9)
200
ns
DS90C241/DS90C124
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3
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
LLHT
LVDS Low-to-High Transition Time
R
L
= 100
,
C
L
= 10 pF to GND
VODSEL = L
(Figure 3)
0.6
ns
t
LHLT
LVDS High-to-Low Transition Time
0.6
ns
t
DIS
DIN (0:23) Setup to TCLK
R
L
= 100
,
C
L
= 10 pF to GND
(Note 8)
5
ns
t
DIH
DIN (0:23) Hold from TCLK
5
ns
t
HZD
DOUT
HIGH to TRI-STATE Delay
R
L
= 100
,
C
L
= 10 pF to GND
(Note 4) (Figure 7)
5
ns
t
LZD
DOUT
LOW to TRI-STATE Delay
5
ns
t
ZHD
DOUT
TRI-STATE to HIGH Delay
5
ns
t
ZLD
DOUT
TRI-STATE to LOW Delay
5
ns
t
PLD
Serializer PLL Lock Time (Figure 8)
R
L
= 100
10
ms
t
SD
Serializer Delay (Figure 9)
R
L
= 100
VODSEL = L, TRFB = H
3.5T + 2.85
ns
R
L
= 100
VODSEL = L, TRFB = L
3.5T + 2.85
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max Units
t
RCP
Receiver out Clock Period
(Note 8)
t
RCP
= t
TCP
RCLK
28.6
200
ns
t
RDC
RCLK Duty Cycle
RCLK
45
50
55
%
t
CLH
CMOS/TTL Low-to-High
Transition Time
C
L
= 8 pF
(lumped load)
(Figure 4)
ROUT [0:23],
LOCK, RCLK
2.5
3.5
ns
t
CHL
CMOS/TTL High-to-Low
Transition Time
2.5
3.5
ns
t
ROS
ROUT (0:7) Setup Data to
RCLK (Group 1)
(Figure 11)
ROUT [0:7]
(29/56)*t
RCP
(2/5)*
t
RCP
ns
t
ROH
ROUT (0:7) Hold Data to
RCLK (Group 1)
(Figure 11)
(27/56)*t
RCP
(2/5)*
t
RCP
ns
t
ROS
ROUT (8:15) Setup Data to
RCLK (Group 2)
(Figure 11)
ROUT [8:15],
LOCK
0.5*t
RCP
(2/5)*
t
RCP
ns
t
ROH
ROUT (9:15) Hold Data to
RCLK (Group 2)
(Figure 11)
0.5*t
RCP
(2/5)*
t
RCP
ns
t
ROS
ROUT (16:23) Setup Data to
RCLK (Group 3)
(Figure 11)
ROUT [16:23]
(27/56)*t
RCP
(2/5)*
t
RCP
ns
t
ROH
ROUT (16:23) Hold Data to
RCLK (Group 3)
(Figure 11)
(29/56)*t
RCP
(2/5)*
t
RCP
ns
t
HZR
HIGH to TRI-STATE Delay
(Figure 12)
ROUT [0:23],
RCLK, LOCK
3
10
ns
t
LZR
LOW to TRI-STATE Delay
3
10
ns
t
ZHR
TRI-STATE to HIGH Delay
3
10
ns
t
ZLR
TRI-STATE to LOW Delay
3
10
ns
DS90C241/DS90C124
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4
Deserializer Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max Units
t
DD
Deserializer Delay
(Figure 10)
RCLK
[4+(3/56)]T+
5.9
ns
5 MHz
817
825
ns
35 MHz
122
125
ns
t
DRDL
Deserializer PLL Lock Time
from Powerdown
(Notes 7, 8)
5 MHz
5
12
ms
35 MHz
5
10
ms
RxIN_TOL_L
Receiver INput TOLerance
Left, (Figure 15)
(Notes 6, 10)
5 MHz35 MHz
0.25
UI
RxIN_TOL_R
Receiver INput TOLerance
Right, (Figure 15)
(Notes 6, 10)
5 MHz35 MHz
0.25
UI
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of "Electrical Characteristics" specifies conditions of device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD,
VOD,
VTH and VTL which are differential voltages.
Note 4: When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: t
DRDL
is the time required by the deserializer to obtain lock when exiting powerdown mode. t
DRDL
is specified with an external synchronization pattern.
Note 6: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National's AN-1217 for detail.
Note 7: The Deserializer PLL lock time may vary depending on input data patterns and the number of transitions within the pattern.
Note 8: Guaranteed by Design (GBD) using statistical analysis.
Note 9: Total Interconnect Jitter Budget (t
JI
) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are Auto SerDes circuits.
Note 10: UI Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 11: Figures 1, 2, 9, 10, 13 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 12: Figures 6, 11 show a rising edge data strobe (TCLK IN/RCLK OUT).
DS90C241/DS90C124
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5
AC Timing Diagrams and Test Circuits
20171902
FIGURE 1. Serializer Input Checker-board Pattern
20171903
FIGURE 2. Deserializer Output Checker-board Pattern
20171904
FIGURE 3. Serializer LVDS Output Load and Transition Times
20171905
FIGURE 4. Deserializer LVCMOS/LVTTL Output Load and Transition Times
DS90C241/DS90C124
www.national.com
6
AC Timing Diagrams and Test Circuits
(Continued)
20171906
FIGURE 5. Serializer Input Clock Transition Times
20171907
FIGURE 6. Serializer Setup/Hold Times
DS90C241/DS90C124
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7
AC Timing Diagrams and Test Circuits
(Continued)
20171908
FIGURE 7. Serializer TRI-STATE Test Circuit and Delay
20171909
FIGURE 8. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
DS90C241/DS90C124
www.national.com
8
AC Timing Diagrams and Test Circuits
(Continued)
20171910
FIGURE 9. Serializer Delay
20171911
FIGURE 10. Deserializer Delay
DS90C241/DS90C124
www.national.com
9
AC Timing Diagrams and Test Circuits
(Continued)
20171912
FIGURE 11. Deserializer Setup and Hold Times
20171913
Note: C
L
includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0]
FIGURE 12. Deserializer TRI-STATE Test Circuit and Timing
DS90C241/DS90C124
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10
AC Timing Diagrams and Test Circuits
(Continued)
20171914
FIGURE 13. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay
20171915
FIGURE 14. Transmitter Output Eye Opening
20171916
FIGURE 15. Receiver Input Tolerance (RxIN_TOL) and Sampling Window
DS90C241/DS90C124
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11
AC Timing Diagrams and Test Circuits
(Continued)
20171917
VOD = (D
OUT+
) (D
OUT -
)
Differential output signal is shown as (D
OUT+
) (D
OUT -
), device in Data Transfer mode.
FIGURE 16. Serializer VOD Diagram
20171918
FIGURE 17. AC Coupled Application
DS90C241/DS90C124
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12
Pin Descriptions
Pin #
Pin Name
I/O
Description
DS90C241 SERIALIZER PIN DESCRIPTIONS
22
VDDDR
VDD
Analog Voltage Supply, LVDS O/P Power
21
VSSDR
GND
Analog Ground, LVDS O/P Ground
16
VDDPT0
VDD
Analog Voltage supply, VCO Power
17
VSSPT0
GND
Analog ground, VCO Ground
14
VDDPT1
VDD
Analog Voltage supply, PLL Power
15
VSSPT1
GND
Analog Ground, PLL Ground
30
VDDT
VDD
Digital Voltage supply, Tx serializer Power
31
VSST
GND
Digital Ground, Tx serializer Ground
7
VDDL
VDD
Digital Voltage supply, Tx Logic Power
6
VSSL
GND
Digital Ground, Tx Logic Ground
42
VDDIT
VDD
Digital Voltage supply, Tx Input Power
43
VSSIT
GND
Digital Ground, Tx Input Ground
24
VSSESD
GND
ESD Ground
4-1,
48-44,
41-32,
29-25
DIN[23:0]
CMOS_I
Transmitter Data INputs
10
TCLK
CMOS_I
Transmitter reference CLocK.
Used to strobe data at the DIN inputs and to drive the transmitter PLL
9
TPWDNB
CMOS_I
Transmitter PoWer DowN Bar (ACTIVE L).
TPWDNB = L; Disabled, DOUT (+/-) are TRI-STATED stand-by mode, PLL is shutdown
TPWDNB = H; Enabled
18
DEN
CMOS_I
Data ENable (ACTIVE H)
DEN = L; Disabled, DOUT (+/-) are TRI-STATED, PLL still operational
DEN = H; Enabled
13
RESRVD
CMOS_I
RESERVED - tie Low
23
PRE
CMOS_I
PRE-emphasis select pin.
PRE = (R
PRE
3 k); I
max
= (1.2/R*20), R
min
= 3 k
PRE = H or floating; pre-emphasis off
11
TRFB
CMOS_I
Transmitter Rising/Falling Bar Clock Edge Select (H = rising edge L = falling edge)
12
VODSEL
CMOS_I
VOD level SELect
VODSEL = L; IOD
3.5 mA, (default). e.g. 3.5 mA*100350 mV
VODSEL = H; IOD
7.0 mA, VOD doubles approximately. e.g. 7 mA*100 700 mV
5
DCAOFF
CMOS_I
RESERVED -- tie Low
8
DCBOFF
CMOS_I
RESERVED -- tie Low
20
DOUT+
LVDS_O
Transmitter LVDS true (+) OUTput
19
DOUT-
LVDS_O
Transmitter LVDS inverted (-) OUTput
DS90C124 DESERIALIZER PIN DESCRIPTIONS
39
VDDIR
VDD
Analog LVDS Voltage supply, Power
40
VSSIR
GND
Analog LVDS Ground
47
VDDPR0
VDD
Analog Voltage supply, PLL Power
46
VSSPR0
GND
Analog Ground, PLL Ground
45
VDDPR1
VDD
Analog Voltage supply, PLL VCO Power
44
VSSPR1
GND
Analog Ground, PLL VCO Ground
37
VDDR1
VDD
Digital Voltage supply, Logic Power
38
VSSR1
GND
Digital Ground, Logic Ground
36
VDDR0
VDD
Digital Voltage supply, Logic Power
35
VSSR0
GND
Digital Ground, Logic Ground
30
VDDOR1
VDD
Digital Voltage supply, LVTTL O/P Power
DS90C241/DS90C124
www.national.com
13
Pin Descriptions
(Continued)
Pin #
Pin Name
I/O
Description
DS90C124 DESERIALIZER PIN DESCRIPTIONS
29
VSSOR1
GND
Digital Ground, LVTTL O/P Ground
20
VDDOR2
VDD
Digital Voltage supply, LVTTL O/P Power
19
VSSOR2
GND
Digital Ground, LVTTL O/P Ground
7
VDDOR3
VDD
Digital Voltage supply, LVTTL O/P Power
8
VSSOR3
GND
Digital Ground, LVTTL O/P Ground
41
RIN+
LVDS_I
Receiver LVDS true (+) INput
42
RIN-
LVDS_I
Receiver LVDS inverted (-) INput
2
RESRVD
CMOS_I
RESERVED - tie Low
43
RRFB
CMOS_I
Receiver Rising Falling Bar clock Edge Select
RRFB = H; ROUT LVTTL O/P clocked on Rising CLK
RRFB = L; ROUT LVTTL O/P clocked on Falling CLK
48
REN
CMOS_I
Receiver ENable, (ACTIVE H)
REN = L; Disabled, ROUT[23-0] and RCLK TRI-STATED, PLL still operational
REN = H; Enabled
1
RPWDNB
CMOS_I
Receiver PoWer DowN Bar (ACTIVE L)
RPWDNB = L; Disabled, ROUT[23-0], RCLK, and LOCK are TRI-STATED in stand-by
mode, PLL is shutdown
RPWDNB = H; Enabled
17
LOCK
CMOS_O
LOCK indicates the status of the receiver PLL
LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED
LOCK = H; receiver PLL is locked
25-28,
31-34
ROUT[7:0]
CMOS_O
Receiver Outputs Group 1
13-16,
21-24
ROUT[15:8]
CMOS_O
Receiver Outputs Group 2
3-6,
9-12
ROUT[23:16]
CMOS_O
Receiver Outputs Group 3
18
RCLK
CMOS_O
Recovered CLocK. Parallel data rate clock recovered from the embedded clock.
DS90C241/DS90C124
www.national.com
14
Pin Diagrams
Serializer - DS90C241
20171919
DS90C241/DS90C124
www.national.com
15
Pin Diagrams
(Continued)
Deserializer - DS90C124
20171920
DS90C241/DS90C124
www.national.com
16
Physical Dimensions
inches (millimeters) unless otherwise noted
Dimensions show in millimeters only
Order Number DS90C241IVS, DS90C124IVS
NS Package Number IVS48
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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DS90C241/DS90C124
5-35MHz
DC-Balanced
24-Bit
L
VDS
Serializer
and
Deserializer
PDF 
ZIP