DS90CR286A/DS90CR216A
+3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit
Channel Link--66 MHz,
+3.3V Rising Edge Strobe
LVDS Receiver 21-Bit Channel Link--66 MHz
General Description
The DS90CR286A receiver converts the four LVDS data
streams (Up to 1.848 Gbps throughput or 231 Megabytes/
sec bandwidth) back into parallel 28 bits of CMOS/TTL data.
Also available is the DS90CR216A that converts the three
LVDS data streams (Up to 1.386 Gbps throughput or 173
Megabytes/sec bandwidth) back into parallel 21 bits of
CMOS/TTL data. Both Receivers' outputs are Rising edge
strobe.
Both devices are offered in TSSOP packages. In addition the
DS90CR286A is also offered in a space saving 64 ball,
0.8mm fine pitch ball grid array (FBGA) which provides a
44% reduction in PCB footprint compared to the 56L TSSOP
package.
The DS90CR286A / DS90CR216A devices are enhanced
over prior generation receivers and provided a wider data
valid time on the receiver output.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n
20 to 66 MHz shift clock support
n
50% duty cycle on receiver output clock
n
BestinClass Set & Hold Times on RxOUTPUTs
n
Rx power consumption
<
270 mW (typ)
@
66MHz Worst
Case
n
Rx Power-down mode
<
200W (max)
n
ESD rating
>
7 kV (HBM),
>
700V (EIAJ)
n
PLL requires no external components
n
Compatible with TIA/EIA-644 LVDS standard
n
Low profile 56-lead or 48-lead TSSOP package
n
DS90CR286A is also offered in a space saving 64 ball
FBGA package
n
Operating Temperature: -40C to +85C
Block Diagrams
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS90CR286A
DS100873-30
Order Number DS90CR286AMTD or DS90CR286ASLC
See NS Package Number MTD56 or SLC64A
DS90CR216A
DS100873-31
Order Number DS90CR216AMTD
See NS Package Number MTD48
May 2000
DS90CR286A/DS90CR216A
+3.3V
Rising
Edge
Data
Strobe
L
VDS
Receiver
28-Bit
Channel
Link
--
6
6
MHz,
+3.3V
Rising
Edge
Data
Strobe
L
VDS
Receiver
21-Bit
Channel
Link
--
6
6
MHz
2000 National Semiconductor Corporation
DS100873
www.national.com
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.3V to +4V
CMOS/TTL Output Voltage
-0.3V to (V
CC
+ 0.3V)
LVDS Receiver Input Voltage
-0.3V to (V
CC
+ 0.3V)
Junction Temperature
+150C
Storage Temperature
-65C to +150C
Lead Temperature
(Soldering, 4 sec)
+260C
Solder Reflow Temperature
(20 sec for FBGA)
+220C
Maximum Package Power Dissipation Capacity
@
25C
MTD56 (TSSOP) Package:
DS90CR286AMTD
1.61 W
MTD48 (TSSOP) Package:
DS90CR216AMTD
1.89 W
SLC64A Package:
DS90CR286ASLC
2.0W
Package Derating:
DS90CR286AMTD
12.4 mW/C above +25C
DS90CR216AMTD
15 mW/C above +25C
DS90CR286ASLC
10.2 mW/C above +25C
ESD Rating
(HBM, 1.5 k
, 100 pF)
>
7 kV
(EIAJ, 0
, 200 pF)
>
700V
Recommended Operating
Conditions
Min
Nom
Max
Units
Supply Voltage (V
CC
)
3.0
3.3
3.6
V
Operating Free Air
Temperature (T
A
)
-40
+25
+85
C
Receiver Input Range
0
2.4
V
Supply Noise Voltage (V
CC
)
100
mV
PP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CMOS/TTL DC SPECIFICATIONS (For PowerDown Pin)
V
IH
High Level Input Voltage
2.0
V
CC
V
V
IL
Low Level Input Voltage
GND
0.8
V
V
CL
Input Clamp Voltage
I
CL
= -18 mA
-0.79
-1.5
V
I
IN
Input Current
V
IN
= 0.4V, 2.5V or V
CC
+1.8
+10
A
V
IN
= GND
-10
0
A
CMOS/TTL DC SPECIFICATIONS
V
OH
High Level Output Voltage
I
OH
= -0.4 mA
2.7
3.3
V
V
OL
Low Level Output Voltage
I
OL
= 2 mA
0.06
0.3
V
I
OS
Output Short Circuit Current
V
OUT
= 0V
-60
-120
mA
LVDS RECEIVER DC SPECIFICATIONS
V
TH
Differential Input High Threshold
V
CM
= +1.2V
+100
mV
V
TL
Differential Input Low Threshold
-100
mV
I
IN
Input Current
V
IN
= +2.4V, V
CC
= 3.6V
10
A
V
IN
= 0V, V
CC
= 3.6V
10
A
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current Worst Case
C
L
= 8 pF, Worst
Case Pattern,
DS90CR286A
(Figures
1, 2 ), T
A
=-10C to
+70C
f = 33 MHz
49
65
mA
f = 37.5 MHz
53
70
mA
f = 66 MHz
81
105
mA
ICCRW
Receiver Supply Current Worst Case
C
L
= 8 pF, Worst
Case Pattern,
DS90CR286A
(Figures
1, 2 ), T
A
=-40C to
+85C
f = 40 MHz
53
70
mA
f = 66 MHz
81
105
mA
ICCRW
Receiver Supply Current Worst Case
C
L
= 8 pF, Worst
Case Pattern,
DS90CR216A
(Figures
1, 2 ), T
A
=-10C to
+70C
f = 33 MHz
49
55
mA
f = 37.5 MHz
53
60
mA
f = 66 MHz
78
90
mA
DS90CR286A/DS90CR216A
www.national.com
2
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
RECEIVER SUPPLY CURRENT
ICCRW
Receiver Supply Current Worst Case
C
L
= 8 pF, Worst
Case Pattern,
DS90CR216A
(Figures
1, 2 ), T
A
=-40C to
+85C
f = 40 MHz
53
60
mA
f = 66 MHz
78
90
mA
ICCRZ
Receiver Supply Current
Power Down = Low
10
55
A
Power Down
Receiver Outputs Stay Low during
Power Down Mode
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of "Electrical Characteristics" specify conditions for device operation.
Note 2: Typical values are given for V
CC
= 3.3V and T
A
= +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
OD
and
V
OD
).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time
(Figure 2 )
2
5
ns
CHLT
CMOS/TTL High-to-Low Transition Time
(Figure 2 )
1.8
5
ns
RSPos0
Receiver Input Strobe Position for Bit 0
(Figure 9,
Figure 10)
f = 40 MHz
1.0
1.4
2.15
ns
RSPos1
Receiver Input Strobe Position for Bit 1
4.5
5.0
5.8
ns
RSPos2
Receiver Input Strobe Position for Bit 2
8.1
8.5
9.15
ns
RSPos3
Receiver Input Strobe Position for Bit 3
11.6
11.9
12.6
ns
RSPos4
Receiver Input Strobe Position for Bit 4
15.1
15.6
16.3
ns
RSPos5
Receiver Input Strobe Position for Bit 5
18.8
19.2
19.9
ns
RSPos6
Receiver Input Strobe Position for Bit 6
22.5
22.9
23.6
ns
RSPos0
Receiver Input Strobe Position for Bit 0
(Figure 9,
Figure 10)
f = 66 MHz
0.7
1.1
1.4
ns
RSPos1
Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2
Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3
Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4
Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5
Receiver Input Strobe Position for Bit 5
11.7
12.1
12.4
ns
RSPos6
Receiver Input Strobe Position for Bit 6
13.9
14.3
14.6
ns
RSKM
RxIN Skew Margin (Note 4)
(Figure 11 )
f = 40 MHz
490
ps
f = 66 MHz
400
ps
RCOP
RxCLK OUT Period
(Figure 3)
15
T
50
ns
RCOH
RxCLK OUT High Time
(Figure 3 )
f = 40 MHz
10.0
12.2
ns
RCOL
RxCLK OUT Low Time
(Figure 3)
10.0
11.0
ns
RSRC
RxOUT Setup to RxCLK OUT
(Figure 3 )
6.5
11.6
ns
RHRC
RxOUT Hold to RxCLK OUT
(Figure 3 )
6.0
11.6
ns
RCOH
RxCLK OUT High Time
(Figure 3 )
f = 66 MHz
5.0
7.6
ns
RCOL
RxCLK OUT Low Time
(Figure 3)
5.0
6.3
ns
RSRC
RxOUT Setup to RxCLK OUT
(Figure 3 )
4.5
7.3
ns
RHRC
RxOUT Hold to RxCLK OUT
(Figure 3 )
4.0
6.3
ns
RCCD
RxCLK IN to RxCLK OUT Delay 25C, V
CC
= 3.3V (Note 5)
(Figure 4 )
3.5
5.0
7.5
ns
RPLLS
Receiver Phase Lock Loop Set
(Figure 5 )
10
ms
RPDD
Receiver Power Down Delay
(Figure 8 )
1
s
DS90CR286A/DS90CR216A
www.national.com
3
Receiver Switching Characteristics
(Continued)
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-
ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2
*
T + RCCD), where T = Clock period.
AC Timing Diagrams
DS100873-2
FIGURE 1. "Worst Case" Test Pattern
DS100873-4
FIGURE 2. DS90CR286A/DS90CR216A (Receiver) CMOS/TTL Output Load and Transition Times
DS100873-5
FIGURE 3. DS90CR286A/DS90CR216A (Receiver) Setup/Hold and High/Low Times
DS100873-6
FIGURE 4. DS90CR286A/DS90CR216A (Receiver) Clock In to Clock Out Delay
DS90CR286A/DS90CR216A
www.national.com
4
AC Timing Diagrams
(Continued)
DS100873-7
FIGURE 5. DS90CR286A/DS90CR216A (Receiver) Phase Lock Loop Set Time
DS100873-9
FIGURE 6. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR286A
DS100873-10
FIGURE 7. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CR216A
DS90CR286A/DS90CR216A
www.national.com
5
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