TL H 9660
LF451
Wide-Bandwidth
JFET-Input
Operational
Amplifier
December 1995
LF451 Wide-Bandwidth
JFET-Input Operational Amplifier
General Description
The LF451 is a low-cost high-speed JFET-input operational
amplifier with an internally trimmed input offset voltage (BI-
FET II
TM
technology) The device requires a low supply cur-
rent and yet maintains a large gain bandwidth product and a
fast slew rate In addition well matched high voltage JFET
input devices provide very low input bias and offset cur-
rents The LF451 is pin compatible with the standard
LM741 allowing designers to upgrade the overall perform-
ance of existing designs
The LF451 may be used in such applications as high-speed
integrators fast D A converters sample-and-hold circuits
and many other circuits requiring low input bias current high
input impedance high slew rate and wide bandwidth
Features
Y
Internally trimmed offset voltage
5 0 mV (max)
Y
Low input bias current
50 pA (typ)
Y
Low input noise current
0 01 pA
0
Hz (typ)
Y
Wide gain bandwidth
4 MHz (typ)
Y
High slew rate
13 V ms (typ)
Y
Low supply current
3 4 mA (max)
Y
High input impedance
10
12
X
(typ)
Y
Low total harmonic distortion A
V
e
10
k
0 02% (typ)
R
L
e
10k V
O
e
20 V
p p
f
e
20 Hz 20 kHz
Y
Low 1 f noise corner
50 Hz (typ)
Y
Fast settling time to 0 01%
2 ms (typ)
Connection Diagram
S O Package
TL H 9660 2
Top View
Order Number LF451CM
See NS Package Number M08A
Typical Connection
TL H 9660 1
Simplified Schematic
TL H 9660 3
BI-FET
TM
is a trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M125 Printed in U S A
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Supply Voltage (V
a
b
V
b
)
36V
Input Voltage Range
V
b s
V
IN
s
V
a
Differential Input Voltage (Note 2)
g
30V
Junction Temperature (T
J
MAX)
150 C
Output Short Circuit Duration
Continuous
Power Dissipation (Note 3)
500 mW
ESD Tolerance
TBD
Soldering Information (Note 5)
SO Package Vapor Phase (60 sec)
215 C
Infrared (15 sec)
220 C
Operating Ratings
(Note 1)
Temperature Range
T
MIN
s
T
A
s
T
MAX
LF451CM
0 C
s
T
A
s
a
70 C
Junction Temperature (T
J max
)
125 C
Supply Voltage (V
a
b
V
b
)
10V to 32V
DC Electrical Characteristics
The following specifications apply for V
a
e a
15V and V
b
e b
15V Bold-
face limits apply for T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
LF451CM
Symbol
Parameter
Conditions
Typical
Tested
Design
Units
(Note 6)
Limit
Limit
(Note 7)
(Note 8)
V
OS
Maximum Input Offset Voltage
R
S
e
10 kX (Note 10)
0 3
5
mV
I
OS
Maximum Input Offset Current
(Notes 9 10)
T
J
e
25 C
25
100
pA
T
J
e
70 C
2
nA
I
B
Maximum Input Bias Current
(Notes 9 10)
T
J
e
25 C
50
200
pA
T
J
e
70 C
4
nA
R
IN
Input Resistance
T
J
e
25 C
10
12
X
AVOL
Minimum Large Signal
V
O
e
g
10V R
L
e
2 kX
200
50
25
V mV
Voltage Gain
(Note 10)
V
O
Minimum Output Voltage Swing
R
L
e
10k
g
13 5
g
12
g
12
V
V
CM
Minimum Input Common Mode
a
14 5
a
11
a
11
V
Voltage Range
b
11 5
b
11
b
11
V
CMRR
Minimum Common-Mode
R
S
s
10 kX
100
80
80
dB
Rejection Ratio
PSRR
Minimum Supply Voltage
(Note 11)
100
80
80
dB
Rejection Ratio
I
S
Maximum Supply Current
3 4
3 4
mA
AC Electrical Characteristics
The following specifications apply for V
a
e a
15V and V
b
e b
15V Bold-
face limits apply for T
MIN
to T
MAX
all other limits T
A
e
T
J
e
25 C
LF451CM
Symbol
Parameter
Conditions
Typical
Tested
Design
Units
(Note 6)
Limit
Limit
(Note 7)
(Note 8)
SR
Slew Rate
A
V
e a
1
13
8
V ms
GBW
Minimum Gain-Bandwidth Product
f
e
100 kHz
4
2 7
MHz
e
n
Equivalent Input Noise Voltage
R
S
e
100X f
e
1 kHz
25
nV
0
Hz
i
n
Equivalent Input Noise Current
R
S
e
100X f
e
1 kHz
0 01
pA
0
Hz
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating
the device beyond its specified operating ratings
Note 2
When the input voltage exceeds the power supplies the current should be limited to 1 mA
Note 3
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
J
MAX i
JA
and the ambient temperature T
A
The maximum
allowable power dissipation at any temperature is P
D
e
(T
J
MAX
b
T
A
) i
JA
or the number given in the Absolute Maximum Ratings whichever is lower For
guaranteed operation T
J max
e
125 C The typical thermal resistance (i
JA
) of the LF451CM when board-mounted is 170 C W
Note 5
See AN-450 ``Surface Mounting Methods and Their Effect on Product Reliability'' (Appendix D) for other methods of soldering surface mount devices
Note 6
Typicals are at T
J
e
25 C and represent most likely parametric norm
2
Note 7
Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level)
Note 8
Design limits are guaranteed to National's AOQL but not 100% tested
Note 9
The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature T
J
Due to limited
production test time the input bias currents are correlated to junction temperature In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation P
D
T
J
e
T
A
a
i
JA
P
D
where i
JA
is the thermal resistance from junction to ambient
Note 10
V
OS
I
B
AVOL and I
OS
are measured at V
CM
e
0V
Note 11
Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice
Typical Performance Characteristics
Distortion vs Frequency
Voltage Swing
Undistorted Output
Response
Open Loop Frequency
Rejection Ratio
Common-Mode
Rejection Ratio
Power Supply
Noise Voltage
Equivalent Input
Gain (V V)
Open Loop Voltage
Output Impedance
Inverter Settling Time
TL H 9660 5
3
Pulse Response
Small Signal Inverting
TL H 9660 6
Small Signal Non-Inverting
TL H 9660 7
Large Signal Inverting
TL H 9660 8
Large Signal Non-Inverting
TL H 9660 9
Current Limit (R
L
e
100X)
TL H 9660 10
Application Hints
The LF451CM is an op amp with an internally trimmed input
offset voltage and JFET input devices (BI-FET II) These
JFETs have large reverse breakdown voltages from gate to
source and drain eliminating the need for clamps across the
inputs Therefore large differential input voltages can easily
be accommodated without a large increase in input current
The maximum differential input voltage is independent of
the supply voltages However neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit
Exceeding the negative common-mode limit with the non-in-
verting input or with both inputs will force the output to a
high state potentially causing a reversal of phase to the
output
In neither case does a latch occur since raising the input
back within the common-mode range again puts the input
stage and thus the amplifier in a normal operating mode
5
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