LM2502
Mobile Pixel Link (MPL) Display Interface Serializer and
Deserializer
General Description
The LM2502 device is a dual link display interface SERDES
that adapts existing CPU / video busses to a low power
current-mode serial MPL link. The chipset may also be used
for a RGB565 application with glue logic. The interconnect is
reduced from 22 signals to only 3 active signals with the
LM2502 chipset easing flex interconnect design, size and
cost.
The Master Serializer (SER) resides beside an application
processor or baseband processor and translates a parallel
bus from LVCMOS levels to serial MPL levels for transmis-
sion over a flex cable and PCB traces to the Slave Deseri-
alizer (DES) located near the display module.
Dual display support is provided for a primary and sub
display through the use of two ChipSelect signals. A Mode
pin selects either a i80 or m68 style interface.
The Power_Down (PD*) input controls the power state of the
MPL interface. When PD* is asserted, the MD1/0 and MC
signals are powered down to save current.
The LM2502 implements the physical layer of the MPL Stan-
dard (MPL-0). The LM2502 is offered in NOPB (Lead-free)
UFBGA and LLP packages.
Features
n
>
300 Mbps Dual Link Raw Throughput
n
MPL Physical Layer (MPL-0)
n
Pin selectable Master / Slave mode
n
Frequency Reference Transport
n
Complete LVCMOS / MPL Translation
n
Interface Modes:
-- 16-bit CPU, i80 or m68 style
-- RGB565 with glue logic
n
-30C to 85C Operating Range
n
Link power down mode reduces I
DDZ
<
10 A
n
Dual Display Support (CS1* & CS2*)
n
Via-less MPL interconnect feature
n
3.0V Supply Voltage (V
DD
and V
DDA
)
n
Interfaces to 1.7V to 3.3V Logic (V
DDIO
)
System Benefits
n
Small Interface
n
Low Power
n
Low EMI
n
Frequency Reference Transport
n
Intrinsic Level Translation
Typical Application Diagram
20093301
Ordering Information
NSID
Package Type
Package ID
LM2502SM
49 Lead UFBGA style, 4.0 X 4.0 X 1.0 mm, 0.5 mm pitch
1000 std reel, LM2502SMX 4500 reel
SLH49A
LM2502SQ
40 Lead LLP style, 5.0 X 5.0 X 0.8 mm, 0.4 mm pitch
1000 std reel, LM2502SQX 4500 reel
SQF40A
August 2005
LM2502
Mobile
Pixel
Link
(MPL)
Display
Interface
Serializer
and
Deserializer
2005 National Semiconductor Corporation
DS200933
www.national.com
Pin Descriptions
Pin Name
No.
of Pins
I/O, Type
Description
Master (SER)
Slave (DES)
MPL SERIAL BUS PINS
MD[1:0]
2
IO, MPL
MPL Data Line Driver/Receiver
MPL Data Receiver/Line Driver
MC
1
IO, MPL
MPL Clock Line Driver
MPL Clock Receiver
V
SSA
Ground
MPL Ground - see Power/Ground Pins
MPL Ground - see Power/Ground Pins
CONFIGURATION/PARALLEL BUS PINS
M/S*
1
I,
LVCMOS
Master/Slave* Input,
M/S* = H for Master
Master/Slave* Input
M/S* = L for Slave
PD*
1
I,
LVCMOS
Power_Down* Input,
H = Active
L = Power Down Mode
Power_Down* Input,
H = Active
L = Power Down Mode
MF0
(E or RD*)
1
IO,
LVCMOS
Multi-function Input Zero (0):
If MODE = L (m68 mode), E input pin,
data is latched on E High-to-Low
transition or E may be static High and
Data is latched on CS* Low-to-High edge
If MODE = H (i80 mode), Read Enable
input pin, active low. Read data is driven
when both RD* and CS* are Low.
Multi-function Output Zero (0):
If MODE = L (m68 mode),
E output pin, static High.
If MODE = H (i80 mode),
Read Enable output pin, active Low.
MF1
(R/W* or
WR*)
1
IO,
LVCMOS
Multi-function Input One (1):
If Mode = L (m68 mode), Read/Write*
pin, Read High, Write* Low
If Mode = H (i80 mode), Write* enable
input pin, active Low. Write data is
latched on the Low-to-High transition of
either WR* or CS* (which ever occurs
first).
Multi-function Output One (1):
If Mode = L (m68 mode)
Read/Write* pin,
Read High, Write* Low
If Mode = H (i80 mode)
Write* enable output pin, active Low.
CS1*
1
IO,
LVCMOS
ChipSelect1* Input
H = Ignored
L = Active
ChipSelect1* Output
H = Ignored
L = Active
CS2*
1
IO,
LVCMOS
ChipSelect2* Input
H = Ignored
L = Active
ChipSelect2* Output
H = Ignored
L = Active
A/D (RS or
A0)
1
IO,
LVCMOS
Address/Data Input
H = Data
L = Address (Command)
Address/Data Output
H = Data
L = Address (Command)
D[15:0]
16
IO,
LVCMOS
Data Bus Inputs/Outputs
Data Bus Outputs/Inputs
INTR
or
CLKDIS*
1
O or I,
LVCMOS
INTR is asserted when the read data is
ready and de-asserted upon a second
CPU Read cycle.
Clock Disable - CLKDIS*:
H = CLK output ON
L = CLK output LOW, allows for the
Slave clock output to be held static if not
used.
CLK
1
IO,
LVCMOS
Clock Input
Clock Output (Frequency Reference)
no phase relationship to data frequency
reference only.
Mode
1
I,
LVCMOS
Mode Input Pin
H = i80 Mode,
L = m68 Mode
Mode Input Pin
H = i80 Mode,
L = m68 Mode
PLL_CON
[2:0]
3
I,
LVCMOS
PLL Configuration Input Pins see Table
10
Clock Divisor Configuration Input Pins
see Table 10
LM2502
www.national.com
4
Pin Descriptions
(Continued)
Pin Name
No.
of Pins
I/O, Type
Description
Master (SER)
Slave (DES)
POWER/GROUND PINS
V
DDA
1
Power
Power Supply Pin for the MPL Interface. 2.9V to 3.3V
V
SSA
1
Ground
Ground Pin for the MPL Interface, a low impedance ground path is required between
the Master and the Slave device - see Applications Information section.
V
DDcore
1
Power
Power Supply Pin for the digital core. 2.9V to 3.3V
V
SScore
1
Ground
Ground Pin for the digital core.
V
DDIO
2
Power
Power Supply Pin for the parallel interface. 1.7V to 3.3V
V
SSIO
2
Ground
Ground Pin for the parallel interface.
9
NC
Not Connected (C3-5, D3-5, E3-5). UFBGA Package only.
1
Ground
DAP = Ground. LLP Package only.
Note:
I = Input, O = Output, IO = Input/Output, V
DDIO
V
DD
(V
DDA
= V
DDcore
). Do not float input pins.
Master Pinout - UFBGA Package
MST
1
2
3
4
5
6
7
A
D0
D1
D2
V
DDA
INTR
MD1
MC
B
D3
D4
D5
V
SSA
M/S*
Mode
MD0
C
D6
D7
NC
NC
NC
CS2*
MF1
D
V
DDIO
V
SSIO
NC
NC
NC
V
SScore
V
DDcore
E
D8
D9
NC
NC
NC
CS1*
PLLCON2
F
D10
D11
D12
V
SSIO
MF0
PLLCON1
PD*
G
D13
D14
D15
V
DDIO
A/D
PLLCON0
CLK
Slave Pinout - UFBGA Package
SLV
1
2
3
4
5
6
7
A
D0
D1
D2
V
DDA
CLKDIS*
MD0
MC
B
D3
D4
D5
V
SSA
M/S*
Mode
MD1
C
D6
D7
NC
NC
NC
CS2*
MF1
D
V
DDIO
V
SSIO
NC
NC
NC
V
SScore
V
DDcore
E
D8
D9
NC
NC
NC
CS1*
PLLCON2
F
D10
D11
D12
V
SSIO
MF0
PLLCON1
PD*
G
D13
D14
D15
V
DDIO
A/D
PLLCON0
CLK
LM2502
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