LM2650
Synchronous Step-Down DC/DC Converter
General Description
The LM2650 is a step-down DC/DC converter featuring high
efficiency over a 3A to milliamperes load range. This feature
makes the LM2650 an ideal fit in battery-powered applica-
tions that demand long battery life in both run and standby
modes.
The LM2650 also features a logic-controlled shutdown mode
in which it draws at most 25A from the input power supply.
The LM2650 employs a fixed-frequency pulse-width modu-
lation (PWM) and synchronous rectification to achieve very
high efficiencies. In many applications, efficiencies reach
95%+ for loads around 1A and exceed 90% for moderate to
heavy loads from 0.2A to 2A.
A low-power hysteretic or
sleep
mode keeps efficiencies
high at light loads. The LM2650 enters and exits sleep mode
automatically as the load crosses
sleep in
and
sleep out
thresholds. The LM2650 provides nodes for programming
both thresholds via external resistors. A logic input allows the
user to override the automatic sleep feature and keep the
LM2650 in PWM mode regardless of the load level.
An optional soft-start feature limits current surges from the
input power supply at start up and provides a simple means
of sequencing multiple power supplies.
Features
n
Ultra high efficiencies (95% possible)
n
High efficiency over a 3A to milliamperes load range
n
Synchronous switching of internal NMOS power FETs
n
Wide input voltage range (4.5V to 18V)
n
Output voltage adjustable from 1.5V to 16V
n
Automatic low-power sleep mode
n
Logic-controlled micropower shutdown (I
QSD
25 A)
n
Frequency adjustable up to 300 kHz
n
Frequency synchronization with external signal
n
Programmable soft-start
n
Short-circuit current limiting
n
Thermal shutdown
n
Available in 24-lead Small-Outline package
Applications
n
Notebook and palmtop personal computers
n
Portable data terminals
n
Modems
n
Portable Instruments
n
Global positioning devices (GPSs)
n
Battery-powered digital devices
Typical Application
DS012848-1
Converting a Four-Cell Li Ion Battery to 5V
LM2650-ADJ Efficiency
DS012848-2
November 2000
LM2650
Synchronous
Step-Down
DC/DC
Converter
2000 National Semiconductor Corporation
DS012848
www.national.com
Connection Diagram
Pin Descriptions
(Refer to the Block Diagrams)
Pins
Description
1, 12
SUB: These pins make electrical contact with the substrate of the die. Ground them. For best thermal
performance, ground them to the same large, uninterrupted copper plane as the PGND pins.
2
SLEEP LOGIC: Use this logic input to select the conversion mode; low selects PWM, high selects sleep, and
high impedance (open) permits the LM2650 to move freely and automatically between the modes, using PWM
for moderate to heavy loads and sleep for light loads.
3, 4, 9, 10
PGND: The ground return of the power stage. The power stage consists of the two power switches Q1 and
Q2, the gate drivers DH and DL, and the linear voltage regulators VRegH and VRegL. For best electrical and
thermal performance, ground these pins to a large, uninterrupted copper plane.
5, 8
SW: The output node of the power stage. It swings from slightly below ground to slightly below the voltage to
PV
IN
. To minimize the effects of switching noise on nearby circuitry, keep all traces originating from SW short
and to the point. Route all traces carrying signals well away from the SW traces.
6, 7
PV
IN
: The positive supply rail of the power stage. Bypass each PV
IN
pin to PGND with a 0.1 F capacitor. Use
capacitors having low ESL and low ESR, and locate them close to the IC.
11
BOOT: The positive supply rail of the high-side gate driver DH. Connect a 0.1 F capacitor from this node to
SW. Bootstrapping action creates a supply rail about 9V above that at PV
IN
, and DH uses this rail to override
the gate of the NMOS power FET Q1. Overriding ensures low R
DS(on)
.
13
FB: The feedback input.
14
V
DD
: An internal regulator steps the input voltage down to a 4V rail used by the signal-level circuitry. V
DD
is the
output node of this regulator. Bypass V
DD
to GND close to the IC with a 0.2 F capacitor.
15
COMP: The inverting input of the error amplifier EA.
16
EA OUT: The output node of the error amplifier EA.
17
SS: The soft start node. Connect a capacitor from SS to GND.
18
GND: The ground return of the signal-level circuitry.
19
V
IN
: The positive supply rail of the internal 4V regulator. Bypass V
IN
to GND close to the IC with a 0.1 F
capacitor.
20
FREQ ADJ: The LM2650 switches at a nominal 90 kHz. Connect a resistor between FREQ ADJ and GND to
adjust the frequency up from the nominal. Use the graph under Typical performance Characteristics to select
the resistor.
21
SYNC: The synchronization input. If the switching frequency is to be synchronized with an external clock
signal, apply the clock signal here. Ground if not used.
22
SD: Use this logic input to control shutdown; pull low for operation, high for shutdown.
23
SLEEP OUT ADJ (SOA): The value of the resistor connected between SIA and ground programs the sleep-in
threshold. Higher values program lower thresholds.
24
SLEEP IN ADJ (SIA): The value of the resistor connected between SIA and ground programs the sleep-in
threshold. Higher values program lower thresholds.
DS012848-14
Top View
24-Lead Small Outline Package (M)
Order Number LM2650M-ADJ
See Package Number M24B
LM2650
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(All voltages are referenced to the PGND and GND pins.)
DC Voltage at PV
IN
and V
IN
20V
DC Voltage at SD, SLEEP LOGIC
and SYNC
15V
DC current into SW
7.5A
Junction Temperature
Limited by the IC
DC Power Dissipation (Note 2)
1.28W
Storage Temperature
-65C to +150C
Soldering Time, Temperature (Note
3)
Wave (4 seconds)
Infrared (10 seconds)
Vapor Phase (75 seconds)
260C
240C
219C
ESD Susceptibility (Note 4)
1.3 kV
Operating Ratings
(Note 1)
Supply Voltage Range (PV
IN
and
V
IN
)
4.5V to 18V
Junction Temperature Range
-40C to +125C
Electrical Characteristics
V
PVIN
= 15V, V
SLEEP LOGIC
= 0V and V
SD
= 0V unless superseded under Conditions. Typicals and limits appearing in plain
type apply for T
A
= T
J
= +25C. Limits appearing in boldface type apply over the full junction temperature range shown under
Operating Ratings.
Symbol
Parameter
Conditions
Typ (Note 5)
Limit (Note 6)
Units
V
OUT
Output Voltage
R1 = 75 k
, 1%,
R2 = 25 k
, 1%,
7.5V
V
PVIN
18V
0.12A
I
LOAD
3A
5.00
4.80/4.75
5.20/5.25
V
V(min)
V(max)
1
System Efficiency
I
LOAD
= 1A, T
A
= 25C,
F
OSC
Not Adjusted
94
%
2
System Efficiency
I
LOAD
= 3A, T
A
= 25C,
F
OSC
Not Adjusted
89
%
V
REF
Reference Voltage
V
SLEEPLOGIC
= 3V (Note 7)
1.25
1.281/1.294
1.219/1.206
V(min)
V(max)
I
Q
Quiescent Current in PWM
mode
V
FB
= V
REF
-20mV (Note 8)
4.0
6.50/7.0
mA
mA(max)
I
QS
Quiescent Current in Sleep
mode
IV
FB
= V
REF
-20mV,
V
SLEEPLOGIC
= 3V (Note 8)
850
1.35/1.60
A
mA(max)
I
QSD
Quiescent Current in Shutdown
mode
V
SD
= 3V
(Note 8)
9
20/25
A
A(max)
R
DS(on)
HS
DC On-Resistance
Drain-to-Source of the
High-Side Power Switch
I
DS
= 1A,
V
SLEEPLOGIC
= 3V,
V
FB
= 3V,
V
BOOT
= 24V
130
170/245
m
m
(max)
R
DS(on)
LS
DC On-Resistance
Drain-to-Source of the
Low-Side Power Switch
I
DS
= 1A,
V
FB
= 3V
125
175/245
m
m
(max)
I
L HS
Leakage current of the
High-Side Power Switch
V
PVIN
= 18V, V
SW
= 0V,
V
SD
= 3V
100
10
nA
A(max)
I
L LS
Leakage current of the
Low-Side Power Switch
V
PVIN
= 18V, V
SW
= 18V,
V
SD
= 3V
95
210
A
A(max)
I
LIMIT
Active Current Limit of the
High-Side Power Switch
V
PVIN
= 15V,
V
BOOT
= 24V,
V
FB
= 3V,
V
SLEEPLOGIC
= 3V,
5.5
3.5
7.5
A
A(min)
A(max)
F
OSC
Oscillator Frequency
V
FB
= V
REF
-20 mV
90
80/75
100/105
kHz
kHz(min)
kHz(max)
F
MAX
Maximum Oscillator Frequency
I
FREQ ADJ
= 100A,(Note 9)
V
FB
= V
REF
-20 mV
315
270/260
360/370
kHz
kHz(min)
kHz(max)
D
MAX
Maximum Duty Cycle
V
FB
= V
REF
-20 mV,
F
OSC
Not Adjusted
97
94/93
%
%(min)
LM2650
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3
Electrical Characteristics
(Continued)
V
PVIN
= 15V, V
SLEEP LOGIC
= 0V and V
SD
= 0V unless superseded under Conditions. Typicals and limits appearing in plain
type apply for T
A
= T
J
= +25C. Limits appearing in boldface type apply over the full junction temperature range shown under
Operating Ratings.
Symbol
Parameter
Conditions
Typ (Note 5)
Limit (Note 6)
Units
D
MIN
Minimum Duty Cycle
V
FB
= V
REF
+50 mV,
F
OSC
Not Adjusted
2.8
5
%
%(min)
V
DD
Internal Rail Voltage
I
VDD
= 1 mA
4.0
3.6/3.4
4.2/4.3
V
V(min)
V(max)
V
BOOT
Bootstrap Regulator Voltage
(VRegH)
I
BOOT
= 1 mA
7.5
6.5/6.0
V
V(min)
I
SS
Soft Start Current
10
13.5/20.0
A
A(max)
V
HYST
Hysteresis of the Sleep
Comparator (C2
Figure 2)
V
SLEEPLOGIC
= 3V
30
10
50
mV
mV(min)
mV(max)
V
IL
of SD
0.95
V(max)
V
IH
of SD
2.10
V(min)
V
IL
of SLEEP LOGIC
0.9
V(max)
V
IH
of SLEEP LOGIC
2.0
V(min)
V
IL
of SYNC
0.50
V(max)
V
IH
of SYNC
1.45
V(min)
T
SD
T
J
for Thermal Shutdown
170
C
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which the device operates
correctly. Operating ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics.
Note 2: This rating is calculated using the formula P
DCmax
= (T
Jmax
- T
A
) /
JA
, where P
DCmax
is the absolute maximum power dissipation, T
Jmax
is the maximum
junction temperature, and
JA
is the junction ot ambient thermal resistance of the package. The P
DCmax
rating of 1.28W results from substituting 170C, 70C and
78C/W for T
Jmax
, T
A
and
JA
respectively. A
JA
of 78C represents the worst condition of no heat sinking of the M24B small-outline package. Heat sinking allows
the safe dissipation of more power. See Application Notes on thermal management. The LM2650 actively limits its junction temperature to about 170C.
Note 3: For detailed information on soldering plastic small-outline packages, refer to the Packaging Databook published by National Semiconductor Corporation.
Note 4: ESD is applied using the human-body model, a 100pF capacitor discharged through a 1.5k
resistor.
Note 5: A typical is the center of characterization data taken at T
A
= T
J
= 25C.
Note 6: All limits are guaranteed. The guarantee is backed with 100% testing at T
A
= T
J
= 125C and statistical correlation for room temperature and cold limits.
Note 7: V
REF
is measured at SLEEP OUT ADJ.
Note 8: Quiescent current is the total current flowing into the P
VIN
and V
IN
pins. I
Q
includes the current used to drive the gates of the two NMOS power FETs at the
nominal switching frequency. I
QS
includes no such current.
Note 9: Pulling 100A out of FREQ ADJ simulates adjusting the oscillator frequency with a 12.5 k
resistor connected from FREQ ADJ to GND. The sleep mode
cannot be used at switching frequencies above 250 kHz.
LM2650
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4
Typical Performance Characteristics
I
QSD
vs Input Voltage
DS012848-3
I
QS
vs Input Voltage
DS012848-4
I
Q
vs Input Voltage
DS012848-5
I
Q
vs Oscillator Frequency
DS012848-6
R
DS(on)
Low-Side vs Input Voltage
DS012848-7
R
DS(on)
High-Side vs Input Voltage
DS012848-8
R
DS(on)
Low-Side vs Junction
Temperature
DS012848-9
R
DS(on)
High-Side vs Junction
Temperature
DS012848-10
Oscillator Frequency vs Junction
Temperature
DS012848-11
Oscillator Frequency vs Adjusting Resistor
DS012848-12
Current Limit vs Junction Temperature
DS012848-13
LM2650
www.national.com
5
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