LM2662/LM2663
Switched Capacitor Voltage Converter

General Description

The LM2662/LM2663 CMOS charge-pump voltage con-
verter inverts a positive voltage in the range of 1.5V to 5.5V
to the corresponding negative voltage. The LM2662/LM2663
uses two low cost capacitors to provide 200 mA of output
current without the cost, size, and EMI related to inductor
based converters. With an operating current of only 300 µA
and operating efficiency greater than 90% at most loads, the
LM2662/LM2663 provides ideal performance for battery
powered systems. The LM2662/LM2663 may also be used
as a positive voltage doubler.

The oscillator frequency can be lowered by adding an exter-
nal capacitor to the OSC pin. Also, the OSC pin may be used
to drive the LM2662/LM2663 with an external clock. For
LM2662, a frequency control (FC) pin selects the oscillator
frequency of 20 kHz or 150 kHz. For LM2663, an external
shutdown (SD) pin replaces the FC pin. The SD pin can be
used to disable the device and reduce the quiescent current
to 10 µA. The oscillator frequency for LM2663 is 150 kHz.

Features

Inverts or doubles input supply voltage

Narrow SO-8 Package

3.5

typical output resistance

86% typical conversion efficiency at 200 mA

(LM2662) selectable oscillator
frequency: 20 kHz/150 kHz

(LM2663) low current shutdown mode

Applications

Laptop computers

Cellular phones

Medical instruments

Operational amplifier power supplies

Interface power supplies

Handheld instruments

Basic Application Circuits

Voltage Inverter

DS100003-1

Positive Voltage Doubler

DS100003-2

Splitting V

in Half

DS100003-3

January 1999

LM2662/LM2663

Switched

Capacitor

oltage

Converter

DS100003

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Absolute Maximum Ratings

(Note 1)

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.

Supply Voltage (V+ to GND, or GND to OUT)

(OUT - 0.3V) to (GND + 3V)

FC, OSC, SD

The least negative of (OUT - 0.3V)

or (V+ - 6V) to (V+ + 0.3V)

V+ and OUT Continuous Output Current

250 mA

Output Short-Circuit Duration to GND (Note 2)

1 sec.

Power Dissipation (T

= 25°C) (Note 3)

735 mW

Max (Note 3)

150°C

(Note 3)

170°C/W

Operating Junction Temperature

Range

-40°C to +85°C

Storage Temperature Range

-65°C to +150°C

Lead Temperature (Soldering, 10 seconds)

300°C

ESD Rating

2 kV

Electrical Characteristics

Limits in standard typeface are for T

= 25°C, and limits in boldface type apply over the full operating temperature range.

Unless otherwise specified: V+ = 5V, FC = Open, C

= C

= 47 µF.(Note 4)

Symbol

Parameter

Condition

Min

Typ

Max

Units

V+

Supply Voltage

= 1k

Inverter, LV = Open

3.5

5.5

Inverter, LV = GND

1.5

5.5

Doubler, LV = OUT

2.5

5.5

Supply Current

No Load

FC = V+ (LM2662)

1.3

LV = Open

SD = Ground (LM2663)

FC = Open

0.3

0.8

Shutdown Supply Current

µA

(LM2663)

Shutdown Pin Input Voltage

Shutdown Mode

2.0

(Note 5)

(LM2663)

Normal Operation

0.3

Output Current

200

OUT

Output Resistance (Note 6)

= 200 mA

3.5

OSC

Oscillator Frequency (Note 7)

OSC = Open

FC = Open

kHz

FC = V+

150

Switching Frequency (Note 8)

OSC = Open

FC = Open

3.5

kHz

FC = V+

27.5

OSC

OSC Input Current

FC = Open

µA

FC = V+

EFF

Power Efficiency

(500) between V

and OUT

= 200 mA to GND

OEFF

Voltage Conversion Efficiency

No Load

99.96

Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device
beyond its rated operating conditions.

Note 2: OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be avoided. Also, for tem-
peratures above 85°C, OUT must not be shorted to GND or V+, or device may be damaged.

Note 3: The maximum allowable power dissipation is calculated by using P

DMax

= (T

JMax

- T

, where T

JMax

is the maximum junction temperature, T

is the

ambient temperature, and

is the junction-to-ambient thermal resistance of the specified package.

Note 4: In the test circuit, capacitors C

and C

are 47 µF, 0.2

maximum ESR capacitors. Capacitors with higher ESR will increase output resistance, reduce output

voltage and efficiency.

Note 5: In doubling mode, when V

out

5V, minimum input high for shutdown equals V

out

- 3V.

Note 6: Specified output resistance includes internal switch resistance and capacitor ESR.

Note 7: For LM2663, the oscillator frequency is 150 kHz.

Note 8: The output switches operate at one half of the oscillator frequency, f

OSC

= 2f

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Connection Diagrams

Pin Description

Pin

Name

Function

Voltage Inverter

Voltage Doubler

Frequency control for internal oscillator:

Same as inverter.

(LM2662)

FC = open, f

OSC

= 20 kHz (typ);

FC = V+, f

OSC

= 150 kHz (typ);

FC has no effect when OSC pin is driven
externally.

(LM2663)

Shutdown control pin, tie this pin to the ground
in normal operation.

Same as inverter.

CAP+

Connect this pin to the positive terminal of
charge-pump capacitor.

Same as inverter.

GND

Power supply ground input.

Power supply positive voltage input.

CAP-

Connect this pin to the negative terminal of
charge-pump capacitor.

Same as inverter.

OUT

Negative voltage output.

Power supply ground input.

Low-voltage operation input. Tie LV to GND
when input voltage is less than 3.5V. Above
3.5V, LV can be connected to GND or left
open. When driving OSC with an external clock,
LV must be connected to GND.

LV must be tied to OUT.

OSC

Oscillator control input. OSC is connected to an
internal 15 pF capacitor. An external capacitor
can be connected to slow the oscillator. Also,
an external clock can be used to drive OSC.

Same as inverter except that OSC cannot be
driven by an external clock.

V+

Power supply positive voltage input.

Positive voltage output.

Circuit Description

The LM2662/LM2663 contains four large CMOS switches
which are switched in a sequence to invert the input supply
voltage. Energy transfer and storage are provided by exter-
nal capacitors.

Figure 2 illustrates the voltage conversion

scheme. When S

and S

are closed, C

charges to the sup-

ply voltage V+. During this time interval switches S

and S

are open. In the second time interval, S

and S

are open

and S

are closed, C

is charging C

. After a number

of cycles, the voltage across C

will be pumped to V+. Since

the anode of C

is connected to ground, the output at the

cathode of C

equals -(V+) assuming no load on C

, no loss

in the switches, and no ESR in the capacitors. In reality, the
charge transfer efficiency depends on the switching fre-
quency, the on-resistance of the switches, and the ESR of
the capacitors.

8-Lead SO (M)

DS100003-20

DS100003-21

Top View

Order Number LM2662M, LM2663M

See NS Package Number M08A

DS100003-22

FIGURE 2. Voltage Inverting Principle

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Application Information

SIMPLE NEGATIVE VOLTAGE CONVERTER

The main application of LM2662/LM2663 is to generate a
negative supply voltage. The voltage inverter circuit uses
only two external capacitors as shown in the Basic Applica-
tion Circuits. The range of the input supply voltage is 1.5V to
5.5V. For a supply voltage less than 3.5V, the LV pin must be
connected to ground to bypass the internal regulator cir-
cuitry. This gives the best performance in low voltage appli-
cations. If the supply voltage is greater than 3.5V, LV may be
connected to ground or left open. The choice of leaving LV
open simplifies the direct substitution of the LM2662/
LM2663 for the LMC7660 Switched Capacitor Voltage Con-
verter.

The output characteristics of this circuit can be approximated
by an ideal voltage source in series with a resistor. The volt-
age source equals -(V+). The output resistance R

out

is a

function of the ON resistance of the internal MOS switches,
the oscillator frequency, and the capacitance and ESR of C

and C

. Since the switching current charging and discharg-

ing C

is approximately twice as the output current, the effect

of the ESR of the pumping capacitor C

is multiplied by four

in the output resistance. The output capacitor C

is charging

and discharging at a current approximately equal to the out-
put current, therefore, its ESR only counts once in the output
resistance. A good approximation is:

where R

is the sum of the ON resistance of the internal

MOS switches shown in

Figure 2.

High value, low ESR capacitors will reduce the output resis-
tance. Instead of increasing the capacitance, the oscillator
frequency can be increased to reduce the 2/(f

osc

x C

) term.

Once this term is trivial compared with R

and ESRs, fur-

ther increasing in oscillator frequency and capacitance will
become ineffective.

The peak-to-peak output voltage ripple is determined by the
oscillator frequency, and the capacitance and ESR of the
output capacitor C

Again, using a low ESR capacitor will result in lower ripple.

POSITIVE VOLTAGE DOUBLER

The LM2662/LM2663 can operate as a positive voltage dou-
bler (as shown in the Basic Application Circuits). The dou-
bling function is achieved by reversing some of the connec-
tions to the device. The input voltage is applied to the GND
pin with an allowable voltage from 2.5V to 5.5V. The V+ pin
is used as the output. The LV pin and OUT pin must be con-
nected to ground. The OSC pin can not be driven by an ex-
ternal clock in this operation mode. The unloaded output
voltage is twice of the input voltage and is not reduced by the
diode D

's forward drop.

The Schottky diode D

is only needed for start-up. The inter-

nal oscillator circuit uses the V+ pin and the LV pin (con-
nected to ground in the voltage doubler circuit) as its power
rails. Voltage across V+ and LV must be larger than 1.5V to
insure the operation of the oscillator. During start-up, D

used to charge up the voltage at V+ pin to start the oscillator;
also, it protects the device from turning-on its own parasitic

diode and potentially latching-up. Therefore, the Schottky di-
ode D

should have enough current carrying capability to

charge the output capacitor at start-up, as well as a low for-
ward voltage to prevent the internal parasitic diode from
turning-on. A Schottky diode like 1N5817 can be used for
most applications. If the input voltage ramp is less than 10V/
ms, a smaller Schottky diode like MBR0520LT1 can be used
to reduce the circuit size.

SPLIT V+ IN HALF

Another interesting application shown in the Basic Applica-
tion Circuits is using the LM2662/LM2663 as a precision volt-
age divider. Since the off-voltage across each switch equals
V

/2, the input voltage can be raised to +11V.

CHANGING OSCILLATOR FREQUENCY

For the LM2662, the internal oscillator frequency can be se-
lected using the Frequency Control (FC) pin. When FC is
open, the oscillator frequency is 20 kHz; when FC is con-
nected to V+, the frequency increases to 150 kHz. A higher
oscillator frequency allows smaller capacitors to be used for
equivalent output resistance and ripple, but increases the
typical supply current from 0.3 mA to 1.3 mA.

The oscillator frequency can be lowered by adding an exter-
nal capacitor between OSC and GND (See typical perfor-
mance characteristics). Also, in the inverter mode, an exter-
nal clock that swings within 100 mV of V+ and GND can be
used to drive OSC. Any CMOS logic gate is suitable for driv-
ing OSC. LV must be grounded when driving OSC. The
maximum external clock frequency is limited to 150 kHz.

The switching frequency of the converter (also called the
charge pump frequency) is half of the oscillator frequency.

Note: OSC cannot be driven by an external clock in the voltage-doubling

mode.

TABLE 1. LM2662 Oscillator Frequency Selection

OSC

Oscillator

Open

20 kHz

V+

Open

150 kHz

Open or V+

External Capacitor

See Typical
Performance
Characteristics

N/A

External Clock

(inverter mode only)

Frequency

TABLE 2. LM2663 Oscillator Frequency Selection

OSC

Oscillator

Open

150 kHz

External
Capacitor

See Typical Performance
Characteristics

External Clock

External Clock Frequency

(inverter mode only)

SHUTDOWN MODE

For the LM2663, a shutdown (SD) pin is available to disable
the device and reduce the quiescent current to 10 µA. Apply-
ing a voltage greater than 2V to the SD pin will bring the de-
vice into shutdown mode. While in normal operating mode,
the SD pin is connected to ground.

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Application Information

(Continued)

CAPACITOR SELECTION

As discussed in the

Simple Negative Voltage Converter section, the output resistance and ripple voltage are dependent on the

capacitance and ESR values of the external capacitors. The output voltage drop is the load current times the output resistance,
and the power efficiency is

Where I

(V+) is the quiescent power loss of the IC device, and I

OUT

is the conversion loss associated with the switch on-

resistance, the two external capacitors and their ESRs.

Low ESR capacitors (

Table 3) are recommended for both capacitors to maximize efficiency, reduce the output voltage drop and

voltage ripple. For convenience, C

and C

are usually chosen to be the same.

The output resistance varies with the oscillator frequency and the capacitors. In

Figure 3, the output resistance vs. oscillator fre-

quency curves are drawn for four difference capacitor values. At very low frequency range, capacitance plays the most important
role in determining the output resistance. Once the frequency is increased to some point (such as 100 kHz for the 47 µF capaci-
tors), the output resistance is dominated by the ON resistance of the internal switches and the ESRs of the external capacitors.
A low value, smaller size capacitor usually has a higher ESR compared with a bigger size capacitor of the same type. Ceramic
capacitors can be chosen for their lower ESR. As shown in

Figure 3, in higher frequency range, the output resistance using the

10 µF ceramic capacitors is close to these using higher value tantalum capacitors.

TABLE 3. Low ESR Capacitor Manufacturers

Manufacturer

Phone

Capacitor Type

Nichicon Corp.

(708)-843-7500

PL, PF series, through-hole aluminum electrolytic

AVX Corp.

(803)-448-9411

TPS series, surface-mount tantalum

Sprague

(207)-324-4140

593D, 594D, 595D series, surface-mount tantalum

Sanyo

(619)-661-6835

OS-CON series, through-hole aluminum electrolytic

Murata

(800)-831-9172

Ceramic chip capacitors

Taiyo Yuden

(800)-348-2496

Ceramic chip capacitors

Tokin

(408)-432-8020

Ceramic chip capacitors

DS100003-36

FIGURE 3. Output Source Resistance vs Oscillator Frequency

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Other Applications

PARALLELING DEVICES

Any number of LM2662s (or LM2663s) can be paralleled to reduce the output resistance. Each device must have its own pumping
capacitor C

, while only one output capacitor C

out

is needed as shown in

Figure 4. The composite output resistance is:

CASCADING DEVICES

Cascading the LM2662s (or LM2663s) is an easy way to produce a greater negative voltage (as shown in

Figure 5). If n is the

integer representing the number of devices cascaded, the unloaded output voltage V

out

is (-nV

). The effective output resistance

is equal to the weighted sum of each individual device:

A three-stage cascade circuit shown in

Figure 6 generates -3V

, from V

Cascading is also possible when devices are operating in doubling mode. In

Figure 7, two devices are cascaded to generate 3V

An example of using the circuit in

Figure 6 or Figure 7 is generating +15V or -15V from a +5V input.

Note that, the number of n is practically limited since the increasing of n significantly reduces the efficiency and increases the out-
put resistance and output voltage ripple.

DS100003-24

FIGURE 4. Lowering Output Resistance by Paralleling Devices

DS100003-25

FIGURE 5. Increasing Output Voltage by Cascading Devices

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Physical Dimensions

inches (millimeters) unless otherwise noted

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2. A critical component in any component of a life support

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8-Lead SO (M)

Order Number LM2662M or LM2663M

NS Package Number M08A

LM2662/LM2663

Switched

Capacitor

oltage

Converter

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

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