LM2725/LM2726
High Speed Synchronous MOSFET Drivers
General Description
The LM2725/LM2726 is a family of dual MOSFET drivers
that can drive both the top MOSFET and bottom MOSFET in
a push-pull structure simultaneously. It takes a logic level
PWM input and splits it into two complimentary signals with
a
typical
20ns
dead
time
in
between. The
built-in
shoot-through protection circuitry prevents the top and bot-
tom FETs from turning on simultaneously. With a bias volt-
age of 5V, the peak sourcing and sinking current for each
driver of the LM2725 is about 1.2A and that of the LM2726 is
about 3A. In an SO-8 package, each driver is able to handle
50mA
average
current.
Input
UVLO
(Under-Voltage-Lock-Out) ensures that all the driver outputs
stay low until the supply rail exceeds the power-on threshold
during system power on, or after the supply rail drops below
power-on threshold by a specified hysteresis during system
power down. The cross-conduction protection circuitry de-
tects both the driver outputs and will not turn on a driver until
the other driver output is low. The top gate bias voltage
needed by the top MOSFET can be obtained through an
external bootstrap structure. Minimum pulse width is as low
as 55ns.
Features
n
High peak output current
n
Adaptive shoot-through protection
n
36V SW pin absolute maximum voltage
n
Input Under-Voltage-Lock-Out
n
Typical 20ns internal delay
n
Plastic 8-pin SO package
Applications
n
High Current DC/DC Power Supplies
n
High Input Voltage Switching Regulators
n
Microprocessors
Typical Application
Connection Diagram
DS200072-1
8-Lead Small Outline Package
DS200072-2
Top View
November 2000
LM2725/LM2726
High
Speed
Synchronous
MOSFET
Drivers
2000 National Semiconductor Corporation
DS200072
www.national.com
Ordering Information
Order Number
Package Type
NSC Package Drawing
Supplied As
LM2725
LM2725M
M08A
95 Units/Rail
LM2725MX
2500 Units/Reel
LM2726
LM2726M
95 Units/Rail
LM2726MX
2500 Units/Reel
Pin Description
Pin
Name
Function
1
SW
Top driver return. Should be connected to the common node of
top and bottom FETs
2
HG
Top gate drive output
3
CBOOT
Bootstrap. Accepts a bootstrap voltage for powering the high-side
driver
4
PWM_IN
Accepts a 5V-logic control signal
5
EN
Chip Enable
6
VCC
Connect to +5V supply
7
LG
Bottom gate drive output
8
GND
Ground
Block Diagram
DS200072-4
LM2725/LM2726
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC
7.5V
CBOOT
42V
CBOOT to SW
8V
SW to PGND
36V
Junction Temperature
+150C
Power Dissipation
(Note 2)
720mW
Storage Temperature
-65 to 150C
ESD Susceptibility
Human Body Model (Note 3)
1 kV
Soldering Time, Temperature
10sec., 300C
Operating Ratings
(Note 1)
VCC
4V to 7V
Junction Temperature Range
0 to 125C
Electrical Characteristics
LM2725
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T
A
= T
J
= +25C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
POWER SUPPLY
I
q_op
Operating Quiescent
Current
PWM_IN = 0V
180
250
A
I
q_sd
Shutdown Quiescent
Current
EN = 0V, PWM_IN = 0V
0.5
15
A
TOP DRIVER
Peak Pull-Up Current
Test Circuit 1, V
bias
= 5V,
R = 0.1
1.2
A
Pull-Up Rds_on
I
CBOOT
= I
HG
= 0.7A
2.4
Peak Pull-down Current
Test Circuit 2, V
bias
= 5V,
R = 0.1
-1.0
A
Pull-down Rds_on
I
SW
= I
HG
= 0.7A
1.4
t
4
Rise Time
Timing Diagram, C
LOAD
=
3.3nF
17
ns
t
6
Fall Time
10
ns
t
3
Pull-Up Dead Time
Timing Diagram
23
ns
t
5
Pull-Down Delay
Timing Diagram, from
PWM_IN Falling Edge
21
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, V
bias
= 5V,
R = 0.1
1.2
A
Pull-up Rds_on
I
VCC
= I
LG
= 0.7A
2.6
Peak Pull-down Current
Test Circuit 4, V
bias
= 5V,
R = 0.1
-2
A
Pull-down Rds_on
I
GND
= I
LG
= 0.7A
0.65
t
8
Rise Time
Timing Diagram, C
LOAD
=
3.3nF
18
ns
t
2
Fall Time
6
ns
t
7
Pull-up Dead Time
Timing Diagram
28
ns
t
1
Pull-down Delay
Timing Diagram, from
PWM_IN Rising Edge
15
ns
LOGIC
V
uvlo_up
Power On Threshold
VCC rises from 0V toward
5V
3.0
V
V
uvlo_dn
Under-Voltage-Lock-Out
Threshold
2.5
V
V
uvlo_hys
Under-Voltage-Lock-Out
Hysteresis
0.5
V
LM2725/LM2726
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3
Electrical Characteristics
LM2725
(Continued)
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T
A
= T
J
= +25C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
LOGIC
V
IH_EN
EN Pin High Input
2.4
V
V
IL_EN
EN Pin Low Input
0.8
V
I
leak_EN
EN Pin Leakage Current
EN = VCC = 5V
-2
2
A
VCC = 5V, EN = 0V
-2
2
t
on_min
Minimum Positive Input
Pulse Width
(Note 4)
55
ns
t
off_min
Minimum Negative Input
Pulse Width
(Note 5)
55
V
IH_PWM
PWM_IN High Level
Input Voltage
When PWM_IN pin goes
high from 0V
2.4
V
V
IL_PWM
PWM_IN Low Level
Input Voltage
When PWM_IN pin goes
low from 5V
0.8
Electrical Characteristics
LM2726
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T
A
= T
J
= +25C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
POWER SUPPLY
I
q_op
Operating Quiescent
Current
PWM_IN = 0V
185
250
A
I
q_sd
Shutdown Quiescent
Current
EN = 0V, PWM_IN = 0V
0.5
15
A
TOP DRIVER
Peak Pull-Up Current
Test Circuit 1, V
bias
= 5V,
R = 0.1
3.0
A
Pull-Up Rds_on
I
CBOOT
= I
HG
= 1.0A
1.2
Peak Pull-down Current
Test Circuit 2, V
bias
= 5V,
R = 0.1
-3.2
A
Pull-down Rds_on
I
SW
= I
HG
= 1.0A
0.5
t
4
Rise Time
Timing Diagram, C
LOAD
=
3.3nF
17
ns
t
6
Fall Time
12
ns
t
3
Pull-Up Dead Time
Timing Diagram
19
ns
t
5
Pull-Down Delay
Timing Diagram, from
PWM_IN from Falling Edge
27
ns
BOTTOM DRIVER
Peak Pull-Up Current
Test Circuit 3, V
bias
= 5V,
R = 0.1
3.2
A
Pull-up Rds_on
I
VCC
= I
LG
= 1.0A
1.1
Peak Pull-down Current
Test Circuit 4, V
bias
= 5V,
R = 0.1
-3.2
A
Pull-down Rds_on
I
GND
= I
LG
= 1.0A
0.6
t
8
Rise Time
Timing Diagram, C
LOAD
=
3.3nF
17
ns
t
2
Fall Time
14
ns
t
7
Pull-up Dead Time
Timing Diagram
12
ns
LM2725/LM2726
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4
Electrical Characteristics
LM2726
(Continued)
VCC = CBOOT = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for T
A
= T
J
= +25C. Limits appearing in boldface type apply over the entire operating temperature range.
Symbol
Parameter
Condition
Min
Typ
Max
Units
BOTTOM DRIVER
t
1
Pull-down Delay
Timing Diagram, from
PWM_IN Rising Edge
13
ns
LOGIC
V
uvlo_up
Power On Threshold
VCC rises from 0V toward
5V
2.8
V
V
uvlo_dn
Under-Voltage-Lock-Out
Threshold
2.5
V
V
uvlo_hys
Under-Voltage-Lock-Out
Hysteresis
0.3
V
V
IH_EN
EN Pin High Input
2.4
V
V
IL_EN
EN Pin Low Input
0.25
V
I
leak_EN
EN Pin Leakage Current
EN = VCC = 5V
-2
2
A
VCC = 5V, EN = 0V
-2
2
t
on_min
Minimum Positive Input
Pulse Width
(Note 4)
55
ns
t
off_min
Minimum Negative Input
Pulse Width
(Note 5)
55
V
IH_PWM
PWM_IN High Level
Input Voltage
When PWM_IN pin goes
high from 0V
2.4
V
V
IL_PWM
PWM_IN Low Level
Input Voltage
When PWM_IN pin goes
low from 5V
0.25
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which the device operates
correctly. Operating Ratings do not imply guaranteed performance limits.
Note 2: Maximum allowable power dissipation is a function of the maximum junction temperature, T
JMAX
, the junction-to-ambient thermal resistance,
JA
, and the
ambient temperature, T
A
. The maximum allowable power dissipation at any ambient temperature is calculated using: P
MAX
= (T
JMAX
-T
A
) /
JA
. The junction-to-
ambient thermal resistance,
JA
, for LM2725/LM2726 is 172C/W. For a T
JMAX
of 150C and T
A
of 25C, the maximum allowable power dissipation is 0.7W.
Note 3: ESD machine model susceptibility is 100V.
Note 4: If after a rising edge, a falling edge occurs sooner than the specified value, the IC may intermittently fail to turn on the bottom gate when the top gate is off.
As the falling edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
Note 5: If after a falling edge, a rising edge occurs sooner than the specified value, the IC may intermittently fail to turn on the top gate when the bottom gate is off.
As the rising edge occurs sooner and sooner, the driver may start to ignore the pulse and produce no output.
LM2725/LM2726
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