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Электронный компонент: LM9701

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2002 National Semiconductor Corporation
www.national.com
ADVANCE INFORMATION
October 2002
LM9701 Digital Image Processor w/ Integrated Pre-processor
General Description
The LM9701 is a cost effective, digital image processor based
around the ARM7
TM
32 bit RISC processor. The chip has been
designed to operate with National's family of advanced CMOS
image sensors allowing a complete camera solution for imaging
applications.
Features
!
Embedded 32 bit ARM7
TM
TDNI RISC processor system
- 16K bytes of internal SRAM
- 8K bytes of instruction Cache
- 4 channel DMA
!
External memory bus supporting:
- 64 M-byte address space for SRAM and Flash
- 64 M-bit address space for SDRAM
!
Processor Peripherals
- Two full duplex UARTs
-
wire/SPI serial port
- Versitile timer
- ARM timer
- Interrupt controller
- 16 general purpose IOs
- Real time clock
!
Glueless CMOS image sensor interface
- 10 bit data, vsync, hsync and pclk
- Fast I
2
C compatible serial Interface
!
Image Pre-processor
- Defective pixel correction (up to 1024)
- Linearization table
- 4 channel digital gain and offset adjustment
- Raw data statistics
!
Integrated USB v1.1 for connection to PC
!
System management
- Internal Clock generation from 12MHz Crystal
- Power management
- Reset generation
- JTAG based serial on-chip debug interface
Applications
!
Clip On Camera
!
Digital Still Camera
!
Industrial Camera
!
Automotive Camera
!
Security Camera
Key Specifications
Input Format
Color Bayer Pattern
Monochrome
Input Pixel Rate
12 Meg-pixels/s
Digital Image Pre-Processor
10 bit
External Memory
- Memory Type
- Address Space
- Speed
SRAM, Flash, SDRAM
24 bit
up to 75MHz
Serial Interfaces
- I
2
C compatible master
-
wire/SPI
- UART
up to 400KHz
up to 6.0 MHz
up to 921.6 K bits/s
32 bit ARM7 Processor
- MIPS
- Internal Memory
- Instruction Cache
up to 75
16K-bytes
8K-bytes
Clock Inputs
- System
- Real Time Clock
12 Mhz Cystal
32 KHz Crystal
Power Supply
- Core
- IO
1.8 Volt
3.3 Volt
Power Dissipation
< 100mW
Package
144 LQFP
Operating temperature
-40
o
C to +85
o
C
System Block Diagram
ARM, ARM7 and ARM7TDMI are registered trademarks of ARM Limited
LM9701
UART
USB
Flash
SRAM
SDRAM
WIRE/SP
Di
gi
ta
l
V
i
de
o
Ou
t
CMOS Image
Sensor
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www.national.com
Overall Chip Block Diagram
I
2
C Compatible
APB
Master
wire/SPI
Master
ARM
GPIO
ARM7 TDMI
16Kbyte
4 Channel
Interrupt
Controller
ARM7 TDMI -Microprocessor System
APB
i2cm
mwire
Timer
usb
DMA
16 Pin
Real Time
Clock
usart
gpio
int
jtag
USB
V1.1
Image PreProcessor
S
e
ns
or
I
/
F
Of
fs
e
t
Config & Raw Statistics Measurement Engine
Ba
d
P
i
x
e
l
C
o
rre
c
t
i
o
n
Co
lo
r
Ga
i
n
sen
Bridge
USART1
8Kbyte
Cache
Versitile
Timer
timer
Bus Interface
Unit
Fr
a
m
e
S
k
i
p
pi
ng
Li
ne
ar
i
z
a
t
i
o
n
Ta
b
l
e
usart
USART0
RAM
AHB
Wrapper
SDRAM
Controller
AHB
Br
i
d
g
e
POR
PLL
JTAG
AH
B
System
Management
ReMap +
Pause
rtc
sys
L
M
9701
3
www.national.com
Connection Diagram
Figure 1. Pin Diagram
1
3
4
5
6
7
8
9
10
12
11
vdd_io1
mem_xd1_sdram_d1
vss_io1
mem_xd5_sdram_d5
144 PIN
2
mem_xd4_sdram_d4
13
15
16
17
18
19
20
21
22
24
23
14
25
Plastic Qual Flatpak
(LQFP) JEDEC
mem_xd0_sdram_d0
mem_xd2_sdram_d2
mem_xd3_sdram_d3
mem_xd6_sdram_d6
vdd_core2
vss_core2
mem_xd7_sdram_d7
mem_xd8_sdram_d8
mem_xd12_sdram_d12
mem_xd9_sdram_d9
mem_xd10_sdram_d10
mem_xd11_sdram_d11
mem_xd13_sdram_d13
vss_io2
mem_xd14_sdram_d14
mem_xd15_vmem_d15
mem_cs2
mem_cs1
gpio15_sys_int
26
27
28
29
30
31
32
33
35
34
36
mem_cs0
mem_xoe
mem_xgwe_sdram_we
vdd_io3
sdram_cke
sdram_cs
vdd_core2
sdram_clk
vss_io3
mem_lbyte_sdram_dqml
mem_hbyte_sdram_dqmh
37
39
40
41
42
43
44
45
46
48
47
vd
d
_
i
o
4
me
m_
x
a
2
_
s
d
r
a
m
_
a
2
m
e
m
_
x
a4_
s
d
r
a
m
_
a4
38
me
m_
x
a
3
_
s
d
r
a
m
_
a
3
49
51
52
53
54
55
56
57
58
60
59
50
61

m
e
m
_
x
a1_
s
d
r
a
m
_
a1
vs
s_
i
o
4
m
e
m
_
x
a5_
s
d
r
a
m
_
a5
m
e
m
_
x
a6_
s
d
r
a
m
_
a6
m
e
m
_
x
a7_
s
d
r
a
m
_
a7
vd
d
_
i
o
5
m
e
m
_
x
a8_
s
d
r
a
m
_
a8
m
e
m
_
x
a9_
s
d
r
a
m
_
a9
m
e
m
_
x
a
1
0_s
dr
am
_a
10
vs
s_
i
o
5
v
dd_
c
o
re3
me
m_
x
a
1
2
me
m_
x
a
1
1
_
s
d
r
a
m
_
a
1
1
v
ss_
co
r
e
3
me
m_
x
a
1
3
m
e
m
_
x
a
1
4_s
dr
am
_b
a0
vd
d
_
i
o
6

m
e
m
_
x
a0_
s
d
r
a
m
_
a0
62
63
64
65
66
67
68
69
71
70
72
m
e
m
_
x
a
1
5_s
dr
am
_b
a1
m
e
m
_
x
a
16
_s
dr
a
m
_
c
a
s
m
e
m
_
x
a
17
_s
dr
a
m
_
r
as
vs
s_
i
o
6
me
m_
x
a
1
9
me
m_
x
a
1
8
me
m_
x
a
2
1
me
m_
x
a
2
2
me
m
_
x
a
2
0
v
d
d_i
o6
me
m
_
c
s
3
_m
em
_x
a23
108
106
105
104
103
102
101
100
99
97
98
vdd_usb
sys_testen
sys_reset
107
96
94
93
92
91
90
89
88
87
85
86
95
84
usb_dn
vss_core5
vdd_core5
sys_pll_test
vss_pll_d
vdd_pll_d
vdd_clk_a
sys_xtali
sys_xtalo
vss_core4
vdd_core4
rtc_xtali
rtc_xtalo
vdd_rtc
vss_irtc
rtc_int
gpi
o10
83
82
81
80
79
78
77
76
74
75
73
gpio4_mwire_mdodi
gpio3_mwire_mdido
vss_io8
gpio2_mwire_msk
vdd_io8
gpio1_usart1_tx
d
m
a
_
r
e
q_
us
ar
t
_
c
t
s
n
10
9
11
1
11
2
11
3
11
4
11
5
11
6
11
7
11
8
12
0
11
9
usb_dp
vss_usb
v
d
d_i
o1
0
gp
i
o
1
1
_
time
r_tm
0
11
0
gpio7_usart0_rtsn
12
1
12
3
12
4
12
5
12
6
12
7
12
8
12
9
13
0
13
2
13
1
12
2
13
3
gp
i
o
9
gpio6_usart0_rdx
vss_io9
g
p
i
o12
_
time
r_tm
1
g
p
i
o13
_
time
r_tm
2
gpio
1
4_
time
r_tm
3
vs
s_
i
o
1
0
s
e
n_s
c
l
s
e
n_s
da
s
e
n_d0
v
d
d_c
ore
6
vs
s_
c
o
r
e
6
s
e
n_d1
s
e
n_d2
s
e
n_d8
s
e
n_d9
s
e
n_v
s
y
nc
v
d
d_c
ore
7
vs
s_
c
o
r
e
7
gp
i
o
8
_
u
s
ar
t
0
_c
t
s
n
13
4
13
5
13
6
13
7
13
8
13
9
14
0
14
1
14
3
14
2
14
4
s
e
n_hs
y
n
c
v
d
d_i
o1
1
s
e
n_pc
l
k
s
e
n_m
c
l
k
j
t
ag
_t
m
s
j
t
ag
_t
c
k
vs
s_
i
o
1
1
j
t
ag
_t
do
j
t
ag
_t
di
j
t
ag
_t
r
s
t
vs
s_
i
o
7
dm
a_
ac
k
_
us
ar
t
1
_r
t
s
n
_
d
1
6
mem_wait_mwire_msc0l
s
e
n_d3
s
e
n_d4
s
e
n_d5
s
e
n_d6
s
e
n_d7
vdd_io2
gpio0_usart1_rdx
sys_clkin_sys_clko
vss_clk_a
gpio5_usart0_tdx
vdd_io9
4
www.national.com
Signal Grouping Diagram
Figure 2. Signal Grouping Diagram
mem_xa[11:0]/sdram_a[11:0]
mem_xd[15:0]/sdram_d[15:0]
mem_cs[2:0]
mem_oe
usb_dn
usb_dp
gpio8_usart0_ctsn
gpio7_usart0_rtsn
gpio6_usart0_rdx
gpio5_usart0_tdx
sen_d[9:0]
sen_vsync
sen_hsync
sen_pclk
sen_mclk
sen_sda
sen_sclk
gpio10
gpio9
gpio2_mwire_msk
gpio3_mwire_mdido
gpio_4_mwire_mdodi
mem_wait_mwire_msc0le
gpio15_sys_int
jtag_trst
jtag_tdo
jtag_tdi
jtag_tck
jtag_tms
sys_xtali
sys_xtalo
sys_reset
sys_testen
sys_clkin_sys_clko
LM9701
mem_hbyte/sdram_dqmh
mem_lbyte/sdram_dqml
mem_xa[15:14]/sdram_ba[1:0]
mem_xa[16]/sdram_cas
mem_xa[22:18]
USB
USART0
MICROWIRE
GPIO
SENSOR
INTERFACE
GPIO
INTERUPT
SOFTWARE
DEBUG
INTERFACE
SYSTEM
INTERFACE
10
3
16
12
2
7
sdram_cs
sdram_clk
mem_xa[17]/sdram_ras
gpio11_timer_tm0
gpio12_timer_tm1
gpio13_timer_tm2
gpio14_timer_tm3
TIMER
GPIO
rtc_xtali
rtc_xtalo
rtc_int
sys_pll_test
gpio0_usart1_rdx
gpio1_usart1_tdx
USB
dma_ack_usart1_rtsn_d16
dma_req_usart1_ctsn
mem_xa[13:12]
2
sdram_cke
mem_xgwe_sdram_we
mem_cs3_mem_xa23
E
X
T
E
RNA
L
M
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M
O
RY

B
U
S
GPIO
REAL TIME CLOCK
USART1
EXTERNAL
MEMORY
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
www.national.com
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LIFE SUPPORT POLICY
NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use pro-
vided in the labeling, can be reasonably expected to result in
a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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PACKAGE INFORMATION