LMX2353
PLLatinum
TM
Fractional N Single 2.5 GHz Frequency
Synthesizer
General Description
The LMX2353 is a monolithic integrated fractional N fre-
quency synthesizer, designed to be used in a local oscillator
subsystem for a radio transceiver. It is fabricated using Na-
tional's 0.5 ABiC V silicon BiCMOS process. The LMX2353
contains dual modulus prescalers along with modulo 15 or
16 fractional compensation circuitry in the N divider. A 16/17
or 32/33 prescale ratio can be selected for the LMX2353. Us-
ing a fractional N phase locked loop technique, the LMX2353
can generate very stable low noise control signals for UHF
and VHF voltage controlled oscillators (VCO's).
The LMX2353 has a highly flexible 16 level programmable
charge pump supplies output current magnitudes from 100
A to 1.6 mA. Serial data is transferred into the LMX2353 via
a three wire interface (Data, LE, Clock). Supply voltage can
range from 2.7V to 5.5V. The LMX2353 features very low
current consumption; typically 4.5 mA at 3.0V. The LMX2353
is available in a 16-pin TSSOP or a 16-pad CSP surface
mount plastic package.
Features
n
2.7V 5.5V operation
n
Low Current Consumption
I
CC
= 4.5 mA typ
@
V
CC
= 3.0V
n
Programmable or Logical Power Down Mode
I
CC
= 5 A typ
@
V
CC
= 3.0V
n
Modulo 15 or 16 fractional N divider
Supports ratios of 1, 2, 3, 4, 5, 8, 15, or 16
n
Programmable charge pump current levels
100 A to 1.6 mA in 100 A steps
n
Digital Filtered Lock Detect
Applications
n
Portable wireless communications (PCS/PCN, cordless)
n
Zero blind slot TDMA systems
n
Cellular and Cordless telephone systems
n
Spread spectrum communication systems (CDMA)
Functional Block Diagram
MICROWIRE
TM
and PLLatinum
TM
are trademarks of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS101124-1
PRELIMINARY
June 1999
LMX2353
PLLatinum
Fractional
N
Single
2.5
GHz
Frequency
Synthesizer
1999 National Semiconductor Corporation
DS101124
www.national.com
Connection Diagrams
Pin Description
Pin No.
Pin
Name
I/O
Description
CSP
TSSOP
16
1
V
P
--
Power supply for charge pump. Must be
V
CC
.
1
2
CP
O
O
Charge pump output. Connected to a loop filter for driving the control input of an
external VCO.
2
3
GND
--
Ground for PLL digital circuitry.
3
4
f
IN
I
RF prescaler input. Small signal input from the VCO.
4
5
f
INB
I
RF prescaler complimentary input. A bypass capacitor should be placed as close
as possible to this pin and be connected directly to the ground plane.
5
6
GND
--
Ground for PLL analog circuitry.
6
7
OSC
in
I
Oscillator input. A CMOS inverting gate input. The input has a V
CC
/2 input
threshold and can be driven from an external CMOS or TTL logic gate.
7
8
F
o
LD
O
Multiplexed output of N or R divider and lock detect. CMOS output.
8
9
CE
I
PLL Enable. Powers down N and R counters, prescalers, and TRI-STATE
charge
pump output when LOW. Bringing CE high powers up PLL depending on the state
of CTL_WORD.
9
10
CLK
I
High impedance CMOS Clock input. Data for the various counters is clocked into
the 24-bit shift register on the rising edge.
10
11
DATA
I
Binary serial data input. Data entered MSB first. The last two bits are the control
bits. High impedance CMOS input.
11
12
LE
I
Load enable high impedance CMOS input. Data stored in the shift registers is
loaded into one of the 4 internal latches when LE goes HIGH.
12
13
GND
--
Ground.
13
14
V
CC
--
PLL power supply voltage input. May range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane.
14
15
OUT1
--
Programmable CMOS output. Level of the output is controlled by F2[18] bit.
15
16
OUT0
--
Programmable CMOS output. Level of the output is controlled by F2[17] bit.
DS101124-2
TOP VIEW
Order Number LMX2353TM or
LMX2353TMX
See NS Package Number MTC16
DS101124-3
TOP VIEW
Order Number LMX2353SLBX
See NS Package Number SLB16A
www.national.com
2
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
V
CC
-0.3V to 6.5V
Vp
-0.3V to 6.5V
Voltage on any pin with
GND = 0V (V
I
)
-0.3V to V
CC
+0.3V
Storage Temperature Range (T
S
)
-65C to +150C
Lead Temperature (solder, 4 sec.) (T
L
)
+260C
ESD - Human Body Model (Note 2)
2 kV
Recommended Operating
Conditions
Power Supply Voltage
V
CC
2.7V to 5.5V
Vp
V
CC
to 5.5V
Operating Temperature (T
A
)
-40C to +85C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Operating Ratings indicate conditions for which the de-
vice is intended to be functional, but do not guarantee specific performance
limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only for the test condi-
tions listed.
Note 2: This device is a high performance RF integrated circuit and is ESD
sensitive. Handling and assembly of this device should only be done at ESD
free workstations.
Electrical Characteristics
(V
CC
= Vp = 3.0V; -40C
<
T
A
<
85C except as specified).
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
GENERAL
I
CC
Power Supply Current
4.5
mA
I
CC-PWDN
Power Down Current
CE = LOW
5
A
f
IN
RF Operating Frequency
(Note 3)
0.5
2.5
GHz
f
OSC
Oscillator Frequency
(Note 3)
2
50
MHz
f
Phase Detector Frequency
10
MHz
Pf
IN
RF Input Sensitivity
V
CC
= 3.0V
-15
0
dBm
V
CC
= 5.0V
-10
0
dBm
V
OSC
Oscillator Sensitivity
OSC
IN
0.5
V
CC
V
PP
CHARGE PUMP
ICP
o-source
Charge Pump Output Current
VCP
o
= Vp/2,
CP_WORD = 0000
-100
A
ICP
o-sink
VCP
o
= Vp/2,
CP_WORD = 0000
100
A
ICP
o-source
VCP
o
= Vp/2,
CP_WORD = 1111
-1.6
mA
ICP
o-sink
VCP
o
= Vp/2,
CP_WORD = 1111
1.6
mA
ICP
o-TRI
Charge Pump TRI-STATE
Current
0.5
VCP
o
Vp - 0.5,
-40C
<
T
A
<
85C
500
pA
ICP
o-sink
vs
ICP
o-source
CP Sink vs Source Mismatch
VCP
o
= Vp/2, T
A
= 25C
3
%
ICP
o
vs
VCP
o
CP Current vs Voltage
0.5
VCP
o
Vp - 0.5, T
A
= 25C
8
%
ICP
o
vs T
CP Current vs Temperature
VCP
o
= Vp/2, -40C
<
T
A
<
85C
8
%
VOLTAGE DOUBLER
V
D-ON
Voltage Doubler Turn on Time
OSC
IN
= 10 MHz, C
ext
= 0.1 F
V
P
Settled to within
10%
TBD
s
V
CPO
Charge Pump Output Voltage
2.7V
V
CC
3.3V,
Doubler Enabled
2 x V
CC
- 1.0
V
V
P DOUBLER
Doubler Voltage at V
P
Pin
2.7V
V
CC
3.3V,
Doubler Enabled
2 x V
CC
- 0.5
V
DIGITAL INTERFACE (DATA, CLK, LE, EN, F
o
LD)
V
IH
High-Level Input Voltage
(Note 4)
0.8 x
V
CC
V
V
IL
Low-Level Input Voltage
(Note 4)
0.2 x
V
CC
V
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3
Electrical Characteristics
(V
CC
= Vp = 3.0V; -40C
<
T
A
<
85C except as specified). (Continued)
Symbol
Parameter
Conditions
Value
Unit
Min
Typ
Max
DIGITAL INTERFACE (DATA, CLK, LE, EN, F
o
LD)
I
IH
High-Level Input Current
V
IH
= V
CC
= 5.5V, (Note 4)
-1.0
1.0
A
I
IL
Low-Level Input Current
V
IL
= 0, V
CC
= 5.5V, (Note 4)
-1.0
1.0
A
I
IH
Oscillator Input Current
V
IH
= V
CC
= 5.5V
100
A
I
IL
Oscillator Input Current
V
IL
= 0, V
CC
= 5.5V
-100
A
V
OH
High-Level Output Voltage
I
OH
= -500 A
V
CC
-
0.4
V
V
OL
Low-Level Output Voltage
I
OL
= 500 A
0.4
V
MICROWIRE TIMING
t
CS
Data to Clock Setup Time
See Data Input Timing
50
ns
t
CH
Data to Clock Hold Time
See Data Input Timing
10
ns
t
CWH
Clock Pulse Width High
See Data Input Timing
50
ns
t
CWL
Clock Pulse Width Low
See Data Input Timing
50
ns
t
ES
Clock to Load Enable Setup
Time
See Data Input Timing
50
ns
t
EW
Load Enable Pulse Width
See Data Input Timing
50
ns
Note 3: Minimum operating frequencies are not production tested -- only characterized.
Note 4: Except f
IN
and OSC
IN
.
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer
such as the National Semiconductor LMX2353, a voltage controlled oscillator (VCO), and a passive loop filter. The frequency syn-
thesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] fre-
quency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a fre-
quency that sets the comparison frequency. This reference signal, fr, is then presented to the input of a phase/frequency detector
and compared with another signal, fp, the feedback signal, which was obtained by dividing the VCO frequency down by way of
the N counter and fractional circuitry. The phase/frequency detector's current source outputs pump charge into the loop filter,
which then converts the charge into the VCO's control voltage. The phase/frequency comparator's function is to adjust the voltage
presented to the VCO until the feedback signal's frequency (and phase) match that of the reference signal. When this "phase-
locked" condition exists, the RF VCO's frequency will be N+F times that of the comparison frequency, where N is the integer di-
vide ratio and F is the fractional component. The fractional synthesis allows the phase detector frequency to be increased while
maintaining the same frequency step size for channel selection. The division value N is thereby reduced giving a lower phase
noise referred to the phase detector input, and the comparison frequency is increased allowing faster switching times.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for the PLL is provided by an external reference TCXO through the OSC
in
pin. OSC
in
block can
operate to 50 MHz with a minimum input sensitivity of 0.5 V
pp
. The inputs have a V
CC
/2 input threshold and can be driven from
an external CMOS or TTL logic gate.
1.2 REFERENCE DIVIDER (R-COUNTER)
The R-counter is clocked through the oscillator block. The maximum frequency is 50 MHz. The R-counter is CMOS design and
15-bit in length with programmable divider ratio from 3 to 32,767.
1.3 FEEDBACK DIVIDER (N-COUNTER)
The N counter is clocked by the small signal f
IN
input pin. The N counter is 19 bits with 15 bits integer divide and 4 bits fractional.
The integer part is configured as a 5-bit A counter and a 10-bit B counter. The LMX2353 is capable of operating from 500 MHz
to 1.2 GHz with the 16/17 prescaler offering a continuous integer divide range from 272 to 16399, and 1.2 GHz to 2.5 GHz with
the 32/33 prescaler offering a continuous integer divide range from 1056 to 32767. The fractional compensation is programmable
in either 1/15 or 1/16 modes.
1.3.1 Prescaler
The RF input to the prescaler consist of f
IN
and f
INB
; which are complimentary inputs to a differential pair amplifier. The compli-
mentary input is internally coupled to ground with a 10 pF capacitor. This input is typically AC coupled to ground through external
capacitors as well. A 16/17 or 32/33 prescaler ratio can be selected.
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4
1.0 Functional Description
(Continued)
1.3.2 Fractional Compensation
The fractional compensation circuitry in the N divider allows the user to adjust the VCO's tuning resolution in 1/16 or 1/15 incre-
ments of the phase detector comparison frequency. A 4-bit register is programmed with the fractions desired numerator, while an-
other bit selects between fractional 15 and 16 modulo base denominator. An integer average is accomplished by using a 4-bit ac-
cumulator. A variable phase delay stage compensates for the accumulated integer phase error, minimizing the charge pump duty
cycle, and reducing spurious levels. This technique eliminates the need for compensation current injection in to the loop filter.
Overflow signals generated by the accumulator are equivalent to 1 full VCO cycle, and result in a pulse swallow.
1.4 PHASE/FREQUENCY DETECTOR
The phase/frequency detector is driven from the N and R counter outputs. The maximum frequency at the phase detector input
is about 2 MHz for some high frequency VCO due to the minimum continuous divide ratio of the dual modulus prescaler. For ex-
ample, if the VCO output frequency is 1.984 GHz, the maximum phase detector input frequency is 2 MHz because the minimum
continuous divide ratio with 32/33 prescaler is 1056. The phase detector outputs control the charge pumps. The polarity of the
pump-up or pump-down control is programmed using PD_POL depending on whether the VCO characteristics are positive or
negative. The phase detector also receives a feedback signal from the charge pump, in order to eliminate dead zone.
1.5 CHARGE PUMPS
The phase detector's current source output pumps charge into an external loop filter, which then integrates into the VCO's control
voltage. The charge pump steers the charge pump output CP
o
to V
CC
(pump-up) or Ground (pump-down). When locked, CP
o
is
primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected from 100 A
to 1.6 mA by programming the CP_WORD bits.
1.6 VOLTAGE DOUBLER
The V
p
pin is normally driven from an external power supply over a range of V
CC
to 5.5V to provide current for the RF charge
pump circuit. An internal voltage doubler circuit connected between the V
CC
and V
p
supply pins alternately allows V
CC
= 3V
(
10%) users to run the RF charge pump circuit at close to twice the V
CC
power supply voltage. The Voltage doubler mode is en-
abled by setting the V2_EN bit (R[20]) to a HIGH level. The average delivery current of the doubler is less than the instantaneous
current demand of the RF charge pump when active and is thus not capable of sustaining a continuous out of lock condition. A
large external capacitor connected to V
p
(
0.1 F) is therefore needed to control power supply droop when changing frequencies.
1.7 MICROWIRE
TM
SERIAL INTERFACE
The programmable functions are accessed through the MICROWIRE serial interface. The interface is made of three functions:
clock, data and latch enable (LE). Serial data for the various counters is clocked in from data on the rising edge of clock, into the
24-bit shift register. Data is entered MSB first. The last two bits decode the internal register address. On the rising edge of LE,
data stored in the shift register is loaded into one of the 4 appropriate latches (selected by address bits). A complete programming
description is included in the following sections.
1.8 Lock Detect Output
A digital filtered lock detect function is included with each phase detector through an internal digital filter to produce a logic level
output available on the FoLD output pin if selected. The lock detect output is high when the error between the phase detector in-
puts is less than 15 ns for 5 consecutive comparison cycles. The lock detect output is low when the error between the phase de-
tector inputs is more than 30 ns for one comparison cycle. An analog lock detect status generated from the phase detector is also
available on the FoLD output pin, if selected. The lock detect output goes high when the charge pump is inactive. It goes low when
the charge pump is active during a comparison cycle. When a PLL is in power down mode, the respective lock detect output is
always low.
1.9 OUT0/OUT1 Output Modes (Fastlock & CMOS Output Modes)
The OUT_0 and OUT_1 pins are normally used as general purpose CMOS outputs or as part of a fastlock scheme. There is also
a production test mode that overrides the other two normal modes when activated. The selection of these modes is determined
by the 4 bit CMOS register (F2_1518) described in Table 2.5.3.
The fastlock mode allows the user to open up the loop bandwidth momentarily while acquiring lock by increasing the charge pump
output current magnitude while simultaneously switching in a second resistor element to ground via the OUT0 output pin. The
loop will lock faster without any additional stability considerations as the phase margin remains constant.
The loop bandwidth during fastlock can be opened up by as much as a factor of 4. The amount of bandwidth increase is a function
of the square root of the charge pump current increase. The maximum charge pump current ratio results from switching the
charge pump current between 100 A and 1.6 mA. The damping resistor ratio for these two charge pump current setting changes
by the reciprocal of the bandwidth change. In the 4 to 1 bandwidth scenerio, the resulting damping resistor value would be 1/4th
of the steady state value. This would be achieved by switching 3 more identical resistors in parallel with the first to ground through
the OUT_0 pin.
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