LMX2364
2.6 GHz PLLatinum Fractional RF Frequency Synthesizer
with 850 MHz Integer IF Frequency Synthesizer
General Description
The LMX2364 integrates a high performance 2.6 GHz frac-
tional frequency synthesizer with a 850 MHz low power
Integer-N frequency synthesizer. Designed for use in a local
oscillator subsystem of a radio transceiver, the LMX2364
generates very stable, low noise control signals for UHF and
VHF voltage controlled oscillators. It is fabricated using Na-
tional's high performance BiCMOS process.
The RF Synthesizer supports both fractional and integer
modes. The N counter contains a selectable, quadruple
modulus prescaler and can support fractional denominators
from 1 to 128. A flexible, 4 level programmable charge pump
supplies output current magnitudes ranging from 1 mA to 16
mA. Only a single word write is required to power up and
tune the synthesizer to a new frequency.
High
performance
FastLock
TM
technology
makes
the
LMX2364 an excellent choice for applications requiring ag-
gressive lock time while maintaining excellent phase noise
and spurious performance. The combination of the improved
FastLock circuitry, the enhanced fractional compensation
engine, and the programmable charge pump architecture
gives the designer maximum freedom to optimize the perfor-
mance of the synthesizer for the target application. Inte-
grated timeout counters greatly simplify the programming
aspects of FastLock. These timeout counters reduce the
demands on the microcontroller by automatically disengag-
ing FastLock after a perscribed number of reference cycles
of the phase detector.
The IF synthesizer includes a fixed 8/9 dual modulus pres-
caler, a two level programmable charge pump, and dedi-
cated FastLock circuitry with an integrated timeout counter.
The LMX2364 offers many performance enhancements over
the LMX2354. Improvements in the fractional compensation
make the spurs on the LMX2364 approximately 6 dB better
in a typical application. The higher and more flexible frac-
tional modulus combined with the higher charge pump cur-
rents result in phase noise improvements on the order of 10
dB. The cycle slip reduction circuitry of the LMX2364 is both
easy to use and effective in reducing cycle slipping and
allows one to use very high phase detector frequencies
without degrading lock times.
Serial data is transferred to the device via a three-wire
interface (DATA, LE, CLK). The low voltage logic interface
allows direct connection to 1.8 Volt and 3.0 Volt devices.
Supply voltages from 2.7V to 5.5V are supported. Indepen-
dent charge pump supplies for each synthesizer allows the
designer to optimize the bias level for the selected VCO. The
LMX2364 consumes 5.0 mA (typical) of current in integer
mode and 7.2 mA (typical) in fractional mode. The LMX2364
is available in a 24 Pin Ultra Thin CSP package and 24 Pin
TSSOP Package.
Features
n
RF Synthesizer supports both Fractional and Integer
Operating Modes
n
Pin Compatible upgrade for LMX2354
n
2.7V to 5.5V operation
n
Pin and programmable power down
n
Fractional N divider supports fractional denominators
ranging from 1 through 128
n
Supports Integer Mode Operation
n
Programmable charge pump current levels
RF: 4 level, 1 16 mA
IF: 2 level, 100/800 uA
n
FastLock Technology with integrated timeout counters
n
Digital filtered & analog lock detect output
n
FastLock Glitch Reduction Technology
n
Enhanced Low Noise Fractional Compensation Engine
n
Low voltage programming interface allows direct
connection to 1.8V logic
Applications
n
Digital Cellular
n
GPRS
n
IS-136
n
GAIT
n
PDC
n
EDGE
n
CDMA
n
Zero blind slot TDMA systems
n
Cable TV Tuners (CATV)
FastLock
TM
is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
July 2003
LMX2364
2.6
GHz
PLLatinum
Fractional
RF
Frequency
Synthesizer
with
850
MHz
Integer-N
IF
Frequency
Synthesizer
2003 National Semiconductor Corporation
DS200506
www.national.com
Pin Descriptions
Pin Number
Pin
Description
TSSOP
SLE
2
1
VccRF
RF PLL power supply voltage input. Must be equal to V
VccIF
. May range from 2.7V to
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
3
2
VcpRF
Power supply for RF charge pump. Must be
V
VccRF
and V
VccIF
.
4
3
CPoutRF
RF charge pump output.
5
4
GND
Ground for RF PLL digital circuitry.
6
5
FinRF
RF prescaler input. Small signal input from the VCO.
7
6
FinRF*
RF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
8
7
GND
Ground for RF PLL analog circuitry.
9
8
OSCinRF
RF R counter input. Has a V
CC
/2 input threshold when configured as an input and can
be driven from an external CMOS or TTL logic gate.
10
9
OSCinIF
Oscillator input which can be configured to drive both the IF and RF R counter inputs
or only the IF R counter depending on the state of the OSC programming bit.
11
10
Ftest/LD
Programmable multiplexed output pin. Can function as general purpose CMOS
TRI-STATE
I/O, analog lock detect output, digital filtered lock detect output, or N & R
divider output.
12
11
ENRF
RF PLL Enable. Powers down RF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW, regardless of the state RF_PD bit. Bringing ENRF
high powers up RF PLL depending on the state of RF_PD control bit.
13
12
ENIF
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the
charge pump output when LOW, regardless of the state IF_PD bit. Bringing ENIF high
powers up IF PLL depending on the state of IF_PD control bit.
14
13
CLK
High impedance CMOS Clock input. Data for the control registers is clocked into the
24-bit shift register on the rising edge.
15
14
DATA
Binary serial data input. Data entered MSB first. The last three bits are the control
bits. High impedance CMOS input.
16
15
LE
Latch enable. High impedance CMOS input. Data stored in the shift register is loaded
into one of the 7 internal latches when LE goes HIGH.
17
16
GND
Ground for IF analog circuitry.
18
17
FinIF*
IF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground.
19
18
FinIF
IF prescaler input. Small signal input from the VCO.
20
19
GND
Ground for IF digital circuitry.
21
20
CPoutIF
IF charge pump output.
22
21
VcpIF
Power supply for IF charge pump. Must be
V
VccRF
and V
VccIF
.
23
22
VccIF
IF power supply voltage input. Must be equal to V
VccRF
. Input may range from 2.7V to
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
24
23
FLoutIF
IF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
1
24
FLoutRF
RF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
LMX2364
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3
Absolute Maximum Ratings
(Notes 1, 2)
Parameter
Symbol
Value
Units
Min
Typ
Max
Power Supply Voltage
V
Vcc
-0.3
6.5
V
V
Vcp
-0.3
6.5
V
Voltage on any pin with GND = 0V
V
CC
-0.3
V
CC
+ 0.3
V
Storage Temperature Range
T
s
-65
+150
C
Lead Temperature (Solder 4 sec.)
T
L
+260
C
Recommended Operating Conditions
Parameter
Symbol
Value
Units
Min
Typ
Max
Power Supply Voltage
V
VccRF
2.7
5.5
V
V
VccIF
V
VccRF
V
VccRF
V
V
VcpRF
V
VccRF
5.5
V
V
VcpIF
V
CCIF
5.5
V
Operating Temperature
T
A
-40
+85
C
Note 1: "Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The
guaranteed specifications apply only for the test conditions listed.
Note 2: This Device is a high performance RF integrated circuit with an ESD rating
<
2 kV and is ESD sensitive. Handling and assembly of this device should only
be done at ESD-free workstations.
Electrical Characteristics
(V
Vcc
= V
Vcp
= 3.0V; -40C
T
A
+85C except as specified)
Symbol
Parameter
Conditions
Value
Units
Min
Typ
Max
I
CC
PARAMETERS
I
CC
RF
Power Supply Current, RF
Synthesizer, Integer Mode
V
ENIF
=V
CLK
=V
DATA
=V
LE
= LOW
V
ENRFV
= HIGH
FE = 0
5.0
6.3
mA
Power Supply Current, RF
Synthesizer, Fractional
Mode
V
ENIF
=V
CLK,
=V
DATA
=V
LE
=0 V
V
ENRF
=HIGH
FE = 1
7.2
8.0
mA
I
CC
IF
Power Supply Current, IF
Synthesizer
V
ENRF
=V
CLK
=V
DATA
=V
LE
=LOW
V
ENIF
=HIGH
2.4
3.2
mA
I
CC
IF PD
Power Down Current
V
ENRF
=V
ENIF
= LOW
V
CLK
=V
DATA
=V
LE
= LOW
5.0
20
A
RF SYNTHESIZER PARAMETERS
f
FinRF
Operating Frequency
Prescaler = 8/9/12/13
500
1200
MHz
Prescaler = 16/17/20/21
1200
2600
MHz
N
Continuous N Divider
Range, Fractional Mode
Prescaler = 8/9/12/13
40
4095
Prescaler = 16/17/20/21
80
8191
Continuous N Divider
Range, Integer Mode
Prescaler = 8/9/12/13
40
266,239
Prescaler = 16/17/20/21
80
532,479
R
R Divider Range,
Fractional Mode
1
511
R Divider Range, Integer
Mode (Note 3)
1
64,897
f
COMP
Phase Detector Frequency
15
MHz
p
FinRF
RF Input Sensitivity
V
CC
= 3.0V
-15
0
dBm
V
CC
= 5.0V
-10
0
dBm
LMX2364
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