LMX2430/LMX2433/LMX2434
PLLatinum
TM
Dual High Frequency Synthesizer for RF
Personal Communications
LMX2430
3.0 GHz/0.8 GHz
LMX2433
3.6 GHz/1.7 GHz
LMX2434
5.0 GHz/2.5 GHz
General Description
The LMX243x devices are high performance frequency syn-
thesizers with integrated dual modulus prescalers. The
LMX243x devices are designed for use as RF and IF local
oscillators for dual conversion radio transceivers.
A 32/33 or a 16/17 prescale ratio can be selected for the 5.0
GHz LMX2434 RF synthesizer. An 8/9 or a 16/17 prescale
ratio can be selected for both the LMX2430 and LMX2433
RF synthesizers. The IF circuitry contains an 8/9 or a 16/17
prescaler. Using a proprietary digital phase locked loop tech-
nique, the LMX243x devices generate very stable, low noise
control signals for RF and IF voltage controlled oscillators.
Both the RF and IF synthesizers include a two-level pro-
grammable charge pump. Both the RF and IF synthesizers
have dedicated Fastlock circuitry with integrated timeout
counters. Furthermore, only a single word write is required to
power up and tune the synthesizers to a new frequency.
Serial data is transferred to the devices via a three-wire
interface (DATA, LE, CLK). A low voltage logic interface
allows direct connection to 1.8V devices. Supply voltages
from 2.25V to 2.75V are supported . The LMX243x family
features low current consumption:
LMX2430 (3.0 GHz/ 0.8 GHz) -- 2.8 mA/ 1.4 mA, LMX2433
(3.6 GHz/ 1.7 GHz) -- 3.2 mA/ 2.0 mA, LMX2434 (5.0 GHz/
2.5 GHz) -- 4.6 mA/ 2.4 mA at 2.50V.
The LMX243x devices are available in 20-Pin TSSOP and
20-Pin UTCSP surface mount plastic packages.
Features
n
Low Current Consumption
n
2.25V to 2.75V Operation
n
Selectable Synchronous or Asynchronous Powerdown
Mode
n
Selectable Dual Modulus Prescaler:
LMX2430
RF: 8/9 or 16/17
LMX2433
RF: 8/9 or 16/17
LMX2434
RF: 16/17 or 32/33
LMX243x
IF: 8/9 or 16/17
n
Programmable Charge Pump Current Levels
RF and IF: 1 or 4 mA
n
Fastlock
TM
Technology with Integrated Timeout Counters
n
Digital Filtered Lock Detect Output
n
Analog Lock Detect Output (supports both Push-Pull
and Open Drain configurations)
n
1.8V MICROWIRE Logic Interface
n
Available in 20-Pin TSSOP and 20-Pin UTCSP
Applications
n
Mobile Handsets
(GSM, GPRS, W-CDMA, CDMA, PCS, AMPS, PDC,
DCS)
n
Cordless Handsets
(DECT, DCT)
n
Wireless Data
n
Cable TV Tuners
Thin Shrink Small Outline Package (MTC20)
Ultra Thin Chip Scale Package (SLE20A)
20053580
20053581
PLLatinum
TM
is a trademark of National Semiconductor Corporation.
May 2003
LMX2430/LMX2433/LMX2434
PLLatinum
Dual
High
Frequency
Synthesizer
for
RF
Personal
Communications
2003 National Semiconductor Corporation
DS200535
www.national.com
Connection Diagrams
Ultra Thin Chip Scale Package (SLE)
(Top View)
Thin Shrink Small Outline Package (TM)
(Top View)
20053539
20053583
Pin Descriptions
Pin No.
UTCSP
Pin No.
TSSOP
Pin Name
I/O
Description
1
2
GND
--
Ground for the IF PLL analog and digital circuits, MICROWIRE
TM
, Ftest/LD and
oscillator circuits.
2
3
FinIF
I
IF PLL prescaler input. Small signal input from the VCO.
3
4
EN
I
Chip Enable input. High Impedance CMOS input. When this pin is set HIGH,
the RF and IF PLLs are powered up. Powerdown is then controlled through the
MICROWIRE. When this pin is set LOW, the device is asynchronously powered
down and the charge pump output is forced to a high impedance state
(TRI-STATE).
4
5
CPoutIF
O
IF PLL charge pump output. The output is connected to the external loop filter,
which drives the input of the IF VCO.
5
6
ENosc
I
Oscillator Enable input. High impedance CMOS input. When this pin is set
HIGH, the oscillator buffer is always powered up, independent of the state of
the EN pin. When this pin is set LOW, the OSCout/ FLoutIF pin functions as an
IF Fastlock output, which connects a resistor in parallel to R2 of the external
loop filter.
6
7
OSCout/
FLoutIF
O
Oscillator output/ IF PLL Fastlock output. The output configuration is dependent
on the state of the ENosc pin. When ENosc is set LOW, the pin functions as an
IF Fastlock output, which connects a resistor in parallel to R2 of the external
loop filter. This configuration also functions as a general purpose CMOS
TRI-STATE output. When ENosc is set HIGH, the pin functions as an oscillator
output so that an external crystal can be used.
7
8
OSCin
I
Reference oscillator input. The input has an approximate Vcc/2 threshold and is
driven by an external AC coupled source.
8
9
Vcc
--
Power supply bias for the RF PLL digital circuits and oscillator circuits. Vcc may
range from 2.25V to 2.75V. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
9
10
Ftest/LD
O
Programmable multiplexed output. Functions as a general purpose CMOS
TRI-STATE output, N and R divider output, RF/ IF PLL push-pull analog lock
detect output, RF/ IF PLL open-drain analog lock detect output, or RF/ IF PLL
digital filtered lock detect output.
LMX2430/LMX2433/LMX2434
www.national.com
3
Pin Descriptions
(Continued)
Pin No.
UTCSP
Pin No.
TSSOP
Pin Name
I/O
Description
10
11
FLoutRF
O
RF PLL Fastlock output. This pin connects a resistor in parallel to R2 of the
external loop filter. This pin can also function as a general purpose CMOS
TRI-STATE output.
11
12
GND
--
Ground for the RF PLL digital circuits.
12
13
CPoutRF
O
RF PLL charge pump output. The output is connected to the external loop filter,
which drives the input of the RF VCO.
13
14
GND
--
Ground for the RF PLL analog circuits.
14
15
FinRF
I
RF PLL prescaler input. Small signal input from the VCO.
15
16
FinRF
*
I
RF PLL prescaler complementary input. For single ended operation, this pin
should be AC grounded through a 100 pF capacitor. The LMX243x can be
driven differentially when the AC coupled capacitor is omitted.
16
17
Vcc
--
Power supply bias for the RF PLL analog circuits. Vcc may range from 2.25V to
2.75V. Bypass capacitors should be placed as close as possible to this pin and
be connected directly to the ground plane.
17
18
LE
I
MICROWIRE Latch Enable input. High impedance CMOS input. When LE
transitions HIGH, DATA stored in the shift register is loaded into one of 6
internal control registers.
18
19
CLK
I
MICROWIRE Clock input. High impedance CMOS input. DATA is clocked into
the 24-bit shift register on the rising edge of CLK.
19
20
DATA
I
MICROWIRE Data input. High impedance CMOS input. Binary serial data. The
MSB of DATA is shifted in first. The two last bits are the control bits.
20
1
Vcc
--
Power supply bias for the IF PLL analog and digital circuits, MICROWIRE, and
Ftest/LD circuits. Vcc may range from 2.25V to 2.75V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to
the ground plane
LMX2430/LMX2433/LMX2434
www.national.com
4
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