LMX3161
Single Chip Radio Transceiver
General Description
The LMX3161 Single Chip Radio Transceiver is a monolithic,
integrated radio transceiver optimized for use in a Digital En-
hanced Cordless Telecommunications (DECT) system. It is
fabricated using National's ABiC V BiCMOS process
(f
T
= 18 GHz).
The LMX3161 contains phase locked loop (PLL), transmit
and receive functions. The 1.1 GHz PLL block is shared be-
tween transmit and receive section. The transmitter includes
a frequency doubler, and a high frequency buffer. The re-
ceiver consists of a 2.0 GHz low noise mixer, an intermediate
frequency (IF) amplifier, a high gain limiting amplifier, a fre-
quency discriminator, a received signal strength indicator
(RSSI), and an analog DC compensation loop. The PLL,
doubler, and buffers can be used to implement open loop
modulation along with an external VCO and loop filter. The
circuit features on-chip voltage regulation to allow supply
voltages ranging from 3.0V to 5.5V. Two additional voltage
regulators provide a stable supply source to external dis-
crete stages in the Tx and Rx chains.
The IF amplifier, high gain limiting amplifier, and discrimina-
tor are optimized for 110 MHz operation, with a total IF gain
of 85 dB. The single conversion receiver architecture pro-
vides a low cost, high performance solution for communica-
tions systems. The RSSI output may be used for channel
quality monitoring.
The Single Chip Radio Transceiver is available in a 48-pin
7mm X 7mm X 1.4mm PQFP surface mount plastic pack-
age.
Features
n
Single chip solution for DECT RF transceiver
n
RF sensitivity to -93 dBm; RSSI sensitivity to -100 dBm
n
Two regulated voltage outputs for discrete amplifiers
n
High gain (85 dB) intermediate frequency strip
n
Allows unregulated 3.0V5.5V supply voltage
n
Power down mode for increased current savings
n
System noise figure 6.5 dB (typ)
Applications
n
Digital Enhanced Cordless Telecommunications (DECT)
n
Personal wireless communications (PCS/PCN)
n
Wireless local area networks (WLANs)
n
Other wireless communications systems
Block Diagram
MICROWIRE
TM
is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS012815-1
PRELIMINARY
November 1999
LMX3161
Single
Chip
Radio
T
ransceiver
1999 National Semiconductor Corporation
DS012815
www.national.com
LMX3161 Pin Diagram
DS012815-2
Top View
Order Number LMX3161VBH or LMX3161VBHX
See NS Package Number VBH48A
LMX3161
www.national.com
2
LMX3161 Pin Diagram
(Continued)
Pin No.
Pin Name
I/O
Description
1
V
CC
--
Power supply for CMOS section of PLL and ESD bussing.
2
MIXER
OUT
O
IF output from the mixer.
3
V
CC
--
Power supply for mixer section.
4
GND
--
Ground.
5
RF
IN
I
RF input to the mixer.
6
GND
--
Ground.
7
Tx V
REG
--
Regulated power supply for external PA gain stage.
8
V
CC
--
Power supply for analog sections of PLL and doubler.
9
GND
--
Ground.
10
Tx
OUT
O
Frequency doubler output.
11
GND
--
Ground.
12
V
CC
--
Power supply for analog sections of PLL and doubler.
13
GND
--
Ground.
14
GND
--
Ground.
15
f
IN
I
RF Input to PLL and frequency doubler.
16
CE
I
Chip Enable. Pulling LOW powers down entire chip. Taking CE HIGH powers up the
appropriate functional blocks depending on the state of bits F6, F7, F11, and F12
programmed in F-latch. It is necessary to initialize the internal registers once, after the
power up reset. The registers' contents are kept even in power-down condition.
17
V
P
--
Power supply for charge pump.
18
D
o
O
Charge pump output. For connection to a loop filter for driving the input of an external VCO.
19
V
CC
--
Power supply for CMOS section of PLL and ESD bussing.
20
GND
--
Ground.
21
OUT 0
O
Programmable CMOS output. Refer to Function Register Programming Description section
for details.
22
Rx PD/OUT 1
I/O
Receiver power down control input or programmable CMOS output. Refer to Function
Register Programming Description section for details.
23
Tx PD/OUT 2
I/O
Transmitter power down control input or programmable CMOS output. Refer to Function
Register Programming Description section for details.
24
PLL PD
I
PLL power down control input. LOW for PLL normal operations, and HIGH for PLL power
saving.
25
CLOCK
I
MICROWIRE
TM
clock input. High impedance CMOS input with Schmitt Trigger.
26
DATA
I
MICROWIRE data input. High impedance CMOS input with Schmitt Trigger.
27
LE
I
MICROWIRE load enable input. High impedance CMOS input with Schmitt Trigger.
28
OSC
IN
I
Oscillator input. High impedance CMOS input with feedback.
29
S FIELD
I
DC compensation circuit enable. While LOW, the DC compensation circuit is enabled and
the threshold is updated through the DC compensation loop. While HIGH, the switch is
opened, and the comparator threshold is held by the external capacitor.
30
RSSI
OUT
O
Received signal strength indicator (RSSI) output.
31
THRESH
O
Threshold level to external comparator.
32
DC COMP
IN
I
Input to DC compensation circuit.
33
DISC
OUT
O
Demodulated output of discriminator.
34
GND
--
Ground.
35
V
CC
--
Power supply for the discriminator circuit.
36
QUAD
IN
I
Quadrature input for tank circuit.
37
V
CC
--
Power supply for limiter output stage.
38
GND
--
Ground.
39
V
CC
--
Power supply for limiter gain stages.
40
GND
--
Ground.
41
V
CC
--
Power supply for IF amplifier gain stages.
LMX3161
www.national.com
3
LMX3161 Pin Diagram
(Continued)
Pin No.
Pin Name
I/O
Description
42
LIM
IN
I
IF input to the limiter.
43
GND
--
Ground.
44
IF
OUT
O
IF output from IF amplifier.
45
V
CC
--
Power supply for IF amplifier output.
46
GND
--
Ground.
47
IF
IN
I
IF input to IF amplifier.
48
Rx V
REG
--
Regulated power supply for external LNA stages.
LMX3161
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4
Absolute Maximum Ratings
(Notes 1, 2)
Power Supply Voltage (V
CC
)
-0.3V to +6.5V
V
P
-0.3V to +6.5V
Voltage on Any Pin with
GND = 0V (V
I
)
-0.3V to V
CC
+0.3V
Storage Temperature Range (T
S
)
-65C to +150C
Lead Temp. (solder, 4 sec)(T
L
)
+260C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
3.0V to 5.5V
(V
P
)
V
CC
to 5.5V
Operating Temperature (T
A
)
-10C to +70C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended Operating Conditions indicate condi-
tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
tions, see the Electrical Characteristics section. The guaranteed specifica-
tions apply only for the test conditions listed.
Note 2: This device is a high performance RF integrated circuit with an ESD
rating
<
KeV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD work stations.
Electrical Characteristics
The following specifications are guaranteed for V
CC
= 3.6V and T
A
= 25C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Current Consumption
I
DD, RX
-Open-Loop Receive Mode
PLL & TX chain powered down
--
50
60
mA
I
DD, TX
-Open-Loop Transmit Mode
PLL & RX chain powered down
--
27
37
mA
I
DD, PLL
-Closed-Loop PLL Mode
RX & TX chain powered down
--
6
8
mA
I
PD
-Power Down Mode
--
--
70
A
MIXER
f
RF
= 1.89 GHz, f
IF
= 110 MHz, f
LO
= 1780 MHz (f
IN
= 890 MHz)
f
RF
RF Frequency Range
(Note 3)
1.7
--
2.0
GHz
f
IF
IF Frequency
(Note 4)
--
110
--
MHz
Z
IN
Input Impedance, RF
IN
--
15-j5
--
Z
OUT
Output Impedance, Mixer Out
--
160-j70
--
NF
Noise Figure (Single Side Band)
(Notes 5, 6)
--
10
14
dB
G
C
Conversion Gain
(Note 5)
14
17
--
dB
P
1dB
Input 1dB Compression Point
(Note 5)
-24
-20
--
dBm
OIP3
Output 3rd Order Intercept Point
(Note 5)
--
7.5
--
dBm
F
IN
-RF
Fin to RF Isolation
F
IN
=890 MHz
--
-30
--
dB
f
IN
=1780 MHz
--
-10.6
--
dB
f
IN
=2670 MHz
--
-30
--
dB
F
IN
-IF
Fin to IF Isolation
f
IN
=890 MHz
--
-30
--
dB
f
IN
=1780 MHz
--
-30
--
dB
f
IN
=2670 MHz
--
-30
--
dB
RFIF
RF to IF Isolation
P
IN
=0 to -85 dB
--
-30
--
dB
IF AMPLIFIER
f
IN
= 110 MHz
NF
Noise Figure
(Note 7)
--
8
11
dB
A
V
Gain
(Note 7)
15
24
--
dB
Z
IN
Input Impedance
--
150j120
--
Z
OUT
Output Impedance
--
190j20
--
IF LIMITER
f
IN
= 110 MHz
Sens
Limiter/Discriminator Sensitivity
BER=10
-3
--
-65
--
dBm
IF
IN
IF Limiter Input Impedance
--
100j300
--
DISCRIMINATOR
f
IN
= 110 MHz
Disc Gain
1X Mode
--
10
--
mV/
(mV/ of Phase Shift from Tank Circuit)
3X Mode
--
33
--
mV/
V
OUT
Discriminator Output Peak to Peak
1X Mode (Note 8)
80
160
--
mV
Voltage
3X Mode (Note 8)
400
580
--
mV
V
OS
Disc. Output DC Voltage
Nominal (Note 10)
1.2
1.82
V
DISC
OUT
Disc. Output Impedance
--
300
--
LMX3161
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