LP3985
Micropower, 150mA Low-Noise Ultra Low-Dropout CMOS
Voltage Regulator
General Description
The LP3985 is designed for portable and wireless applica-
tions with demanding performance and space requirements.
The LP3985 is stable with a small 1F
30% ceramic or
high-quality tantalum output capacitor. The micro SMD re-
quires the smallest possible PC board area - the total appli-
cation circuit area can be less than 2.0mm x 2.5mm, a
fraction of a 1206 case size.
The LP3985's performance is optimized for battery powered
systems to deliver ultra low noise, extremely low dropout
voltage and low quiescent current. Regulator ground current
increases only slightly in dropout, further prolonging the
battery life.
An optional external bypass capacitor reduces the output
noise without slowing down the load transient response.
Fast start-up time is achieved by utilizing an internal
power-on circuit that actively pre-charges the bypass capaci-
tor.
Power supply rejection is better than 50 dB at low frequen-
cies and starts to roll off at 1kHz. High power supply rejection
is maintained down to low input voltage levels common to
battery operated circuits.
The device is ideal for mobile phone and similar battery
powered wireless applications. It provides up to 150 mA,
from a 2.5V to 6V input. The LP3985 consumes less than
1.5A in disable mode and has fast turn-on time less than
200s.
The LP3985 is available in a 5 bump small bump micro SMD,
a 5 bump large bump micro SMD, a 5 bump thin micro SMD
and a 5 pin SOT-23 package. Performance is specified for
-40C to +125C temperature range and is available in 2.5V,
2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V. 3.1V, 3.2V, 3.3V, 4.7V,
4.8V and 5.0V output voltages. For other output voltage
options between 2.5V to 5.0V or for a dual LP3985, please
contact National Semiconductor sales office.
Key Specifications
n
2.5 to 6.0V input range
n
150mA guaranteed output
n
50dB PSRR at 1kHz
@
V
IN
= V
OUT
+ 0.2V
n
1.5A quiescent current when shut down
n
Fast Turn-On time: 200 s (typ.)
n
100mV maximum dropout with 150mA load
n
30Vrms output noise (typ) over 10Hz to 100kHz
n
-40 to +125C junction temperature range for operation
n
2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9V, 3.0V, 3.1V, 3.2V,
3.3V, 4.7V, 4.8V and 5.0V outputs standard
Features
n
Miniature 5-I/O micro SMD and SOT-23-5 package
n
Logic controlled enable
n
Stable with ceramic and high quality tantalum capacitors
n
Fast turn-on
n
Thermal shutdown and short-circuit current limit
Applications
n
CDMA cellular handsets
n
Wideband CDMA cellular handsets
n
GSM cellular handsets
n
Portable information appliances
Typical Application Circuit
10136402
Note: Pin Numbers in parenthesis indicate micro SMD package.
* Optional Noise Reduction Capacitor.
June 2003
LP3985
Micropower
,
150mA
Low-Noise
Ultra
Low-Dropout
CMOS
V
oltage
Regulator
2003 National Semiconductor Corporation
DS101364
www.national.com
Block Diagram
10136401
Pin Description
Name
* micro SMD
SOT
Function
V
EN
A1
3
Enable Input Logic, Enable High
GND
B2
2
Common Ground
V
OUT
C1
5
Output Voltage of the LDO
V
IN
C3
1
Input Voltage of the LDO
BYPASS
A3
4
Optional Bypass Capacitor for Noise
Reduction
* The pin numbering scheme for the micro SMD package was revised in April 2002 to conform to JEDEC standard. Only the pin numbers were
revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering scheme had VEN
as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and BYPASS as pin 5.
Connection Diagrams
SOT 23-5 Package (MF)
5 Bump micro SMD Package (BPA05, BLA05, TLA05)
10136407
Top View
See NS Package Number MF05A
10136470
Top View
See NS Package Number BPA05, BLA05, TLA05
LP3985
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2
Ordering Information
BP refers to 0.170mm bump size, 0.900mm height for micro SMD Package
Output
Voltage (V)
Grade
LP3985 Supplied as 250
Units, Tape and Reel
LP3985 Supplied as 3000
Units, Tape and Reel
2.5
STD
LP3985IBP-2.5
LP3985IBPX-2.5
2.6
STD
LP3985IBP-2.6
LP3985IBPX-2.6
2.7
STD
LP3985IBP-2.7
LP3985IBPX-2.7
2.8
STD
LP3985IBP-2.8
LP3985IBPX-2.8
2.85
STD
LP3985IBP-285
LP3985IBPX-285
2.9
STD
LP3985IBP-2.9
LP3985IBPX-2.9
3.0
STD
LP3985IBP-3.0
LP3985IBPX-3.0
3.1
STD
LP3985IBP-3.1
LP3985IBPX-3.1
3.2
STD
LP3985IBP-3.2
LP3985IBPX-3.2
3.3
STD
LP3985IBP-3.3
LP3985IBPX-3.3
4.7
STD
LP3985IBP-4.7
LP3985IBPX-4.7
5.0
STD
LP3985IBP-5.0
LP3985IBPX-5.0
BL refers to 0.300mm bump size, 0.995mm height for micro SMD Package
Output
Voltage (V)
Grade
LP3985 Supplied as 250
Units, Tape and Reel
LP3985 Supplied as 3000
Units, Tape and Reel
2.5
STD
LP3985IBL-2.5
LP3985IBLX-2.5
2.6
STD
LP3985IBL-2.6
LP3985IBLX-2.6
2.7
STD
LP3985IBL-2.7
LP3985IBLX-2.7
2.8
STD
LP3985IBL-2.8
LP3985IBLX-2.8
2.85
STD
LP3985IBL-285
LP3985IBLX-285
2.9
STD
LP3985IBL-2.9
LP3985IBLX-2.9
3.0
STD
LP3985IBL-3.0
LP3985IBLX-3.0
3.1
STD
LP3985IBL-3.1
LP3985IBLX-3.1
3.2
STD
LP3985IBL-3.2
LP3985IBLX-3.2
3.3
STD
LP3985IBL-3.3
LP3985IBLX-3.3
4.8
STD
LP3985IBL-4.8
LP3985IBLX-4.8
5.0
STD
LP3985IBL-5.0
LP3985IBLX-5.0
TL refers to 0.300mm bump size, 0.600mm height for micro SMD Package
Output
Voltage (V)
Grade
LP3985 Supplied as 250
Units, Tape and Reel
LP3985 Supplied as 3000
Units, Tape and Reel
2.5
STD
LP3985ITL-2.5
LP3985ITLX-2.5
2.6
STD
LP3985ITL-2.6
LP3985ITLX-2.6
2.7
STD
LP3985ITL-2.7
LP3985ITLX-2.7
2.8
STD
LP3985ITL-2.8
LP3985ITLX-2.8
2.85
STD
LP3985ITL-285
LP3985ITLX-285
2.9
STD
LP3985ITL-2.9
LP3985ITLX-2.9
3.0
STD
LP3985ITL-3.0
LP3985ITLX-3.0
3.1
STD
LP3985ITL-3.1
LP3985ITLX-3.1
3.2
STD
LP3985ITL-3.2
LP3985ITLX-3.2
3.3
STD
LP3985ITL-3.3
LP3985ITLX-3.3
4.8
STD
LP3985ITL-4.8
LP3985ITLX-4.8
5.0
STD
LP3985ITL-5.0
LP3985ITLX-5.0
LP3985
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3
Ordering Information
(Continued)
For SOT Package
Output
Voltage (V)
Grade
LP3985 Supplied as 1000
Units, Tape and Reel
LP3985 Supplied as 3000
Units, Tape and Reel
Package Marking
2.5
STD
LP3985IM5-2.5
LP3985IM5X-2.5
LCSB
2.6
STD
LP3985IM5-2.6
LP3985IM5X-2.6
LCTB
2.7
STD
LP3985IM5-2.7
LP3985IM5X-2.7
LCUB
2.8
STD
LP3985IM5-2.8
LP3985IM5X-2.8
LCJB
2.85
STD
LP3985IM5-285
LP3985IM5X-285
LCXB
2.9
STD
LP3985IM5-2.9
LP3985IM5X-2.9
LCYB
3.0
STD
LP3985IM5-3.0
LP3985IM5X-3.0
LCRB
3.1
STD
LP3985IM5-3.1
LP3985IM5X-3.1
LCZB
3.2
STD
LP3985IM5-3.2
LP3985IM5X-3.2
LDPB
3.3
STD
LP3985IM5-3.3
LP3985IM5X-3.3
LDQB
4.7
STD
LP3985IM5-4.7
LP3985IM5X-4.7
LDRB
5.0
STD
LP3985IM5-5.0
LP3985IM5X-5.0
LDSB
LP3985
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4
Absolute Maximum Ratings
(Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
IN
, V
EN
-0.3 to 6.5V
V
OUT
-0.3 to (V
IN
+0.3)
6.5V
Junction Temperature
150C
Storage Temperature
-65C to +150C
Lead Temp.
235C
Pad Temp. (Note 3)
235C
Maximum Power Dissipation
SOT23-5 (Note 4)
micro SMD (Note 4)
364mW
355mW
ESD Rating(Note 5)
Human Body Model
Machine Model
2kV
150V
Operating Ratings
(Notes 1, 2)
V
IN
2.5 to 6V
V
EN
0 to (V
IN
+0.3)
6V
Junction Temperature
-40C to +125C
Thermal Resistance
JA
(SOT23-5)
JA
(micro SMD)
220C/W
255C/W
Maximum Power Dissipation
SOT23-5 (Note 6)
micro SMD (Note 6)
250mW
244mW
Electrical Characteristics
Unless otherwise specified: V
IN
= V
OUT(nom)
+ 0.5V, C
IN
= 1 F, I
OUT
= 1mA, C
OUT
= 1 F, C
BYPASS
= 0.01F. Typical values
and limits appearing in standard typeface are for T
J
= 25C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40C to +125C. (Note 7) (Note 8)
Symbol
Parameter
Conditions
Typ
Limit
Units
Min
Max
V
OUT
Output Voltage
Tolerance
I
OUT
= 1mA
-2
-3
2
3
% of
V
OUT(nom)
Line Regulation Error
V
IN
= (V
OUT(nom)
+ 0.5V) to 6.0V,
For 4.7 to 5.0 options
For all other options
-0.19
-0.1
0.19
0.1
%/V
Load Regulation Error
(Note 9)
I
OUT
= 1 mA to 150 mA
LP3985IM5 (SOT23-5)
0.0025
0.005
%/mA
LP3985 (micro SMD)
0.0004
0.002
Output AC Line Regulation
V
IN
= V
OUT(nom)
+ 1V,
I
OUT
= 150 mA (Figure 1)
1.5
mV
P-P
PSRR
Power Supply Rejection Ratio
V
IN
= V
OUT(nom)
+ 0.2V,
f = 1 kHz,
I
OUT
= 50 mA (Figure 2)
50
dB
V
IN
= V
OUT(nom)
+ 0.2V,
f = 10 kHz,
I
OUT
= 50 mA (Figure 2)
40
I
Q
Quiescent Current
V
EN
= 1.4V, I
OUT
= 0 mA
For 4.7 to 5.0 options
For all other options
100
85
165
150
A
V
EN
= 1.4V, I
OUT
= 0 to 150 mA
For 4.7 to 5.0 options
For all other options
155
140
250
200
V
EN
= 0.4V
0.003
1.5
Dropout Voltage (Note 10)
I
OUT
= 1 mA
0.4
2
mV
I
OUT
= 50 mA
20
35
I
OUT
= 100 mA
45
70
I
OUT
= 150 mA
60
100
I
SC
Short Circuit Current Limit
Output Grounded
(Steady State)
600
mA
I
OUT(PK)
Peak Output Current
V
OUT
V
OUT(nom)
- 5%
550
300
mA
LP3985
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5
Electrical Characteristics
(Continued)
Unless otherwise specified: V
IN
= V
OUT(nom)
+ 0.5V, C
IN
= 1 F, I
OUT
= 1mA, C
OUT
= 1 F, C
BYPASS
= 0.01F. Typical values
and limits appearing in standard typeface are for T
J
= 25C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40C to +125C. (Note 7) (Note 8)
Symbol
Parameter
Conditions
Typ
Limit
Units
Min
Max
T
ON
Turn-On Time
(Note 11)
C
BYPASS
= 0.01 F
200
s
e
n
Output Noise Voltage(Note 12)
BW = 10 Hz to 100 kHz,
C
OUT
= 1F
30
Vrms
Output Noise Density
C
BP
= 0
230
nV/
I
EN
Maximum Input Current at EN
V
EN
= 0.4 and V
IN
= 6.0
1
nA
V
IL
Maximum Low Level Input
Voltage at EN
V
IN
= 2.5 to 6.0V
0.4
V
V
IH
Minimum High Level Input
Voltage at EN
V
IN
= 2.5 to 6.0V
1.4
V
C
OUT
Output Capacitor
Capacitance
1
20
F
ESR
5
500
m
TSD
Thermal Shutdown Temperature
160
C
Thermal Shutdown Hysteresis
20
C
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pin.
Note 3: Additional information on lead temperature and pad temperature can be found in National Semiconductor Application Note (AN-1112).
Note 4: The Absolute Maximum power dissipation depends on the ambient temperature and can be calculated using the formula: P
D
= (T
J
- T
A
)/
JA
,
where T
J
is the junction temperature, T
A
is the ambient temperature, and
JA
is the junction-to-ambient thermal resistance. The 364mW rating for SOT23-5
appearing under Absolute Maximum Ratings results from substituting the Absolute Maximum junction temperature, 150C, for T
J
, 70C for T
A
, and 220C/W for
JA
.
More power can be dissipated safely at ambient temperatures below 70C . Less power can be dissipated safely at ambient temperatures above 70C. The Absolute
Maximum power dissipation can be increased by 4.5mW for each degree below 70C, and it must be derated by 4.5mW for each degree above 70C.
Note 5: The human body model is 100pF discharged through 1.5k
resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each
pin.
Note 6: Like the Absolute Maximum power dissipation, the maximum power dissipation for operation depends on the ambient temperature. The 250mW rating for
SOT23-5 appearing under Operating Ratings results from substituting the maximum junction temperature for operation, 125C, for T
J
, 70C for T
A
, and 220C/W for
JA
into (Note 4) above. More power can be dissipated at ambient temperatures below 70C . Less power can be dissipated at ambient temperatures above 70C.
The maximum power dissipation for operation can be increased by 4.5mW for each degree below 70C, and it must be derated by 4.5mW for each degree above
70C.
Note 7: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with T
J
= 25C or correlated using
Statistical Quality Control (SQC) methods. All hot and cold limits are guaranteed by correlating the electrical characteristics to process and temperature variations
and applying statistical process control.
Note 8: The target output voltage, which is labeled V
OUT(nom)
, is the desired voltage option.
Note 9: An increase in the load current results in a slight decrease in the output voltage and vice versa.
Note 10: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification does not apply
for input voltages below 2.5V.
Note 11: Turn-on time is time measured between the enable input just exceeding V
IH
and the output voltage just reaching 95% of its nominal value.
Note 12: The output noise varies with output voltage option. The 30Vrms is measured with 2.5V voltage option. To calculate an approximated output noise for other
options, use the equation: (30Vrms)(X)/2.5, where X is the voltage option value.
10136408
FIGURE 1. Line Transient Input Test Signal
LP3985
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6
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
.
Output Voltage Change vs Temperature
Dropout Voltage vs Load Current
10136441
10136433
Ground Current vs Load Current
Ground Current vs V
IN
@
25C
10136440
10136435
10136409
FIGURE 2. PSRR Input Test Signal
LP3985
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7
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
. (Continued)
Ground Current vs V
IN
@
-40C
Ground Current vs V
IN
@
125C
10136437
10136439
Short Circuit Current (micro SMD)
Short Circuit Current (micro SMD)
10136445
10136446
Short Circuit Current (SOT)
Short Circuit Current (SOT)
10136447
10136448
LP3985
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8
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
. (Continued)
Short Circuit Current (SOT)
Short Circuit Current (SOT)
10136449
10136450
Short Circuit Current (micro SMD)
Short Circuit Current (micro SMD)
10136451
10136452
Output Noise Spectral Density
Ripple Rejection (V
IN
= V
OUT
+ 0.2V)
10136410
10136411
LP3985
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9
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
. (Continued)
Ripple Rejection (V
IN
= V
OUT
+ 1V)
Ripple Rejection (V
IN
= 5.0V)
10136412
10136413
Start Up Time (V
IN
= V
OUT
+ 0.2V)
Start Up Time (V
IN
= 4.2V)
10136414
10136415
Start Up Time (V
IN
= V
OUT
+ 0.2V)
Start Up Time (V
IN
= 4.2V)
10136416
10136417
LP3985
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10
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
. (Continued)
Start Up Time (V
IN
= V
OUT
+ 0.2V)
Start Up Time (V
IN
= 4.2V)
10136418
10136419
Line Transient Response
Line Transient Response
10136420
10136421
Load Transient Response (V
IN
= 3.2V)
Load Transient Response (V
IN
= 4.2V)
10136423
10136422
LP3985
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11
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
. (Continued)
Load Transient Response (V
IN
= 3.2V)
Load Transient Response (V
IN
= 4.2V)
10136424
10136425
Enable Response (V
IN
= V
OUT
+ 0.2V)
Enable Response (V
IN
= 4.2V)
10136453
10136454
Enable Response (V
IN
= V
OUT
+ 0.2V)
Enable Response (V
IN
= 4.2V)
10136455
10136456
LP3985
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12
Typical Performance Characteristics
Unless otherwise specified, C
IN
= C
OUT
= 1 F Ceramic,
C
BYPASS
= 0.01 F, V
IN
= V
OUT
+ 0.2V, T
A
= 25C, Enable pin is tied to V
IN
. (Continued)
Output Impedance (V
IN
= 4.2V)
Output Impedance (V
IN
= V
OUT
+ 0.2V)
10136465
10136466
Application Hints
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3985 requires external
capacitors for regulator stability. The LP3985 is specifically
designed for portable applications requiring minimum board
space and smallest components. These capacitors must be
correctly selected for good performance.
INPUT CAPACITOR
An input capacitance of ) 1F is required between the
LP3985 input pin and ground (the amount of the capacitance
may be increased without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR on the input capaci-
tor, but tolerance and temperature coefficient must be con-
sidered when selecting the capacitor to ensure the capaci-
tance will be ) 1F over the entire operating temperature
range.
OUTPUT CAPACITOR
The LP3985 is designed specifically to work with very small
ceramic output capacitors. A ceramic capacitor (temperature
characteristics X7R, X5R, Z5U, or Y5V) in 1 to 22 F range
with 5m
to 500m ESR range is suitable in the LP3985
application circuit.
It may also be possible to use tantalum or film capacitors at
the output, but these are not as attractive for reasons of size
and cost (see next section Capacitor Characteristics).
The output capacitor must meet the requirement for mini-
mum amount of capacitance and also have an ESR (Equiva-
lent Series Resistance) value which is within a stable range
(5 m
to 500 m).
NO-LOAD STABILITY
The LP3985 will remain stable and in regulation with no
external load. This is specially important in CMOS RAM
keep-alive applications.
CAPACITOR CHARACTERISTICS
The LP3985 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer: for
capacitance values in the range of 1F to 4.7F range,
ceramic capacitors are the smallest, least expensive and
have the lowest ESR values (which makes them best for
eliminating high frequency noise). The ESR of a typical 1F
ceramic capacitor is in the range of 20 m
to 40 m, which
easily meets the ESR requirement for stability by the
LP3985.
The ceramic capacitor's capacitance can vary with tempera-
ture. The capacitor type X7R, which operates over a tem-
perature range of -55C to +125C, will only vary the capaci-
tance to within
15%. Most large value ceramic capacitors
() 2.2F) are manufactured with Z5U or Y5V temperature
characteristics. Their capacitance can drop by more than
50% as the temperature goes from 25C to 85C. Therefore,
X7R is recommended over Z5U and Y5V in applications
where the ambient temperature will change significantly
above or below 25C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1F to 4.7F range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly ) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25C down to -40C, so some guard band must be
allowed.
NOISE BYPASS CAPACITOR
Connecting a 0.01F capacitor between the C
BYPASS
pin
and ground significantly reduces noise on the regulator out-
put. This cap is connected directly to a high impedance node
LP3985
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13
Application Hints
(Continued)
in the band gap reference circuit. Any significant loading on
this node will cause a change on the regulated output volt-
age. For this reason, DC leakage current through this pin
must be kept as low as possible for best output voltage
accuracy.
The types of capacitors best suited for the noise bypass
capacitor are ceramic and film. High-quality ceramic capaci-
tors with either NPO or COG dielectric typically have very
low leakage. Polypropolene and polycarbonate film capaci-
tors are available in small surface-mount packages and
typically have extremely low leakage current.
Unlike many other LDO's, addition of a noise reduction
capacitor does not effect the load transient response of the
device.
ON/OFF INPUT OPERATION
The LP3985 is turned off by pulling the V
EN
pin low, and
turned on by pulling it high. If this feature is not used, the V
EN
pin should be tied to V
IN
to keep the regulator output on at all
time. To assure proper operation, the signal source used to
drive the V
EN
input must be able to swing above and below
the specified turn-on/off voltage thresholds listed in the Elec-
trical Characteristics section under V
IL
and V
IH
.
FAST ON-TIME
The LP3985 output is turned on after Vref voltage reaches its
final value (1.23V nomial). To speed up this process, the
noise reduction capacitor at the bypass pin is charged with
an internal 70uA current source. The current source is turned
off when the bandgap voltage reaches approximately 95% of
its final value. The turn on time is determined by the time
constant of the bypass capacitor. The smaller the capacitor
value, the shorter the turn on time, but less noise gets
reduced. As a result, turn on time and noise reduction need
to be taken into design consideration when choosing the
value of the bypass capacitor.
micro SMD MOUNTING
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note (AN-1112). Referring to the section Surface
Mount Technology (SMT) Assembly Considerations, it
should be noted that the pad style which must be used with
the 5 pin package is NSMD (non-solder mask defined) type.
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
micro SMD LIGHT SENSITIVITY
Exposing the micro SMD device to direct sunlight will cause
misoperation of the device. Light sources such as halogen
lamps can effect electrical performance if brought near to the
device.
The wavelengths which have most detrimental effect are
reds and infra-reds, which means that the fluorescent light-
ing used inside most buildings has very little effect on per-
formance. A micro SMD test board was brought to within
1cm of a fluorescent desk lamp and the effect on the regu-
lated output voltage was negligible, showing a deviation of
less than 0.1% from nominal.
LP3985
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14
Physical Dimensions
inches (millimeters)
unless otherwise noted
5-Lead Small Outline Package (MF)
NS Package Number MF05A
micro SMD, 5 Bump, Package (BPA05)
NS Package Number BPA05CMC
The dimensions for X1, X2 and X3 are as given:
X1 = 0.828 +/- 0.03mm
X2 = 1.387 +/- 0.03mm
X3 = 0.900 +/- 0.10mm
LP3985
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15
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
micro SMD, 5 Bump, Package (BLA05)
NS Package Number BLA05ADC
The dimensions for X1, X2 and X3 are as given:
X1 = 1.006 +/- 0.03mm
X2 = 1.438 +/- 0.03mm
X3 = 0.995 +/- 0.10mm
LP3985
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16
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
thin micro SMD, 5 Bump, Package (TLA05)
NS Package Number TLA05ADA
The dimensions for X1, X2 and X3 are as given:
X1 = 1.006 +/- 0.03mm
X2 = 1.438 +/- 0.03mm
X3 = 0.6 +/- 0.075mm
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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Americas Customer
Support Center
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
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www.national.com
LP3985
Micropower
,
150mA
Low-Noise
Ultra
Low-Dropout
CMOS
V
oltage
Regulator
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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