TL H 5510

TP3054

TP3057

``Enhanced''

Serial

Interface

CODECFilter

COMBO

Family

August 1994

TP3054 TP3057
``Enhanced'' Serial Interface
CODEC Filter COMBO

Family

General Description

The TP3054 TP3057 family consists of m-law and A-law
monolithic PCM CODEC filters utilizing the A D and D A
conversion architecture shown in

Figure 1 and a serial PCM

interface The devices are fabricated using National's ad-
vanced double-poly CMOS process (microCMOS)

The encode portion of each device consists of an input gain
adjust amplifier an active RC pre-filter which eliminates very
high frequency noise prior to entering a switched-capacitor
band-pass filter that rejects signals below 200 Hz and above
3400 Hz Also included are auto-zero circuitry and a com-
panding coder which samples the filtered signal and en-
codes it in the companded m-law or A-law PCM format The
decode portion of each device consists of an expanding
decoder which reconstructs the analog signal from the
companded m-law or A-law code a low-pass filter which
corrects for the sin x x response of the decoder output and
rejects signals above 3400 Hz followed by a single-ended
power amplifier capable of driving low impedance loads
The devices require two 1 536 MHz 1 544 MHz or 2 048
MHz transmit and receive master clocks which may be
asynchronous transmit and receive bit clocks which may
vary from 64 kHz to 2 048 MHz and transmit and receive
frame sync pulses The timing of the frame sync pulses and
PCM data is compatible with both industry standard formats

Features

Complete CODEC and filtering system (COMBO)
including

Transmit high-pass and low-pass filtering
Receive low-pass filter with sin x x correction
Active RC noise filters
m

-law or A-law compatible COder and DECoder

Internal precision voltage reference
Serial I O interface
Internal auto-zero circuitry

-law 16-pin

TP3054

A-law 16-pin

TP3057

Designed for D3 D4 and CCITT applications

5V operation

Low operating power

typically 50 mW

Power-down standby mode

typically 3 mW

Automatic power-down

TTL or CMOS compatible digital interfaces

Maximizes line interface card circuit density

Dual-In-Line or surface mount packages

See also AN-370 ``Techniques for Designing with
CODEC Filter COMBO Circuits''

Connection Diagrams

Dual-In-Line Package

TL H 5510 1

Top View

Order Number TP3054J or TP3057J

See NS Package Number J16A

Order Number TP3054N or TP3057N

See NS Package Number N16A

Order Number TP3054WM or TP3057WM

See NS Package Number M16B

Plastic Chip Carriers

TL H 5510 10

Top View

Order Number TP3057V

See NS Package Number V20A

COMBO

and TRI-STATE

are registered trademarks of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M125 Printed in U S A

Block Diagram

FIGURE 1

TL H 5510 2

Pin Description

Symbol

Function

Negative power supply pin
V

e b

GNDA

Analog ground All signals are referenced
to this pin

Analog output of the receive power ampli-
fier

Positive power supply pin
V

e a

Receive frame sync pulse which enables
BCLK

to shift PCM data into D

an 8 kHz pulse train See

Figures 2 and 3

for timing details

Receive data input PCM data is shifted
into D

following the FS

leading edge

BCLK

CLKSEL The bit clock which shifts data into D

af-

ter the FS

leading edge May vary from

64 kHz to 2 048 MHz Alternatively may
be a logic input which selects either
1 536 MHz 1 544 MHz or 2 048 MHz for
master clock in synchronous mode and
BCLK

is used for both transmit and re-

ceive directions (see Table I)

MCLK

PDN

Receive

master

clock

Must

1 536 MHz 1 544 MHz or 2 048 MHz
May be asynchronous with MCLK

but

Symbol

Function

should be synchronous with MCLK

for best per-

formance When MCLK

is connected continu-

ously low MCLK

is selected for all internal tim-

ing When MCLK

is connected continuously

high the device is powered down

MCLK

Transmit master clock Must be 1 536 MHz
1 544 MHz or 2 048 MHz May be asynchronous
with MCLK

Best performance is realized from

synchronous operation

Transmit frame sync pulse input which enables
BCLK

to shift out the PCM data on D

an 8 kHz pulse train see

Figures 2 and 3 for

timing details

BCLK

The bit clock which shifts out the PCM data on
D

May vary from 64 kHz to 2 048 MHz but

must be synchronous with MCLK

The TRI-STATE

PCM data output which is en-

abled by FS

Open drain output which pulses low during the
encoder time slot

Analog output of the transmit input amplifier
Used to externally set gain

Inverting input of the transmit input amplifier

Non-inverting input of the transmit input amplifi-
er

Functional Description

POWER-UP

When power is first applied power-on reset circuitry initializ-
es the COMBO and places it into a power-down state All
non-essential circuits are deactivated and the D

and VF

outputs are put in high impedance states To power-up the
device a logical low level or clock must be applied to the
MCLK

PDN pin

and FS

and or FS

pulses must be pres-

ent Thus 2 power-down control modes are available The
first is to pull the MCLK

PDN pin high the alternative is to

hold both FS

and FS

inputs continuously low

the device

will power-down approximately 1 ms after the last FS

pulse Power-up will occur on the first FS

or FS

pulse The TRI-STATE PCM data output D

will remain in

the high impedance state until the second FS

pulse

SYNCHRONOUS OPERATION

For synchronous operation the same master clock and bit
clock should be used for both the transmit and receive di-
rections In this mode a clock must be applied to MCLK

and the MCLK

PDN pin can be used as a power-down

control A low level on MCLK

PDN powers up the device

and a high level powers down the device In either case
MCLK

will be selected as the master clock for both the

transmit and receive circuits A bit clock must also be ap-
plied to BCLK

and the BCLK

CLKSEL can be used to

select the proper internal divider for a master clock of 1 536
MHz 1 544 MHz or 2 048 MHz For 1 544 MHz operation
the device automatically compensates for the 193rd clock
pulse each frame

With a fixed level on the BCLK

CLKSEL pin BCLK

will be

selected as the bit clock for both the transmit and receive
directions Table 1 indicates the frequencies of operation
which can be selected depending on the state of BCLK

CLKSEL In this synchronous mode the bit clock BCLK

may be from 64 kHz to 2 048 MHz but must be synchro-
nous with MCLK

Each FS

pulse begins the encoding cycle and the PCM

data from the previous encode cycle is shifted out of the
enabled D

output on the positive edge of BCLK

After 8

bit clock periods the TRI-STATE D

output is returned to a

high impedance state With an FS

pulse PCM data is

latched via the D

input on the negative edge of BCLK

(or

BCLK

if running) FS

and FS

must be synchronous with

MCLK

X R

TABLE I Selection of Master Clock Frequencies

BCLK

CLKSEL

Master Clock

Frequency Selected

TP3057

TP3054

Clocked

2 048 MHz

1 536 MHz or

1 544 MHz

1 536 MHz or

2 048 MHz

1 544 MHz

2 048 MHz

1 536 MHz or

1 544 MHz

ASYNCHRONOUS OPERATION

For asynchronous operation separate transmit and receive
clocks may be applied

MCLK

and MCLK

must be

2 048 MHz for the TP3057 or 1 536 MHz 1 544 MHz for the
TP3054 and need not be synchronous For best transmis-
sion performance however MCLK

should be synchronous

with MCLK

which is easily achieved by applying only static

logic levels to the MCLK

PDN pin This will automatically

connect MCLK

to all internal MCLK

functions (see Pin

Description) For 1 544 MHz operation the device automati-
cally compensates for the 193rd clock pulse each frame
FS

starts each encoding cycle and must be synchronous

with MCLK

and BCLK

starts each decoding cycle

and must be synchronous with BCLK

BCLK

must be a

clock the logic levels shown in Table 1 are not valid in
asynchronous mode BCLK

and BCLK

may operate from

64 kHz to 2 048 MHz

SHORT FRAME SYNC OPERATION

The COMBO can utilize either a short frame sync pulse or a
long frame sync pulse Upon power initialization the device
assumes a short frame mode In this mode both frame sync
pulses FS

and FS

must be one bit clock period long

with timing relationships specified in

Figure 2 With FS

high

during a falling edge of BCLK

the next rising edge of

BCLK

enables the D

TRI-STATE output buffer which will

output the sign bit The following seven rising edges clock
out the remaining seven bits and the next falling edge dis-
ables the D

output With FS

high during a falling edge of

BCLK

(BCLK

in synchronous mode) the next falling edge

of BCLK

latches in the sign bit The following seven falling

edges latch in the seven remaining bits All four devices
may utilize the short frame sync pulse in synchronous or
asynchronous operating mode

LONG FRAME SYNC OPERATION

To use the long frame mode both the frame sync pulses
FS

and FS

must be three or more bit clock periods long

with timing relationships specified in

Figure 3 Based on the

transmit frame sync FS

the COMBO will sense whether

short or long frame sync pulses are being used For 64 kHz
operation the frame sync pulse must be kept low for a mini-
mum of 160 ns The D

TRI-STATE output buffer is enabled

with the rising edge of FS

or the rising edge of BCLK

whichever comes later and the first bit clocked out is the
sign bit The following seven BCLK

rising edges clock out

the remaining seven bits The D

output is disabled by the

falling BCLK

edge following the eighth rising edge or by

going low whichever comes later A rising edge on the

receive frame sync pulse FS

will cause the PCM data at

to be latched in on the next eight falling edges of BCLK

(BCLK

in synchronous mode) All four devices may utilize

the long frame sync pulse in synchronous or asynchronous
mode

In applications where the LSB bit is used for signalling with
FS

two bit clock periods long the decoder will interpret the

lost LSB as ``

'' to minimize noise and distortion

Functional Description

(Continued)

TRANSMIT SECTION

The transmit section input is an operational amplifier with
provision for gain adjustment using two external resistors
see

Figure 4 The low noise and wide bandwidth allow gains

in excess of 20 dB across the audio passband to be real-
ized The op amp drives a unity-gain filter consisting of RC
active pre-filter followed by an eighth order switched-ca-
pacitor bandpass filter clocked at 256 kHz The output of
this filter directly drives the encoder sample-and-hold circuit
The A D is of companding type according to m-law
(TP3054) or A-law (TP3057) coding conventions A preci-
sion voltage reference is trimmed in manufacturing to pro-
vide an input overload (t

MAX

) of nominally 2 5V peak (see

table of Transmission Characteristics) The FS

frame sync

pulse controls the sampling of the filter output and then the
successive-approximation encoding cycle begins The 8-bit
code is then loaded into a buffer and shifted out through D

at the next FS

pulse The total encoding delay will be ap-

proximately 165 ms (due to the transmit filter) plus 125 ms

(due to encoding delay) which totals 290 ms Any offset
voltage due to the filters or comparator is cancelled by sign
bit integration

RECEIVE SECTION

The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz The decoder is A-law (TP3057) or
m

-law (TP3054) and the 5th order low pass filter corrects for

the sin x x attenuation due to the 8 kHz sample hold The
filter is then followed by a 2nd order RC active post-filter
power amplifer capable of driving a 600X load to a level of
7 2 dBm The receive section is unity-gain Upon the occur-
rence of FS

the data at the D

input is clocked in on the

falling edge of the next eight BCLK

(BCLK

) periods At

the end of the decoder time slot the decoding cycle begins
and 10 ms later the decoder DAC output is updated The
total decoder delay is E 10 ms (decoder update) plus
110 ms (filter delay) plus 62 5 ms (

frame) which gives

approximately 180 ms

Absolute Maximum Ratings

If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications

to GNDA

Voltage at any Analog Input

or Output

0 3V to V

0 3V

Voltage at any Digital Input or

Output

0 3V to GNDA

0 3V

Operating Temperature Range

25 C to

125 C

Storage Temperature Range

65 C to

150 C

Lead Temperature (Soldering 10 seconds)

300 C

ESD (Human Body Model)

2000V

Latch-Up Immunity

100 mA on any Pin

Electrical Characteristics

Unless otherwise noted limits printed in BOLD characters are guaranteed for V

5 0V

5% V

e b

5 0V

5% T

0 C to 70 C by correlation with 100% electrical testing at T

25 C All other limits

are assured by correlation with other production tests and or product design and characterization All signals referenced to
GNDA Typicals specified at V

5 0V V

e b

5 0V T

25 C

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DIGITAL INTERFACE

Input Low Voltage

0 6

Input High Voltage

2 2

Output Low Voltage

3 2 mA

0 4

SIG

1 0 mA

0 4

3 2 mA Open Drain

0 4

Output High Voltage

e b

3 2 mA

2 4

SIG

e b

1 0 mA

2 4

Input Low Current

GNDA

All Digital Inputs

Input High Current

Output Current in High Impedance

GNDA

State (TRI-STATE)

ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)

Input Leakage Current

2 5V

2 5V VF

or VF

200

Input Resistance

2 5V

2 5V VF

or VF

Output Resistance

Closed Loop Unity Gain

Load Resistance

Load Capacitance

Output Dynamic Range

10 kX

2 8

Voltage Gain

to GS

5000

V V

Unity Gain Bandwidth

MHz

Offset Voltage

Common-Mode Voltage

CMRRXA

60 dB

2 5

CMRRXA

Common-Mode Rejection Ratio

DC Test

PSRRXA

Power Supply Rejection Ratio

DC Test

ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)

Output Resistance

Pin VF

Load Resistance

2 5V

600

Load Capacitance

500

VOS

Output DC Offset Voltage

200

POWER DISSIPATION (ALL DEVICES)

Power-Down Current

No Load (Note)

0 5

1 5

Power-Down Current

No Load (Note)

0 05

0 3

Power-Up Active Current

No Load

5 0

9 0

Power-Up Active Current

No Load

5 0

9 0

Note

CC0

and I

BB0

are measured after first achieving a power-up state

Timing Specifications

Unless otherwise noted limits printed in BOLD characters are guaranteed for V

5 0V

5% V

e b

5 0V

5% T

0 C to 70 C by correlation with 100% electrical testing at T

25 C All other limits are

assured by correlation with other production tests and or product design and characterization All signals referenced to GNDA
Typicals specified at V

5 0V V

e b

5 0V T

25 C All timing parameters are measured at V

2 0V and V

0 7V See Definitions and Timing Conventions section for test methods information

Symbol

Parameter

Conditions

Min

Typ

Max

Units

1 t

Frequency of Master Clocks

Depends on the Device Used and the

1 536

MHz

BCLK

CLKSEL Pin

1 544

MHz

MCLK

and MCLK

2 048

MHz

Rise Time of Master Clock

MCLK

and MCLK

Fall Time of Master Clock

MCLK

and MCLK

Period of Bit Clock

485

488

15725

Rise Time of Bit Clock

BCLK

and BCLK

Fall Time of Bit Clock

BCLK

and BCLK

WMH

Width of Master Clock High

MCLK

and MCLK

160

WML

Width of Master Clock Low

MCLK

and MCLK

160

SBFM

Set-Up Time from BCLK

High

First Bit Clock after the Leading

100

to MCLK

Falling Edge

Edge of FS

SFFM

Set-Up Time from FS

High

Long Frame Only

100

to MCLK

Falling Edge

WBH

Width of Bit Clock High

2 2V

160

WBL

Width of Bit Clock Low

0 6V

160

HBFL

Holding Time from Bit Clock

Long Frame Only

Low to Frame Sync

HBFS

Holding Time from Bit Clock

Short Frame Only

High to Frame Sync

SFB

Set-Up Time from Frame Sync

Long Frame Only

to Bit Clock Low

DBD

Delay Time from BCLK

High

Load

150 pF plus 2 LSTTL Loads

140

to Data Valid

DBTS

Delay Time to TS

Low

Load

150 pF plus 2 LSTTL Loads

140

DZC

Delay Time from BCLK

Low to

0 pF to 150 pF

165

Data Output Disabled

DZF

Delay Time to Valid Data from

0 pF to 150 pF

165

or BCLK

Whichever

Comes Later

SDB

Set-Up Time from D

Valid to

BCLK

R X

Low

HBD

Hold Time from BCLK

R X

Low to

Invalid

Set-Up Time from FS

X R

Short Frame Sync Pulse (1 Bit Clock

BCLK

X R

Low

Period Long)

Hold Time from BCLK

X R

Low

Short Frame Sync Pulse (1 Bit Clock

100

to FS

X R

Low

Period Long)

HBFl

Hold Time from 3rd Period of

Long Frame Sync Pulse (from 3 to 8 Bit

100

Bit Clock Low to Frame Sync

Clock Periods Long)

(FS

or FS

)

WFL

Minimum Width of the Frame

64k Bit s Operating Mode

160

Sync Pulse (Low Level)

Transmission Characteristics

Unless otherwise noted limits printed in BOLD characters are guaranteed for

5 0V

5% V

e b

5 0V

5% T

0 C to 70 C by correlation with 100% electrical testing at T

25 C All other

limits are assured by correlation with other production tests and or product design and characterization GNDA

0V f

1 02 kHz V

0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at V

5 0V V

e b

5 0V T

25 C

Symbol

Parameter

Conditions

Min

Typ

Max

Units

AMPLITUDE RESPONSE

Absolute Levels

Nominal 0 dBm0 Level is 4 dBm

(Definition of Nominal Gain)

(600X)
0 dBm0

1 2276

Vrms

MAX

Virtual Decision Valve Defined

Max Overload Level

Per CCITT Rec G711

TP3054 (3 17 dBm0)

2 501

TP3057 (3 14 dBm0)

2 492

Transmit Gain Absolute

25 C V

5V V

e b

Input at GS

0 dBm0 at 1020 Hz

TP3054 57

0 15

Transmit Gain Relative to G

16 Hz

50 Hz

60 Hz

200 Hz

1 8

0 1

300 Hz

3000 Hz

0 15

3300 Hz

0 35

0 05

3400 Hz

0 7

4000 Hz

4600 Hz and Up Measure

Response from 0 Hz to 4000 Hz

XAT

Absolute Transmit Gain Variation

Relative to G

0 1

with Temperature

XAV

Absolute Transmit Gain Variation

Relative to G

0 05

with Supply Voltage

XRL

Transmit Gain Variations with

Sinusoidal Test Method

Level

Reference Level

e b

10 dBm0

e b

40 dBm0 to

3 dBm0

0 2

e b

50 dBm0 to

40 dBm0

0 4

e b

55 dBm0 to

50 dBm0

1 2

Receive Gain Absolute

25 C V

5V V

e b

Input

Digital Code Sequence for

0 dBm0 Signal at 1020 Hz
TP3054 57

0 15

Receive Gain Relative to G

0 Hz to 3000 Hz

0 15

3300 Hz

0 35

0 05

3400 Hz

0 7

4000 Hz

RAT

Absolute Receive Gain Variation

Relative to G

0 1

with Temperature

RAV

Absolute Receive Gain Variation

Relative to G

0 05

with Supply Voltage

RRL

Receive Gain Variations with

Sinusoidal Test Method Reference

Level

Input PCM Code Corresponds to an
Ideally Encoded PCM Level

e b

40 dBm0 to

3 dBm0

0 2

e b

50 dBm0 to

40 dBm0

0 4

e b

55 dBm0 to

50 dBm0

1 2

Receive Output Drive Level

600X

2 5

Transmission Characteristics

(Continued) Unless otherwise noted limits printed in BOLD characters are

guaranteed for V

5 0V

5% V

e b

5 0V

5% T

0 C to 70 C by correlation with 100% electrical testing at T

25 C All other limits are assured by correlation with other production tests and or product design and characterization GNDA

0V f

1 02 kHz V

0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at V

5 0V V

e b

5 0V T

25 C

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ENVELOPE DELAY DISTORTION WITH FREQUENCY

Transmit Delay Absolute

1600 Hz

290

315

Transmit Delay Relative to D

500 Hz 600 Hz

195

220

600 Hz 800 Hz

120

145

800 Hz 1000 Hz

1000 Hz 1600 Hz

1600 Hz 2600 Hz

2600 Hz 2800 Hz

105

2800 Hz 3000 Hz

130

155

Receive Delay Absolute

1600 Hz

180

200

Receive Delay Relative to D

500 Hz 1000 Hz

1000 Hz 1600 Hz

1600 Hz 2600 Hz

2600 Hz 2800 Hz

100

125

2800 Hz 3000 Hz

145

175

NOISE

Transmit Noise C Message

TP3054

dBrnC0

Weighted

Transmit Noise P Message

TP3057

dBm0p

Weighted

Receive Noise C Message

PCM Code is Alternating Positive

Weighted

and Negative Zero

TP3054

dBrnC0

Receive Noise P Message

PCM Code Equals Positive

Weighted

Zero

TP3057

dBm0p

Noise Single Frequency

0 kHz to 100 kHz Loop Around

dBm0

Measurement VF

0 Vrms

PPSR

Positive Power Supply Rejection

e b

50 dBm0

Transmit

5 0 V

100 mVrms

0 kHz 50 kHz (Note 2)

dBC

NPSR

Negative Power Supply Rejection

e b

50 dBm0

Transmit

e b

5 0 V

100 mVrms

0 kHz 50 kHz (Note 2)

dBC

PPSR

Positive Power Supply Rejection

PCM Code Equals Positive Zero

Receive

5 0 V

100 mVrms

Measure VF

0 Hz 4000 Hz

dBC

4 kHz 25 kHz

25 kHz 50 kHz

NPSR

Negative Power Supply Rejection

PCM Code Equals Positive Zero

Receive

e b

5 0 V

100 mVrms

Measure VF

0 Hz 4000 Hz

dBC

4 kHz 25 kHz

25 kHz 50 kHz

Transmission Characteristics

(Continued) Unless otherwise noted limits printed in BOLD characters are

guaranteed for V

5 0V

5% V

e b

5 0V

5% T

0 C to 70 C by correlation with 100% electrical testing at T

25 C All other limits are assured by correlation with other production tests and or product design and characterization GNDA

0V f

1 02 kHz V

0 dBm0 transmit input amplifier connected for unity gain non-inverting Typicals specified at V

5 0V V

e b

5 0V T

25 C

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SOS

Spurious Out-of-Band Signals

Loop Around Measurement 0 dBm0

at the Channel Output

300 Hz to 3400 Hz Input PCM Code Applied
at D

4600 Hz 7600 Hz

7600 Hz 8400 Hz

8400 Hz 100 000 Hz

DISTORTION

STD

Signal to Total Distortion

Sinusoidal Test Method (Note 3)

STD

Transmit or Receive

3 0 dBm0

Level

dBC

Half-Channel

0 dBm0 to

30 dBm0

dBC

XMT

e b

40 dBm0

dBC

RCV

dBC

XMT

e b

55 dBm0

dBC

RCV

dBC

SFD

Single Frequency Distortion

Transmit

SFD

Single Frequency Distortion

Receive

IMD

Intermodulation Distortion

Loop Around Measurement

e b

4 dBm0 to

21 dBm0 Two

Frequencies in the Range
300 Hz 3400 Hz

CROSSTALK

X-R

Transmit to Receive Crosstalk

300 Hz 3400 Hz

0 dBm0 Transmit Level

Quiet PCM Code

R-X

Receive to Transmit Crosstalk

300 Hz 3400 Hz VF

Multitone

0 dBm0 Receive Level

(Note 2)

ENCODING FORMAT AT D

OUTPUT

TP3054

TP3057

m-Law

A-Law

(Includes Even Bit Inversion)

(at GS

)

e a

Full-Scale

(at GS

)

(at GS

)

e b

Full-Scale

Note 1

Measured by extrapolation from the distortion test result at

50 dBm0

Note 2

PPSR

NPSR

and CT

R-X

are measured with a

50 dBm0 activation signal applied to VF

Note 3

Devices are measured using C message weighted filter for m-Law and psophometric weighted filter for A-Law

Applications Information

POWER SUPPLIES

While the pins of the TP305X family are well protected
against electrical misuse it is recommended that the stan-
dard CMOS practice be followed ensuring that ground is
connected to the device before any other connections are
made In applications where the printed circuit board may be
plugged into a ``hot'' socket with power and clocks already
present an extra long ground pin in the connector should
be used

All ground connections to each device should meet at a
common point as close as possible to the GNDA pin This
minimizes the interaction of ground return currents flowing
through a common bus impedance 0 1 mF supply decou-
pling capacitors should be connected from this common
ground point to V

and V

as close to the device as

possible

For best performance the ground point of each CODEC
FILTER on a card should be connected to a common card
ground in star formation rather than via a ground bus

This common ground point should be decoupled to V

and

with 10 mF capacitors

RECEIVE GAIN ADJUSTMENT

For applications where a TP305X family CODEC filter re-
ceive output must drive a 600X load but a peak swing lower
than

2 5V is required the receive gain can be easily ad-

justed by inserting a matched T-pad or

-pad at the output

Table II lists the required resistor values for 600X termina-
tions As these are generally non-standard values the equa-
tions can be used to compute the attenuation of the closest
practical set of resistors It may be necessary to use un-
equal values for the R1 or R4 arms of the attenuators to
achieve a precise attenuation Generally it is tolerable to
allow a small deviation of the input impedance from nominal
while still maintaining a good return loss For example a 30
dB return loss against 600X is obtained if the output imped-
ance of the attenuator is in the range 282X to 319X (as-
suming a perfect transformer)

T-Pad Attenuator

2 a

2 b

Z1 Z2

2 b

Z1 Z2

2 b

Where N

POWER IN

POWER OUT

and

Also Z

Where Z

impedance with short circuit termination

and Z

impedance with open circuit termination

-Pad Attenuator

TL H 5510 5

Z1 Z2

2 b

2NS

Note

See Application Note 370 for further details

TP3054

TP3057

``Enhanced''

Serial

Interface

CODECFilter

COMBO

Family

Physical Dimensions

inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number TP3054N or TP3057N

NS Package Number N16A

LIFE SUPPORT POLICY

NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION As used herein

1 Life support devices or systems are devices or

2 A critical component is any component of a life

systems which (a) are intended for surgical implant

support device or system whose failure to perform can

into the body or (b) support or sustain life and whose

be reasonably expected to cause the failure of the life

failure to perform when properly used in accordance

support device or system or to affect its safety or

with instructions for use provided in the labeling can

effectiveness

be reasonably expected to result in a significant injury
to the user

National Semiconductor

Corporation

Europe

Hong Kong Ltd

Japan Ltd

1111 West Bardin Road

Fax (a49) 0-180-530 85 86

13th Floor Straight Block

Tel 81-043-299-2309

Arlington TX 76017

Email cnjwge tevm2 nsc com

Ocean Centre 5 Canton Rd

Fax 81-043-299-2408

Tel 1(800) 272-9959

Deutsch Tel (a49) 0-180-530 85 85

Tsimshatsui Kowloon

Fax 1(800) 737-7018

English

Tel (a49) 0-180-532 78 32

Hong Kong

Fran ais Tel (a49) 0-180-532 93 58

Tel (852) 2737-1600

Italiano

Tel (a49) 0-180-534 16 80

Fax (852) 2736-9960

National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TP3057WM

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: TP3057WM