TP3070, TP3071, TP3070-X
COMBO

II Programmable PCM CODEC/Filter

General Description

The TP3070 and TP3071 are second-generation combined
PCM CODEC and Filter devices optimized for digital switch-
ing applications on subscriber line and trunk cards. Using
advanced switched capacitor techniques, COMBO II com-
bines transmit bandpass and receive lowpass channel filters
with a companding PCM encoder and decoder. The devices
are A-law and µ-law selectable and employ a conventional
serial PCM interface capable of being clocked up to
4.096 MHz. A number of programmable functions may be
controlled via a serial control port.

Channel gains are programmable over a 25.4 dB range in
each direction, and a programmable filter is included to en-
able Hybrid Balancing to be adjusted to suit a wide range of
loop impedance conditions. Both transformer and active
SLIC interface circuits with real or complex termination im-
pedances can be balanced by this filter, with cancellation in
excess of 30 dB being readily achievable when measured
across the passband against standard test termination net-
works.

To enable COMBO II to interface to the SLIC control leads, a
number of programmable latches are included; each may be
configured as either an input or an output. The TP3070 pro-
vides 6 latches and the TP3071 5 latches.

Features

Complete CODEC and FILTER system including:

-- Transmit and receive PCM channel filters
-- µ-law or A-law companding encoder and decoder
-- Receive power amplifier drives 300

-- 4.096 MHz serial PCM data (max)

Programmable Functions:

-- Transmit gain: 25.4 dB range, 0.1 dB steps
-- Receive gain: 25.4 dB range, 0.1 dB steps
-- Hybrid balance cancellation filter
-- Time-slot assignment; up to 64 slots/frame
-- 2 port assignment (TP3070)
-- 6 interface latches (TP3070)
-- A or µ-law
-- Analog loopback
-- Digital loopback

Direct interface to solid-state SLICs

Simplifies transformer SLIC; single winding secondary

Standard serial control interface

80 mW operating power (typ)

1.5 mW standby power (typ)

Designed for CCITT and LSSGR applications

TTL and CMOS compatible digital interfaces

Extended temperature versions available for -40°C to
+85°C (TP3070V-X)

Note: See also AN-614, COMBO II application guide.

COMBO

and TRI-STATE

are registered trademarks of National Semiconductor Corporation.

April 1994

TP3070,

TP3071,

TP3070-X

COMBO

Programmable

PCM

CODEC/Filter

DS008635

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Pin Descriptions

(Continued)

Pin

Description

Receive Frame Sync input. Normally a pulse
or squarewave with an 8 kHz repetition rate is
applied to this input to define the start of the
receive time slot assigned to this device
(non-delayed data timing mode), or the start of
the receive frame (delayed data timing mode
using the internal time-slot assignment
counter).

BCLK

Bit clock input used to shift PCM data into and
out of the D

and D

pins. BCLK may vary

from 64 kHz to 4.096 MHz in 8 kHz
increments, and must be synchronous with
MCLK.

MCLK

Master clock input used by the switched
capacitor filters and the encoder and decoder
sequencing logic. Must be 512 kHz, 1.536
MHz, 1.544 MHz, 2.048 MHz or 4.096 MHz
and synchronous with BCLK.

The Transmit analog high-impedance input.
Voice frequency signals present on this input
are encoded as an A-law or µ-law PCM bit
stream and shifted out on the selected D

pin.

The Receive analog power amplifier output,
capable of driving load impedances as low as
300

(depending on the peak overload level

required). PCM data received on the assigned
D

pin is decoded and appears at this output

as voice frequency signals.

1 is available on the TP3070 only; D

0 is

available on all devices. These Transmit Data
TRI-STATE

outputs remain in the high

impedance state except during the assigned
transmit time slot on the assigned port, during
which the transmit PCM data byte is shifted
out on the rising edges of BCLK.

1 is available on the TP3070 only; TS

0 is

available on all devices. Normally these
open-drain outputs are floating in a high
impedance state except when a time-slot is
active on one of the D

outputs, when the

appropriate TS

output pulls low to enable a

backplane line-driver.

1 is available on the TP3070 only; D

0 is

available on all devices. These receive data
inputs are inactive except during the assigned
receive time slot of the assigned port when
the receive PCM data is shifted in on the
falling edges of BCLK.

CCLK

Control Clock input. This clock shifts serial
control information into or out from CI/O or CI
and CO when the CS input is low, depending
on the current instruction. CCLK may be
asynchronous with the other system clocks.

Pin

Description

CI/O

This is the Control Data I/O pin which is
provided on the TP3071. Serial control
information is shifted to or read from COMBO
II on this pin when CS is low. The direction of
the data is determined by the current
instruction as defined in

Table 1.

This is a separate Control Input, available only
on the TP3070. It can be connected to CO if
required.

This is a separate Control Output, available
only on the TP3070. It can be connected to CI
if required.

Chip Select input. When this pin is low, control
information can be written to or read from
COMBO II via the CI/O pin (or CI and CO).

IL5IL0

IL5 through IL0 are available on the TP3070.
IL4 through IL0 are available on the TP3071.
Each Interface Latch I/O pin may be
individually programmed as an input or an
output determined by the state of the
corresponding bit in the Latch Direction
Register (LDR). For pins configured as inputs,
the logic state sensed on each input is latched
into the Interface Latch Register (ILR)
whenever control data is written to COMBO II,
while CS is low, and the information is shifted
out on the CO (or CI/O) pin. When configured
as outputs, control data written into the ILR
appears at the corresponding IL pins.

This logic input must be pulled low for normal
operation of COMBO II. When pulled
momentarily high (at least 1 µsec.), all
programmable registers in the device are reset
to the states specified under "Power-On
Initialization".

No Connection. Do not connect to this pin. Do
not route traces through this pin.

Functional Description

POWER-ON INITIALIZATION

When power is first applied, power-on reset circuitry initial-
izes the COMBO II and puts it into the power-down state.
The gain control registers for the transmit and receive gain
sections are programmed to OFF (00000000), the hybrid
balance circuit is turned off, the power amp is disabled and
the device is in the non-delayed timing mode. The Latch Di-
rection Register (LDR) is pre-set with all IL pins programmed
as inputs, placing the SLIC interface pins in a high imped-
ance state. The CI/O pin is set as an input ready for the first
control byte of the initialization sequence. Other initial states
in the Control Register are indicated in Section 2.0.

A reset to these same initial conditions may also be forced by
driving the MR pin momentarily high. This may be done ei-
ther when powered-up or down. For normal operation this
pin must be pulled low. If not used, MR should be hard-wired
to ground.

The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.

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Functional Description

(Continued)

POWER-DOWN STATE

Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the "P" bit
set to "1" as indicated in

Table 1. It is recommended that the

chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the D

0 (and D

1) outputs are in the high

impedance TRI-STATE condition.

The coefficients stored in the Hybrid Balance circuit and the
Gain Control registers, the data in the LDR and ILR, and all
control bits remain unchanged in the power-down state un-
less changed by writing new data via the serial control port,
which remains active. The outputs of the Interface Latches
also remain active, maintaining the ability to monitor and
control the SLIC.

TRANSMIT FILTER AND ENCODER

The Transmit section input, VF

I, is a high impedance sum-

ming input which is used as the differencing point for the in-
ternal hybrid balance cancellation signal. No external com-
ponents are necessary to set the gain. Following this circuit
is a programmable gain/attenuation amplifier which is con-
trolled by the contents of the Transmit Gain Register (see
Programmable Functions section). An active pre-filter then
precedes the 3rd order high-pass and 5th order low-pass
switched capacitor filters. The A/D converter has a com-
pressing characteristic according to the standard CCITT A or
µ255 coding laws, which must be selected by a control in-
struction during initialization (see

Table 1 and Table 2). A pre-

cision on-chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage arising in the
gain-set amplifier, the filters or the comparator is canceled by
an internal auto-zero circuit.

Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 µs (due to
the Transmit Filter) plus 125 µs (due to encoding delay),
which totals 290 µs. Data is shifted out on D

0 or D

1 during

the selected time slot on eight rising edges of BCLK.

DECODER AND RECEIVE FILTER

PCM data is shifted into the Decoder's Receive PCM Regis-
ter via the D

0 or D

1 pin during the selected time-slot on

the 8 falling edges of BCLK. The Decoder consists of an ex-
panding DAC with either A or µ255 law decoding character-
istic, which is selected by the same control instruction used
to select the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor filter with
integral Sin x/x correction for the 8 kHz sample and hold. A
programmable gain amplifier, which must be set by writing to
the Receive Gain Register, is included, and finally a Power
Amplifier capable of driving a 300

load to

3.5V, a 600

load to

3.8V or a 15 k

load to

4.0V at peak overload.

A decode cycle begins immediately after the assigned re-
ceive time-slot, and 10 µs later the Decoder DAC output is
updated. The total signal delay is 10 µs plus 120 µs (filter de-
lay) plus 62.5 µs (

frame) which gives approximately 190

µs.

PCM INTERFACE

The FS

and FS

frame sync inputs determine the begin-

ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see

Table 2). Non-delayed data mode is

similar to long-frame timing on the TP3050/60 series of de-
vices (COMBO); time-slots begin nominally coincident with
the rising edge of the appropriate FS input. The alternative is
to use Delayed Data mode, which is similar to short-frame
sync timing on COMBO, in which each FS input must be high
at least a half-cycle of BCLK earlier than the time-slot. The
Time-Slot Assignment circuit on the device can only be used
with Delayed Data timing.

When using Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate FS input.
The actual transmit and receive time-slots are then deter-
mined by the internal Time-Slot Assignment counters.

Transmit and Receive frames and time-slots may be skewed
from each other by any number of BCLK cycles. During each
assigned Transmit time-slot, the selected D

0/1 output shifts

data out from the PCM register on the rising edges of BCLK.
TS

0 (or TS

1 as appropriate) also pulls low for the first 7

bit times of the time-slot to control the TRI-STATE Enable of
a backplane line-driver. Serial PCM data is shifted into the
selected D

0/1 input during each assigned Receive time-slot

on the falling edges of BCLK. D

0 or D

1 and D

0 or D

are selectable on the TP3070 only, see Section 6.

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Functional Description

(Continued)

TABLE 1. Programmable Register Instructions

Function

Byte 1 (Note 1)

Byte 2 (Note 1)

Single Byte Power-Up/Down

None

Write Control Register

See

Table 2

Read-Back Control Register

See

Table 2

Write to Interface Latch Register

See

Table 4

Read Interface Latch Register

See

Table 4

Write Latch Direction Register

See

Table 3

Read Latch Direction Register

See

Table 3

Write Receive Gain Register

See

Table 8

Read Receive Gain Register

See

Table 8

Write Transmit Gain Register

See

Table 7

Read Transmit Gain Register

See

Table 7

Write Receive Time-Slot/Port

See

Table 6

Read-Back Receive Time-Slot/Port

See

Table 6

Write Transmit Time-Slot/Port

See

Table 6

Read-Back Transmit Time-Slot/Port

See

Table 6

Write Hybrid Balance Register 1

Derive from

Optimization

Routine in

TP3077SW

Program

Read Hybrid Balance Register 1

Write Hybrid Balance Register 2

Read Hybrid Balance Register 2

Write Hybrid Balance Register 3

Read Hybrid Balance Register 3

Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI, CO or CI/O pin. X = don't care.

Note 2: "P" is the power-up/down control bit, see "Power-Up/Down Control" section. ("0" = Power Up, "1" = Power Down)

Note 3: Other register address codes are invalid and should not be used.

SERIAL CONTROL PORT

Control information and data are written into or read-back
from COMBO II via the serial control port consisting of the
control clock CCLK, the serial data input/output CI/O, (or
separate input, CI, and output, CO, on the TP3070 only), and
the Chip Select input, CS. All control instructions require 2
bytes, as listed in

Table 1, with the exception of a single byte

power-up/down command. The byte 1 bits are used as fol-
lows: bit 7 specifies power up or power down; bits 6, 5, 4 and
3 specify the register address; bit 2 specifies whether the in-
struction is read or write; bit 1 specifies a one or two byte in-
struction; and bit 0 is not used.

To shift control data into COMBO II, CCLK must be pulsed 8
times while CS is low. Data on the CI/O (or CI) input is
shifted into the serial input register on the falling edge of
each CCLK pulse. After all data is shifted in, the contents of
the input shift register are decoded, and may indicate that a
2nd byte of control data will follow. This second byte may ei-
ther be defined by a second byte-wide CS pulse or may fol-
low the first contiguously, i.e. it is not mandatory for CS to re-
turn high between the first and second control bytes. At the
end of CCLK8 in the 2nd control byte the data is loaded into
the appropriate programmable register. CS may remain low
continuously when programming successive registers, if de-
sired. However, CS should be set high when no data trans-
fers are in progress.

To readback Interface Latch data or status information from
COMBO II, the first byte of the appropriate instruction is

strobed in while CS is low, as defined in

Table 1. CS must be

kept low, or be taken low again for a further 8 CCLK cycles,
during which the data is shifted onto the CO or CI/O pin on
the rising edges of CCLK. When CS is high the CO or CI/O
pin is in the high-impedance TRI-STATE, enabling the CI/O
pins of many devices to be multiplexed together.

If CS returns high during either byte 1 or byte 2 before all
eight CCLK pulses of that byte occur, both the bit count and
byte count are reset and register contents are not affected.
This prevents loss of synchronization in the control interface
as well as corruption of register data due to processor inter-
rupt or other problem. When CS returns low again, the de-
vice will be ready to accept bit 1 of byte 1 of a new instruc-
tion.

Programmable Functions

1.0 POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and power-down
control may be accomplished by writing any of the control in-
structions listed in

Table 1 into COMBO II with the "P" bit set

to "0" for power-up or "1" for power-down. Normally it is rec-
ommended that all programmable functions be initially pro-
grammed while the device is powered down. Power state
control can then be included with the last programming in-
struction or the separate single-byte instruction. Any of the
programmable registers may also be modified while the de-

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