TP3076
COMBO
II Programmable PCM CODEC/Filter for ISDN
and Digital Phone Applications
General Description
The TP3076 is a second-generation combined PCM CODEC
and Filter devices optimized for digital switching applications
on subscriber line and trunk cards and digital phone appli-
cations. Using advanced switched capacitor techniques,
COMBO II combines transmit bandpass and receive low-
pass channel filters with a companding PCM encoder and
decoder. The devices are A-law and -law selectable and
employ a conventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programmable func-
tions may be controlled via a serial control port.
Channel gains are programmable over a 25.4 dB range in
each direction.
To enable COMBO II to interface to the SLIC control leads, a
number of programmable latches are included; each may be
configured as either an input or an output. The TP3076
provides 4 latches.
Features
n
Complete CODEC and Filter system including:
-- Transmit and receive PCM channel filters
-- -law or A-law companding coder and decoder
-- Receive power amplifier drives 300
-- 4.096 MHz serial PCM data (max)
n
Programmable functions:
-- Transmit gain: 25.4 dB range, 0.1 dB steps
-- Receive gain: 25.4 dB range, 0.1 dB steps
-- Time-slot assignment; to 64 slots/frame
-- 4 interface latches
-- A or -law
-- Analog loopback
-- Digital loopback
n
Direct interface to solid-state SLICs
n
Standard serial control interface
n
80 mW operating power (typ)
n
1.5 mW standby power (typ)
n
Designed for CCITT and LSSGR specifications
n
TTL and CMOS compatible digital interfaces
Note: See also AN-614 COMBO II application guide.
Block Diagram
00975801
TRI-STATE
and COMBO
are registered trademarks of National Semiconductor Corporation.
MICROWIRE/PLUS
TM
is a trademark of National Semiconductor Corporation.
February 2003
TP3076
COMBO
II
Programmable
PCM
CODEC/Filter
for
ISDN
and
Digital
Phone
Applications
2003 National Semiconductor Corporation
DS009758
www.national.com
Connection Diagram
00975804
Order Number TP3076N-G
See NS Package Number N20A
Pin Descriptions
Pin
Description
V
CC
+5V
5% power supply.
V
BB
-5V
5% power supply.
GND
Ground. All analog and digital signals are referenced to this pin.
FS
X
Transmit Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied
to this input to define the start of the transmit time slot assigned to this device (non-delayed data
timing mode), or the start of the transmit frame (delayed data timing mode using the internal time-slot
assignment counter).
FS
R
Receive Frame Sync input. Normally a pulse or squarewave with an 8 kHz repetition rate is applied to
this input to define the start of the receive time slot assigned to this device (non-delayed data timing
mode), or the start of the receive frame (delayed data timing mode using the internal time-slot
assignment counter).
BCLK
Bit clock input used to shift PCM data into and out of the D
R
and D
X
pins. BCLK may vary from 64
kHz to 4.096 MHz in 8 kHz increments, and must be synchronous with MCLK.
MCLK
Master clock input used by the switched capacitor filters and the encoder and decoder sequencing
logic. Must be 512 kHz, 1.536/1.544 MHz, 2.048 MHz or 4.096 MHz and synchronous with BCLK.
VF
X
I
The Transmit analog high-impedance input. Voice frequency signals present on this input are
encoded as an A-law or -law PCM bit stream and shifted out on the selected D
X
pin.
VF
R
O
The Receive analog power amplifier output, capable of driving load impedances as low as 300
(depending on the peak overload level required). PCM data received on the assigned D
R
pin is
decoded and appears at this output as voice frequency signals.
D
X
1
This transmit data TRI-STATE
output remains in the high impedance state except during the
assigned transmit time slot on the assigned port, during which the transmit PCM data byte is shifted
out on the rising edges of BCLK.
TS
X
1
Normally this open drain output is floating in a high impedance state except when a time-slot is active
on the D
X
output, when the TS
X
1 output pulls low to enable a backplane line-driver.
D
R
1
This receive data input is inactive except during the assigned receive time slot of the assigned port
when the receive PCM data is shifted in on the falling edges of BCLK.
CCLK
Control Clock input. This clock shifts serial control information into CI or out from CO when the CS
input is low, depending on the current instruction. CCLK may be asynchronous with the other system
clocks.
CI
Control Data Input pin. Serial control information is shifted into COMBO II on this pin when CS is low.
Byte 1 of control information is always written into COMBO II, while the direction of byte 2 data is
determined by bit 2 of byte 1, as defined in Table 1
CO
Control Data Output pin. Serial control or status information is shifted out of COMBO II on this pin
when CS is low.
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2
Pin Descriptions
(Continued)
Pin
Description
CS
Chip Select input. When this pin is low, control information can be written to or read from COMBO II
via CI or CO.
IL3IL0
Each Interface Latch I/O pin may be individually programmed as an input or an output determined by
the state of the corresponding bit in the Latch Direction Register (LDR). For pins configured as inputs,
the logic state sensed on each input is latched into the Interface Latch Register (ILR) whenever
control data is written to COMBO II, while CS is low, and the information is shifted out on the CO pin.
When configured as outputs, control data written into the ILR appears at the corresponding IL pins.
Functional Description
POWER-ON INITIALIZATION
When power is first applied, power-on reset circuitry initial-
izes the COMBO II and puts it into the power-down state.
The gain control registers for the transmit and receive gain
sections are programmed for no output, the power amp is
disabled and the device is in the non-delayed timing mode.
The Latch Direction Register (LDR) is pre-set with all IL pins
programmed as inputs, placing the SLIC interface pins in a
high impedance state. The CO pin is in TRI-STATE condi-
tion. Other initial states in the Control Register are indicated
in Section 2.0.
The desired modes for all programmable functions may be
initialized via the control port prior to a Power-up command.
POWER-DOWN STATE
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the "P" bit
set to "1" as indicated in Table 1. It is recommended that the
chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the D
X
1 output is in the high impedance
TRI-STATE condition.
The data stored in the Gain Control registers, the LDR and
ILR, and all control bits remain unchanged in the power-
down state unless changed by writing new data via the serial
control port, which remains active. The outputs of the Inter-
face Latches also remain active, maintaining the ability to
monitor and control the SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF
X
I, is a high impedance input.
No external components are necessary to set the gain.
Following this is a programmable gain/attenuation amplifier
which is controlled by the contents of the Transmit Gain
Register (see Programmable Functions section). An active
pre-filter then precedes the 3rd order high-pass and 5th
order low-pass switched capacitor filters. The A/D converter
has a compressing characteristic according to the standard
CCITT A or 255 coding laws, which must be selected by a
control instruction during initialization (see Table 1 and Table
2). A precision on-chip voltage reference ensures accurate
and highly stable transmission levels. Any offset voltage
arising in the gain-set amplifier, the filters or the comparator
is canceled by an internal auto-zero circuit.
Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 s (due to
the Transmit Filter) plus 125 s (due to encoding delay),
which totals 290 s. Data is shifted out on D
X
1 during the
selected time slot on eight rising edges of BCLK.
DECODER AND RECEIVER FILTER
PCM data is shifted into the Decoder's Receive PCM Reg-
ister via the D
R
1 pin during the selected time-slot on the 8
falling edges of BCLK. The Decoder consists of an expand-
ing DAC with either A or 255 law decoding characteristic,
which is selected by the same control instruction used to
select the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor filter with
integral Sin x/x correction for the 8 kHz sample and hold. A
programmable gain amplifier, which must be set by writing to
the Receive Gain Register, is included, and finally a Power
Amplifier capable of driving a 300
load to
3.5V, a 600
load to
3.8V or a 15 k
load to
4.0V at peak overload.
TABLE 1. Programmable Register Instructions
Function
Byte 1 (Notes 1, 2, 3)
Byte 2 (Note 1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Single Byte Power-Up/Down
P
X
X
X
X
X
0
X
None
Write Control Register
P
0
0
0
0
0
1
X
See Table 2
Read-Back Control Register
P
0
0
0
0
1
1
X
See Table 2
Write to Interface Latch Register
P
0
0
0
1
0
1
X
See Table 4
Read Interface Latch Register
P
0
0
0
1
1
1
X
See Table 4
Write Latch Direction Register
P
0
0
1
0
0
1
X
See Table 3
Read Latch Direction Register
P
0
0
1
0
1
1
X
See Table 3
Write Receive Gain Register
P
0
1
0
0
0
1
X
See Table 8
Read Receive Gain Register
P
0
1
0
0
1
1
X
See Table 8
TP3076
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3
Functional Description
(Continued)
TABLE 1. Programmable Register Instructions (Continued)
Function
Byte 1 (Notes 1, 2, 3)
Byte 2 (Note 1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Write Transmit Gain Register
P
0
1
0
1
0
1
X
See Table 7
Read Transmit Gain Register
P
0
1
0
1
1
1
X
See Table 7
Write Receive Time-Slot/Port
P
1
0
0
1
0
1
X
See Table 6
Read-Back Receive Time-Slot/Port
P
1
0
0
1
1
1
X
See Table 6
Write Transmit Time-Slot/Port
P
1
0
1
0
0
1
X
See Table 6
Read-Back Transmit Time-Slot/Port
P
1
0
1
0
1
1
X
See Table 6
Note 1: Bit 7 of bytes 1 and 2 is always the first bit clocked into or out from the CI or CO pin. X = don't care.
Note 2: "P" is the power-up/down control bit, see Power-up/Down Control section. ("0" = Power Up, "1" = Power Down)
Note 3: Other register address codes are invalid and should not be used.
A decode cycle begins immediately after the assigned re-
ceive timeslot, and 10 s later the Decoder DAC output is
updated. The total signal delay is 10 s plus 120 s (filter
delay) plus 62.5 s (
1
/
2
frame) which gives approximately
190 s.
PCM INTERFACE
The FS
X
and FS
R
frame sync inputs determine the begin-
ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see Table 2). Non-delayed data mode is
similar to long-frame timing on the TP3050/60 series of
devices (COMBO); time-slots begin nominally coincident
with the rising edge of the appropriate FS input. The alter-
native is to use Delayed Data mode, which is similar to
shortframe sync timing on COMBO, in which each FS input
must be high at least a half-cycle of BCLK earlier than the
timeslot. The Time-Slot Assignment circuit on the device can
only be used with Delayed Data timing.
When using Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate FS input.
The actual transmit and receive time-slots are then deter-
mined by the internal Time-Slot Assignment counters.
Transmit and Receive frames and time-slots may be skewed
from each other by any number of BCLK cycles. During each
assigned Transmit time-slot, the D
X
1 output shifts data out
from the PCM register on the rising edges of BCLK. TS
X
1
also pulls low for the first 7
1
/
2
bit times of the time-slot to
control the TRI-STATE Enable of a backplane line-driver.
Serial PCM data is shifted into the D
R
1 input during each
assigned Receive time-slot on the falling edges of BCLK.
SERIAL CONTROL PORT
Control information and data are written into or read-back
from COMBO II via the serial control port consisting of the
control clock CCLK, the serial data input, CI, and output, CO,
and the Chip Select input, CS. All control instructions require
2 bytes, as listed Table 1, with the exception of a single byte
power-up/down command. The Byte 1 bits are used as
follows: bit 7 specifies power up or power down; bits 6, 5, 4
and 3 specify the register address, bit 2 specifies whether
the instruction is read or write; bit 1 specifies a one or two
byte instruction; and bit 0 is not used.
To shift control data into COMBO II, CCLK must be pulsed
high 8 times while CS is low. Data on the CI input is shifted
into the serial input register on the falling edge of each CCLK
pulse. After all data is shifted in, the contents of the input
shift register are decoded, and may indicate that a 2nd byte
of control data will follow. This second byte may either be
defined by a second byte-wide CS pulse or may follow the
first contiguously, i.e, it is not mandatory for CS to return high
between the first and second control bytes. At the end of
CCLK8 in the 2nd control byte the data is loaded into the
appropriate programmable register. CS may remain low con-
tinuously when programming successive registers, if de-
sired. However, CS must be set high when no data transfers
are in progress.
To readback Interface Latch data or status information from
COMBO II, the first byte of the appropriate instruction is
strobed while CS is low, as defined in Table 1. CS must be
kept low, or be taken low again for a further 8 CCLK cycles,
during which the data is shifted onto the CO pin on the rising
edges of CCLK. When CS is high the CO pin is in the
high-impedance TRI-STATE, enabling the CI and CO pins of
many devices to be multiplexed together.
If CS returns high during either byte 1 or byte 2 before all
eight CCLK pulses of that byte occur, both the bit count and
byte count are reset and register contents are not affected.
This prevents loss of synchronization in the control interface
as well as corruption of register data due to processor inter-
rupt or other problem. When CS returns low again, the
device will be ready to accept bit 1 of byte 1 of a new
instruction.
Programmable Functions
POWER-UP/DOWN CONTROL
Following power-on initialization, power-up and power-down
control may be accomplished by writing any of the control
instructions listed in Table 1 into COMBO II with the "P" bit
set to "0" for power-up or "1" for power-down. Normally it is
recommended that all programmable functions be initially
programmed while the device is powered down. Power state
control can then be included with the last programming
instruction or the separate single-byte instruction. Any of the
programmable registers may also be modified while the
device is powered-up or down by setting the "P" bit as
indicated. When the power-up or down control is entered as
a single byte instruction, bit one (1) must be reset to a 0.
When a power-up command is given, all de-activated circuits
are activated, but the TRI-STATE PCM output(s), D
X
1 will
remain in the high impedance state until the second FS
X
pulse after power-up.
TP3076
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4
Programmable Functions
(Continued)
CONTROL REGISTER INSTRUCTION
The first byte of a READ or WRITE instruction to the Control
Register is as shown in Table 1. The second byte has the
following bit functions:
TABLE 2. Control Register Byte 2 Functions
Bit Number and Name
7
6
5
4
3
2
1
0
Function
F
1
F
0
MA IA DN DL AL PP
0
0
MCLK = 512 kHz
0
1
MCLK = 1.536 MHz
or 1.544 MHz
1
0
MCLK = 2.048 MHz
(Note 4)
1
1
MCLK = 4.096 MHz
0
X
Select 255 Law
(Note 4)
1
0
A-Law, Including
Even Bit
Inversion
1
1
A-Law, No Even Bit
Inversion
0
Delay Data Timing
1
Non-Delayed
Data Timing (Note
4)
0
0
Normal Operation
(Note 4)
1
X
Digital Loopback
0
1
Analog Loopback
0
Power Amp
Enabled in PDN
1
Power Amp
Disabled in PDN
(Note 4)
Note 4: state at power-on initialization.
Master Clock Frequency Selection
A Master clock must be provided to COMBO II for operation
of the filter and coding/decoding functions. The MCLK fre-
quency must be either 512 kHz, 1.536 MHz, 1.544 MHz,
2.048 MHz, or 4.096 MHz and must be synchronous with
BCLK. Bits F
1
and F
0
(see Table 2) must be set during
initialization to select the correct internal divider.
Coding Law Selection
Bits "MA" and "IA" in Table 2 permit the selection of 255
coding or A-law coding, with or without even bit inversion.
Analog Loopback
Analog Loopback mode is entered by setting the "AL" and
"DL" bits in the Control Register as shown in Table 2. In the
analog loopback mode, the Transmit input VF
X
I is isolated
from the input pin and internally connected to the VF
R
O
output, forming a loop from the Receive PCM Register back
to the Transmit PCM Register. The VF
R
O pin remains active,
and the programmed settings of the Transmit and Receive
gains remain unchanged, thus care must be taken to ensure
that overload levels are not exceeded anywhere in the loop.
Digital Loopback
Digital Loopback mode is entered by setting the "AL" and
"DL" bits in the Control Register as shown in Table 2. This
mode provides another stage of path verification by enabling
data written into the Receive PCM Register to be read back
from that register in any Transmit time-slot at D
X
1. PCM
decoding continues and analog output appears at VF
R
0. The
output can be disabled by programming `No Output' in the
Receive Gain Register (see Table 8).
INTERFACE LATCH DIRECTIONS
Immediately following power-on, all Interface Latches as-
sume they are inputs, and therefore all IL pins are in a high
impedance state. Each IL pin may be individually pro-
grammed as a logic input or output by writing the appropriate
instruction to the LDR, see Table 1 and Table 3. For mini-
mum power dissipation, unconnected latch pins should be
programmed as outputs. For the TP3076, bits 2 and 3 should
always be programmed as "1" (outputs).
Bits L
3
L
0
must be set by writing the specific instruction to
the LDR with the L bits in the second byte set as follows:
TABLE 3. Byte 2 Functions of Latch Direction Register
Byte 2 Bit Number
7
6
5
4
3
2
1
0
L
0
L
1
L
2
L
3
1
1
X
X
L
n
Bit
IL Direction
0
Input
1
Output
X = Don't Care
INTERFACE LATCH STATES
Interface Latches configured as outputs assume the state
determined by the appropriate data bit in the 2-byte instruc-
tion written to the Interface Latch Register (ILR) as shown in
Table 1 and Table 4. Latches configured as inputs will sense
the state applied by an external source, such as the Off-
Hook detect output of a SLIC. All bits of the ILR, i.e. sensed
inputs and the programmed state of outputs, can be read
back in the 2nd byte of a READ from the ILR.
It is recommended that during initialization, the state of IL
pins to be configured as outputs should be programmed first
followed immediately by the Latch Direction Register.
TABLE 4. Interface Latch Data Bit Order
Bit Number
7
6
5
4
3
2
1
0
D
0
D
1
D
2
D
3
D
4
D
5
X
X
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