TP3420A
ISDN S/T Interface Device
General Description
The TP3420A is an enhanced version of the TP3420, with a
number of upgraded features for compliance with the new
release of ANSI T1.605-1991 and CCITT I-430. At initial
power-up the device is fully backwards compatible with the
TP3420 device, and modifications to the firmware are only
required to take advantage of the new features.
The TP3420A S Interface Device (SID
TM
) is a complete
monolithic transceiver for data transmission on twisted pair
subscriber loops. It is built on National's advanced 1.0 mi-
cron double-metal CMOS process, and requires only a
single +5V supply. All functions specified in CCITT recom-
mendation I.430 (1991) and ANSI T1.605 (1991) for ISDN
basic access at the "S" and "T" interfaces are provided, and
the device can be configured to operate either in a TE (Ter-
minal Equipment), in an NT-1 or NT-2 (Network Termination)
or as a PABX line-card or trunk-card device.
As specified in I.430, full-duplex transmission at 192 kb/s is
provided on separate transmit and receive twisted wire pairs
using inverted Alternate Mark Inversion (AMI) line coding. 2
"B" channels, each of 64 kb/s, and 1 "D" channel at 16 kb/s
are available for users' data. In addition, the TP3420A pro-
vides the 800 b/s "S1", "S2" & "Q" multiframe channels for
Layer 1 maintenance.
All I.430 wiring configurations are supported by the TP3420A
SID, including the "passive bus" for up to 8 TE's distributed
within
200
meters
of
low
capacitance
cable,
and
point-to-point and point-to-star connections up to at least
1500 meters (24AWG). Adaptive receive signal processing
ensures low bit error rates on any of the standard types of
cable pairs commonly found in premise wiring installations
when tested with the noise sources specified in I.430.
Features
n
2 B + D 4-wire 192 kb/s transceiver
n
Selectable TE or NT mode
n
Exceeds I.430 range: 1.5 km point-to-point
n
Adaptive receiver for high noise immunity
n
Adaptive and fixed timing options for NT-1
n
Clock resynchronizer and elastic buffers for NT-2/LT
n
Slave-slave mode for NT-2 trunks
n
Extensive hardware support for SC1, SC2 and Q
channel messaging
n
Bipolar violation detection and FECV messaging
n
Selectable system interface formats
n
MICROWIRE
TM
and SCP compatible serial control
interface
n
TP3054/7 Codec/Filter COMBO
TM
compatibility
n
Single +5V supply
n
20-pin package DIP, PLCC
Applications
n
Same Device for NT, TE and PBX Line Card
n
Point-to-Point Range Extended to 1.5 km
n
Point-to-Multipoint for all I.430 Configurations
n
Easy Interface to:
LAPD Processor
MC68302, HPC16400
Terminal Adapter
MC68302, HPC16400
Codec/Filter COMBO
TP3054/7 and TP3076
"U" Interface Device
TP3410
Line Card Backplanes -- No External PLL Needed
n
Line Monitor Mode for Test Equipment
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
COMBO
TM
, MICROWIRE
TM
and SID
TM
are trademarks of National Semiconductor Corporation.
PRELIMINARY
July 1994
TP3420A
ISDN
S/T
Interface
Device
1999 National Semiconductor Corporation
DS009143
www.national.com
Block Diagram
Connection Diagrams
Pin Descriptions
Name
Description
GND
Negative power supply pin, normally 0V
(ground). All analog and digital signals
are referenced to this pin.
V
CC
Positive power supply input, which must
be +5V
5% relative to GND.
MCLK/XTAL
The 15.36 MHz Master Clock input, which
requires either a crystal (Note 1) to be
tied between this pin and XTAL2, or a
CMOS logic level clock input from a
stable source. When using a crystal, a
total of 33 pF load capacitance to GND
must also be connected. (Note 2)
XTAL2
The output of the crystal oscillator, which
should be connected to one end of the
crystal, and 33 pF of load capacitance to
GND. (Note 2) If using an external master
Clock via the MCLK pin, leave the XTAL2
pin unconnected.
BCLK
The Bit Clock pin, which determines the
data shift rate for "B" and "D" channel
data at the digital interface. When NT
mode or TES mode is selected, BCLK is
a TTL/CMOS input which may be any
multiple of 8 kHz from 256 kHz to 4.096
MHz. It need not be synchronous with
MCLK.
When TEM mode is selected, this pin is a
CMOS output at frequency selected by
the Digital Interface Format. This clock is
phase-locked to the received line signal
and is synchronous with the data on B
x
and B
r
.
DS009143-1
TP3420A SID
DS009143-20
Order Number TP3420AV
See NS Package Number V20A
TP3420A SID
DS009143-2
Top View
Order Number TP3420AJ or TP3420AN
See NS Package Number J20A or N20A
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2
Pin Descriptions
(Continued)
Name
Description
FS
a
In NT modes and TES mode, this pin is
the Transmit Frame Sync pulse
TTL/CMOS input, requiring a positive
edge to indicate the start of the active
channel time for transmit "B" and "D"
channel data into B
x
. In TEM mode only,
this pin is a digital output pulse whose
positive indicates the start of the "B"
channel data transfer at both B
x
and B
r
.
FS
b
(Pin 11)
In NT modes and TES mode, this pin is
the Receive Frame Sync pulse
TTL/CMOS input, requiring a positive
edge to indicate the start of the active
channel time of the device for receive "B"
and "D" channel data out from B
r
. In TEM
mode only, when digital interface Format
1 is selected, this pin is an 8-bit wide
pulse which indicates the active slot for
the B2 channel on the digital interface.
The DCKE command will alter the
function of this pin. See
Table 2 for
details.
B
x
TTL/CMOS input for "B" and "D" channel
data to be transmitted to the line; must be
synchronous with BCLK.
B
r
CMOS output for "B" and "D" channel
data received from the line, which is
synchronous with BCLK. When not
shifting data, this pin is TRI-STATE
.
DEN
x
/p2
(Pin 8)
In TEM mode, this pin by default is a
CMOS output which is normally low and
pulses high to indicate the active bit-times
for "D" channel Transmit data at the B
x
input. It is intended to be gated with
BCLK to control the shifting of data from
layer 2 device to the TP3420A transmit
buffer.
In NT modes, this pin by default is a
pulse output (DEN
x
) which occurs in
every 8 KHz frame and indicates the
location of D channel data input on the B
x
pin.
In TES mode, this pin by default is an
output synchronized clock (SCLK) at the
frequency selected by the Digital
Interface Format. This clock is
phase-locked to the received line signal,
and is intended to be used as the BCLK
source.
This pin called P2 in
Table 1 can also be
programmed to provide alternate
functions. See
Table 1 for details.
CI
MICROWIRE control channel serial data
TTL/CMOS input.
Name
Description
CO
Control channel serial data CMOS output
for status information. When not enabled
by CS, this output is TRI-STATE.
CCLK
TTL/CMOS clock input for the Control
Channel.
CS
Chip Select input which enables the
control channel data to be shifted in and
out when pulled low. When high, this pin
inhibits the Control interface.
INT
Interrupt output, a latched n-channel
open-drain output signal which is
normally high impedance, and goes low
to indicate a change of status of the loop
transmission system.
LSD/P1
(Pin 18)
In all modes, this pin by default is the
Line Signal Detect output, an n-channel
open-drain output which is normally
high-impedance, but pulls low when the
device is powered down and a received
line signal is detected. It is intended to be
used to "wake-up" a microprocessor from
a low-power idle mode. This output is
high impedance when the device is
powered up.
This pin P1 in
Table 1 can also be
programmed to provide alternate
functions. See
Table 1 for details.
L
o
+, L
o
-
Transmit AMI signal differential outputs to
the line transformer. When used with a
2:1 step-down transformer, the line signal
conforms to the output pulse masks in
I.430.
L
i
+, L
i
-
Receive AMI signal differential inputs
from the line transformer. The L
i
- pin is
also the internal voltage reference pin,
and must be decoupled to GND with a 10
f capacitor in parallel with a 0.1 F
ceramic capacitor.
Note 1: Crystal specification: 15.36 MHz parallel resonant; R
s
150
,
C
L
= 20 pF and C
O
<
7 pF.
Note 2: The 33 pF includes any board capacitance.
ALTERNATE PIN FUNCTIONS
With a MICROWIRE command PINDEF (B'1110 0 x2 x1 x0)
the pin signal functions of these pins can be changed to pro-
vide alternate functions (see
Table 1 and the MICROWIRE
command in
Table 4). "
*
" indicates the default pin function af-
ter a device mode selection. Power-up default device mode
is NTA.
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3
Pin Descriptions
(Continued)
TABLE 1. Alternate Pin Function Assignment
Device
Mode
P2 - Pin 8
P1 - Pin 18
Function
x
2
Function
x
1
, x
0
TEM
DENx
(Note 3)
0
(Note 3)
LSD
00
(Note 3)
SCLK
1
DENr
01
SCLK
10
DENx
11
TES
DENx
0
LSD
00
(Note 3)
SCLK
(Note 3)
1
(Note 3)
DENr
01
SCLK
10
DENx
11
NTA
DENx
(Note 3)
0
(Note 3)
LSD
00
(Note 3)
NTF
SCLK
1
DENr
01
SCLK
10
DENx
11
MMA
DENx
(Note 3)
0
(Note 3)
LSD
00
(Note 3)
SCLK
1
DENr
01
SCLK
10
DENx
11
PINDEF command is coded as X'EX (i.e. 11100x
2
x
1
x
0
).
Note 3: Default pin function after device mode selection.
SIGNAL DESCRIPTION
SCLK is an output synchronized clock at the frequency se-
lected by the Digital Interface Format. This clock is
phase-locked to the received line signal, and is intended to
be used as the BCLK source.
LSD is the Line Signal Output, an n-channel open-drain out-
put that is normally high-impedance, but pulls low when the
device is powered down and a received line signal is de-
tected. It is intended to be used to "wake-up" a microproces-
sor from a low-power idle mode. This output is a high imped-
ance when the device is powered up.
DENr is a CMOS output that is normally low and pulses high
to indicate the active bit times for "D" channel Receive data
at the B
r
output pin. It is intended to be gated with BCLK to
control the shifting of data from the TP3420A receive buffer
to a layer 2 device.
DENx is a CMOS output that is normally low and pulses high
to indicate the active bit times for D channel Transmit data at
the B
x
input. It is intended to be gated with BCLK to control
the shifting of data from a layer 2 device to the TP3420A's
transmit buffer. In NT mode, this pulse occurs every 8 kHz
frame and indicates the location of D channel data input on
the B
x
pin.
ADDITIONAL PIN CONFIGURATION
The TP3420A in TEM mode can be configured to interface
with the Motorola layer-2 devices such as the MC68302 and
the MC145488. A PINDEF (X'E1) command followed by a
DCKE (X'F1) command will alter the TP3420A pin functions
as shown in
Table 2. Other configurations of PINDEF are not
supported.
TABLE 2.
Pin Number
Pin Function
8
DTCK
11
TxD
18
DRCK
Where:
DCLK is a burst clock output intended to be used as a
clock source for the transmitter of an HDLC device.
TxD is an input being sampled on the rising edge of
DCLK during the active D-channel timeslot.
DRCK is a burst clock output which pulses 2 BCLK peri-
ods every 8 kHz frame. This output is intended to be used
as a clock source for the receiver of an HDLC device. The
D-channel data at B
r
is transmitted on the falling edge of
the DRCK.
Functional Description
DEVICE MODES
The TP3420A can be programmed into one of four possible
modes. For NT applications select NT Adaptive timing (NTA)
for all wiring configurations except a Short Passive Bus, for
which NT Fixed Timing (NTF) should be selected. In TE ap-
plications, select TE Master mode (TEM) for the device to be
the master (source) of clocks at the digital interface, or select
TE Slave mode (TES) for the digital interface to accept
clocks from the system.
Selection of these modes is described in the section on Con-
trol Register instructions.
POWER-ON DEVICE CONDITIONS
Following the initial application of power, the TP3420A SID
enters the power-down (de-activated) state, in which all the
internal circuits including the Master oscillator are inactive
and in a low power state except for the Line-Signal Detect
circuit; the line outputs L
o
+/L
o
- are in a high impedance
state and the Digital System Interface is inactive. All bits in
the Control Register power-up as indicated in
Table 1. In
both NT and TE modes, a Line-Signal Detect circuit monitors
the line while the device is powered-down, to enable loop
transmission to be initiated from either end.
POWER-OFF DEVICE CONDITION
When power to the TP3420A is turned off, the Line outputs
L
o
+/L
o
- go into high impedance state, hence if a TE on a
passive bus lost power its transmit impedance still meets the
specification without any external relay (see AN665 for exter-
nal protection components). The receiver impedance also
remains in specification.
LINE CODING AND FRAME FORMAT
For both directions of transmission, Alternate-Mark Inversion
(AMI) coding with inverted binary is used, as illustrated in
Figure 1. This coding rule requires that a binary ONE is rep-
resented by 0V high impedance output, whereas a binary
ZERO is represented by a positive or negative-going 100%
duty-cycle pulse. Normally, binary ZEROs alternate in polar-
ity to maintain a d.c.-balanced line signal.
The frame format used in the TP3420A SID follows the
CCITT recommendation specified in I.430 and illustrated in
Figure 2. Each complete frame consists of 48 bits, with a line
bit rate of 192 kb/s, giving a frame repetition rate of 4 kHz. A
violation of the AMI coding rule is used to indicate a frame
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4
Functional Description
(Continued)
boundary, by using a 0
+
bit followed by a 0
-
balance bit to in-
dicate the start of a frame, and forcing the first binary zero
following the balance bit to be of the same polarity as the bal-
ance bit.
In the Network Termination (NT) to the Terminal Equipment
(TE) transmission direction the frame contains an echo
channel, the E bit, which is used to retransmit the D bits that
are received from the TE. The last bit of this frame is used as
a frame balancing bit. In the TE to NT direction,
d.c.-balancing is carried out for each channel, as illustrated
in
Figure 2.
LINE TRANSMIT SECTION
The differential line-driver outputs, L
o
+ and L
o
-, are de-
signed to drive a transformer with an external termination re-
sistor. A suitable 2:1 transformer, terminated in 50
, results
in a signal amplitude of nominally 750 mV pk on the line
which fully complies with the I.430 pulse mask specifica-
tions. When driving a binary 1 symbol the output presents a
high impedance in accordance with I.430. When driving a 0+
or 0- symbol a voltage-limited current source is turned on.
Short-circuit protection is included in the output stage;
over-voltage protection is required externally, see the Appli-
cations section.
LINE RECEIVE SECTION
The receive input signal should be derived via a 1:1 trans-
former, or a 1:2 transformer of the same type used for the
transmit direction. At the front-end of the receive section is a
continuous filter which limits the noise bandwidth. To correct
pulse attenuation and distortion caused by the transmission
line in point-to-point and extended passive bus applications,
an adaptive equalizer enhances the received pulse shape,
thereby restoring a "flat" channel response with maximum
eye opening over a wide spread of cable attenuation charac-
teristics. This equalizer is always enabled when either TE
mode or NT Mode Adaptive Sampling is selected, but is dis-
abled for short passive bus applications when NT Mode
Fixed Sampling is selected. An adaptive threshold circuit
maximizes the Signal-to-Noise ratio in the eye at the detec-
tor for all loop conditions.
In NTF mode the receive baud sampling point is fixed rela-
tive to the transmit baud clock. This ensures accurate sam-
pling of received pulses with differential delays on a passive
bus, thus extending the short passive bus range to over
250m of low capacitive cable.
In NTA and TE modes, the receive baud sampling is adap-
tive. In these modes, a DPLL (Digital Phase-Locked Loop)
recovers a low-jitter clock for optimum sampling of the re-
ceived symbols. The MCLK input provides the reference
clock for the DPLL at 15.36 MHz. Clocks for the digital inter-
face timing may either be derived from this recovered clock,
as in TE mode Digital System Interface Master, or may be
slaved to an external source, as in the T-interface side of an
NT-2 (TES mode). In TES and NT modes, re-timing circuitry
on the TP3420A allows the MCLK frequency to be plesio-
chronous (i.e., free-running) with respect to the network
clock, i.e. the 8 kHz FS
a
input. With a tolerance on the MCLK
oscillator of 15.36 MHz
100 ppm, the lock-in range of the
DPLL allows the network clock frequency to deviate up to
50 ppm from nominal.
When the device is powered-down (either on initial
powering-on of the device or after using a PDN command), a
Line-Signal Detect circuit is enabled to detect the presence
of incoming data if the far-end starts to activate the loop. The
LSD circuit is disabled by a Power-Up (PUP) command.
DS009143-4
FIGURE 1. Inverted AMI Line-Coding Rule
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