NTE8212
Integrated Circuit
Schottky, 8Bit Input/Output Port
Description:
The NTE8212 input/output port is an integrated circuit in a 24Lead DIP type package and consists
of an 8bit latch with threestate output buffers along with control and device selection logic. Also
included is a service request flipflop for the control and generation of interrupts to the microprocessor.
Features:
D
Fully Parallel 8Bit Data Register and Buffer
D
Service Request FlipFlop for Interrupt Generation
D
Low Input Load Current: 0.25mA Max
D
Three State Outputs
D
Outputs Sink 15mA
D
3.65V Output High Voltge for Direct Interface to 8080A Processor
D
Asynchronous Register Clear
D
Replaces Buffers, Latches and Multiplexers in Microcomputer Systems
D
Reduces System Package Count
Absolute Maximum Ratings: (T
A
= +25
C, Note 1 unless otherwise specified)
All Output or Supply Voltages
0.5V to +7V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Input Voltages
1.0V to +5.5V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Currents
125mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range
0
to +70
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature Range
65
to +150
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Note 1. Stress above those listed under "Absolute Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Electrical Characteristics: (T
A
= 0
to +70
C, V
CC
= 5V
5% unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
DC Characteristics
Input Load Current
STB, DS
2
, CLR, DI
1
DI
8
Inputs
|I
L1
|
V
F
= 0.45V
0.25
mA
MD Input
|I
L2
|
0.75
mA
DS
1
Input
|I
L3
|
1.0
mA
Input Leakage Current
STB, DS, CLR, DI
1
DI
8
Inputs
|I
H1
|
V
R
= 5.25V
10
A
MD Input
|I
H2
|
30
A
DS
1
Input
|I
H3
|
40
A
Input Forward Voltge Clamp
V
C
I
C
= 5mA
1.0
V
Input "Low" Voltage
V
IL
0.85
V
Input "High" Voltage
V
IH
2.0
V
Output "Low" Voltage
V
OL
I
OL
= 15mA
0.48
V
Output "High" Voltage
V
OH
I
OH
= 1mA
3.65
V
Short Circuit Output Current
I
O
5
V
O
= 0V, V
CC
= 5V
15
75
mA
Output Leakage Current, High Impedance
State (DO
0
DO
8
)
I
O
V
O
= 0.45V/5.25V
20
A
Power Supply Current
I
CC
130
mA
AC Characteritics
Pulse Width
t
pw
Input Pulse Amplitude = 2.5V,
30
ns
Data to Output Delay
t
pd
Input Rise & Fall Times = 5ns,
Between 1V and 2V
30
ns
Write Enable to Output Delay
t
we
Between 1V and 2V
Measurement made
40
ns
data Setup Time
t
set
at 1.5V with 15mA and 30pF
Test Load
15
ns
Data Hold Time
t
h
20
ns
Reset to Output Delay
t
r
40
ns
Set to Output Delay
t
s
30
ns
Output Enable/Disable Time (Note 2)
t
e
/t
d
45
ns
Clear to Output Delay
t
c
55
ns
Note 2. R
1
= 300
/10K
; R
2
= 600
/1K
Capacitance: (T
A
= +25
C, V
CC
= 5V, V
BIAS
= 2.5V, f = 1MHz, Note 3 unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Capacitance
C
IN
DS
1
, MD
12
pF
Input Capacitance
C
IN
DS
2
, CLR, STB, DI
1
DI
8
9
pF
Output Capacitance
C
OUT
DO
1
DO
8
12
pF
Note 3. This parameter is periodically sampled and not 100% tested.
Functional Description:
Data Latch
The 8 flipflops that compose the data latch are of a "D" type design. The output (Q) of the flipflop
follows the data input (D) while the clock input (C) is high. Latching occurs when the clock (C) returns
low.
The data latch is cleared by an asynchronous reset input (CLR).
(NOTE: Clock (C) overrides Reset (CLR).)
Output Buffer
The outputs of the data latch (Q) are connected to threestate, noninverting output buffers. These
buffers have a common control line (EN); enabling the buffer to transmit the data from the outputs of
the data latch (Q) or disabling the buffer, forcing the output into a high impedance state (threestate).
This highimpedance state allows the designer to connect the NTE8212 directly to the microproces-
sor bidirectional data bus.
Control Logic
The NTE8212 has four control inputs: DS
1
, DS
2
, MD and STB. These inputs are employed to control
device selection, data latching, output buffer state and the service request flipflop.
DS
1
, DS
2
(Device Select)
These two inputs are employed for device selection. When DS
1
is low and DS
2
is high (DS
1
DS
2
)
the device is selected. In the selected state the output buffer is enabled and the service request flip
flop (SR) is asynchronously set.
Service Request FlipFlop (SR)
The (SR) flipflop is employed to generate and control interrupts in microcomputer systems. It is asyn-
chronously set by the CLR input (active low). When the (SR) flipflop is set it is in the noninterrupting
state.
The output (Q) of the (SR) flipflop is connected to an inverting input of a "NOR" gate. The other input
of the "NOR" gate is noninverting and is connected to the device selection logic (DS
1
DS
2
). The
output of the "NOR" gate (INT) is active low (interrupting state) for connection to active low input prior-
ity generating circuits.
MD (Mode)
This input is employed to control the state of the output buffer and to determine the source of the clock
(C) to the data latch.
When MD is in the output mode (high) the output buffers are enabled and the source of clock (C) to
the data latch is from the device selection logic (DS
1
DS
2
).
When MD is in the input mode (low) the output buffer state is determined by the device selection logic
(DS
1
DS
2
) and the source of clock (C) to the data latch is the STB (Strobe) input.
STB (Strobe)
STB is employed as the clock (C) to the data latch for the input mode (MD = 0) and to synchronously
reset the service request (SR) flipflop.
Note that the SR flipflop triggers on the negative edge of STB which overrides CLR.
DO
5
DI
5
DO
6
DI
6
DO
7
DI
7
DO
8
DI
8
DS
2
CLR
INT
V
CC
Pin Connection Diagram
1
12
24
13
1.300 (33.02) Max
.520
(13.2)
.600 (15.24)
1.100 (27.94)
.100 (2.54)
.225
(5.73)
Max
.126
(3.22)
Min
DS
1
GND
1
2
3
4
MD
5
6
7
8
24
23
22
21
20
19
18
17
9
16
10
11
STB
15
14
12
13
DI
1
DI
2
DI
3
DI
4
DO
1
DO
2
DO
3
DO
4
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