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Электронный компонент: NLC0375

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(c) NTT Electronics Corporation
November 2001
Digital Wrapper with Forward Error Correction
for 10Gbps Optical Transport Network
NLC0375APB
NTT Electronics Corporation
PRELIMINARY
NLC0375APB < Features >
(c) NTT Electronics Corporation
November 2001
Compliant with ITU-T G.709 Recommendation
FEC algorithm: Reed-Solomon code RS8 (255,239), Coding gain: 6db
Supports Justification Control (JC) and Fixed Stuff (FS) insertion for STM-64/OC-192 signal
Bit rate
OTU-side: 10.71 Gbps/10.66 Gbps
Client-side: 9.95 Gbps/9.99 Gbps
Simultaneous processing of Encoding/Decoding is possible
Upgrading to 40 Gbps system
By combining four LSIs together, upgrading to 40 Gbps system is possible
Other features
Overhead insertion/extraction
Scrambling/Descrambling
BIP-8 insertion/checking
Alarm detection/sending
Internal loop connection
Host CPU interface: 8-bits address/data separated bus
I/O interface
Main signal: LVDS, Others: LVTTL
600-pin BGA Package
Boundary scan test circuit (JTAG) compatible with IEEE1149.1 standard is built-in
Power supply: 1.8 V (for Core circuits) and 2.5V/3.3 V (for I/O circuits)
NLC0375APB < Block Diagram >
(c) NTT Electronics Corporation
November 2001
(OTU-Side)
(Client-Side)
666/669
Mbps
x 16ch
(LVDS)
666/669
Mbps
x 16ch
(LVDS)
Scrambler
RS
Encoder
Overhead
Insert
FIFO
FEC
Framer
Descrambler
RS
Decoder
Overhead
Extract
622/624
Mbps
x 16ch
(LVDS)
Microprocessor
Interface
JTAG
OH input
OH output
Host CPU
Encoder
output
Decoder
output
Encoder
input
Decoder
input
FIFO
622/624
Mbps
x 16ch
(LVDS)
NLC0375APB < Clock System >
(c) NTT Electronics Corporation
November 2001
DEMUX
1:16
EO15-00(P/N)
ECLKL(P/N)
ECLKLO(P/N)
ECLKLO2(P/N)
TXDATA
TXCLK
TXCLK_SRC
RXCLK
EI15-00(P/N)
ECLKS(P/N)
DO15-00(P/N)
DCLKS(P/N)
DCLKSO(P/N)
DCLKSO2(P/N)
TXDATA
TXCLK
TXCLK_SRC
RXDATA
RXCLK
DI15-00(P/N)
DCLKL(P/N)
MUX
16:1
DEMUX
1:16
MUX
16:1
Client
OTU
Encoder
Encoder
Encoder
Encoder
Decoder
Decoder
Decoder
Decoder
STM-64
OC-192
other
a
b
85/79
15/14
79/85
14/15
Client
10.71Gbps
10.66Gbps
-
REFCLK
REFCLK
PLL
PLL
f
1
* a
f
1
NLC375APB
NLC375APB
NLC375APB
NLC375APB
f
2
f
2
* b
9.95Gbps
9.95Gbps
9.99Gbps
669.33MHz
666.52MHz
OTU
622.08MHz
622.08MHz
624.70MHz
clock in
bitrate
signal
PLL
bitrate
clock in
O/E
E/O
O/E
E/O
RXDATA
Frame Structure (ITU-T G.709)
Order of frame data transmission (ITU-T G.709)
NLC0375APB < Frame Structure >
(c) NTT Electronics Corporation
November 2001
Overhead
Payload
FEC
(4 x 16 bytes)
(4 x 3808 bytes)
(4 x 256 bytes)
Column
Row
1
16
17
. . .
4080
3825
3824
. . .
. . .
1
2
3
4
(4 x 16 bytes)
(4 x 3808 bytes)
(4 x 256 bytes)
1
2
3
4
5
6
7
8
MSB
LSB
Column
Row
1
16
17
. . .
4080
3825
3824
. . .
. . .
1
2
3
4