(c) NTT Electronics Corporation
November 2001
Digital Wrapper with Forward Error Correction
for 10Gbps Optical Transport Network
NLC0375APB
NTT Electronics Corporation
PRELIMINARY
NLC0375APB < Features >
(c) NTT Electronics Corporation
November 2001
Compliant with ITU-T G.709 Recommendation
FEC algorithm: Reed-Solomon code RS8 (255,239), Coding gain: 6db
Supports Justification Control (JC) and Fixed Stuff (FS) insertion for STM-64/OC-192 signal
Bit rate
OTU-side: 10.71 Gbps/10.66 Gbps
Client-side: 9.95 Gbps/9.99 Gbps
Simultaneous processing of Encoding/Decoding is possible
Upgrading to 40 Gbps system
By combining four LSIs together, upgrading to 40 Gbps system is possible
Other features
Overhead insertion/extraction
Scrambling/Descrambling
BIP-8 insertion/checking
Alarm detection/sending
Internal loop connection
Host CPU interface: 8-bits address/data separated bus
I/O interface
Main signal: LVDS, Others: LVTTL
600-pin BGA Package
Boundary scan test circuit (JTAG) compatible with IEEE1149.1 standard is built-in
Power supply: 1.8 V (for Core circuits) and 2.5V/3.3 V (for I/O circuits)
Frame Structure (ITU-T G.709)
Order of frame data transmission (ITU-T G.709)
NLC0375APB < Frame Structure >
(c) NTT Electronics Corporation
November 2001
Overhead
Payload
FEC
(4 x 16 bytes)
(4 x 3808 bytes)
(4 x 256 bytes)
Column
Row
1
16
17
. . .
4080
3825
3824
. . .
. . .
1
2
3
4
(4 x 16 bytes)
(4 x 3808 bytes)
(4 x 256 bytes)
1
2
3
4
5
6
7
8
MSB
LSB
Column
Row
1
16
17
. . .
4080
3825
3824
. . .
. . .
1
2
3
4