PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a

10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI ASA - Vestre Rosten 81, N-7075 Tiller, Norway

Phone +4772898900

Fax +4772898989

Revision: 1.0A

Page 1 of 13

2003-04-10

FEATURES

10-bit ADC

Up to 120 MSPS Conversion Rate

Single 1.2 V Power Supply

1.0 V p-p Differential Input

Excellent Dynamic Performance
59 dBFS SNR at F

= 10 MHz

70 dBc SFDR at F

= 10 MHz

600 MHz Analog Input Bandwidth

Low Power Consumption
90 mW at 120 MSPS
20 mW at 25 MSPS

Dynamic Power Scaling

Power Saving Idle Modes

Internal Voltage Reference

1.34 mm

Core Area

APPLICATIONS

Communication Receive Channel
WLAN / HiperLan / 802.11x

Digital Imaging / Video

TV / Video / Radio Decoders

Graphic Capture

GENERAL DESCRIPTION

The nAD10120-13a is a monolithic, high-speed,
low power, analog-to-digital converter silicon IP. It
uses

fully

differential

multistage

pipeline

architecture with digital error correction to provide
10-bit accuracy from 10 to 120 MSPS conversion
speed. The core includes a wide-band sample-and-
hold and an internal voltage reference that provides
a nominal full-scale range of 1.0 V peak-to-peak.

The IP is designed for high dynamic performance
at input frequencies up to Nyquist and beyond. It
thus

represents

ideal

solution

for

PIPELINE

ADC

DIGI

CORR

ECTI

DYNAMIC

BIAS

VOLTAGE

REFERENCE

BITO[9:0]
RFLAG[2:0]

OPM[1:0]

CLK

EXTREF

TIMING GENERATOR

DIGITAL CONTROL

INP

VCM

INN

REFP

REFN

Figure 1. Functional block diagram

demanding

applications

broadband

communication, digital imaging and multimedia.
The ADC consumes only 90 mW at 120 MSPS
operation. Dynamic power scaling means that the
power consumption is scaled with the operating
frequency resulting in only 20 mW consumption at
25 MSPS operation. Combined with power saving
idle modes the ADC is suitable for battery powered
devices.

The conversion is controlled by the single-ended
clock input. Output data is available in a binary
offset coded format. Three out-of-range indicator
bits are also available for determining if the input
signal is over-range, under-range or out-of-range.

Implemented in a generic 0.13

m CMOS process,

operating from a single 1.2 V supply and
employing a

fully differential architecture

represents an ideal ADC for highly integrated
mixed-signal systems.

QUICK REFERENCE DATA

IP Type / Technology

Hard Macro / TSMC Generic, 8 Metal 0.13

m CMOS

IP Area / Dimensions

1.34 mm

/ 1.400

0.93 mm

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

1.1

1.2

1.3

Power Dissipation, @ F

CLK

= 110 MHz

Differential Non Linearity

0.5

LSB

Integral Non Linearity

LSB

Signal-to-Noise Ration, F

= 10 MHz

dBFS

Spurious-Free-Dynamic Range, F

= 10 MHz

dBc

Table 1. nAD10120-13a quick reference data

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 2 of 13

Revision: 1.0A

ELECTRICAL SPECIFICATIONS

DC SPECIFICATIONS

( At T

= 25 ºC, V

AVDD

= V

VDD

= 1.2 V, F

CLK

= 120 MHz, F

= 10 MHz, internal references, differential full-

scale input signal, 50 % duty cycle clock, and 10nF reference decoupling unless otherwise noted )

Symbol

Parameter (condition)

Test
level

Min.

Typ.

Max.

Unit

DC ACCURACY

Resolution

Bits

NMC

No Missing Codes Guaranteed

Bits

MON

Monotonicity Guaranteed

Bits

INL

Integral Non Linearity

0.4

1.0

LSB

DNL

Differential Non Linearity

0.3

0.5

LSB

Gain Error

1.0

% FSR

Offset Error

1.0

% FSR

ANALOG INPUT

FSR

Input Differential Voltage Range

0.5

VCM,EXT

Input Common Mode Voltage

0.6

0.65

0.7

Input Impedance

1.5

AIBW

Analog Input Bandwidth

600

MHz

REFERENCE VOLTAGES

REFP

Internal Positive Voltage Reference

0.9

REFN

Internal Negative Voltage Reference

0.5

Internal Reference Range

0.5

FSR

Internal Differential Full-scale Range

1.0

V p-p

VCM

Internal Reference Common Mode Voltage

0.65

Internal Voltage Reference Drift

100

ppm /

RR,EXT

External Reference Range

0.25

0.5

FSR

EXT

External Differential Full Scale Range

0.5

1.0

V p-p

RCM,EXT

External Reference Common Mode Voltage

0.65

POWER SUPPLY

AVDD

Positive Analog Supply Voltage

1.1

1.2

1.3

VDD

Positive Digital Supply Voltage

1.1

1.2

1.3

Negative Supply Voltage

GND

Supply Current, Active

Supply Current, Standby

2.2

Supply Current, Sleep

1.7

Supply Current, Power down

2.2

Power Dissipation, Active

Power Dissipation, Standby

Power Dissipation, Sleep

Power Dissipation, Power down

OPERATING CONDITIONS

Junction Operating Temperature

-40

125

Table 2. nAD10120-13a DC Specifications

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 3 of 13

Revision: 1.0A

DYNAMIC SPECIFICATIONS

( At T

= 25 ºC, V

AVDD

= V

VDD

= 1.2 V, F

CLK

= 120 MHz, F

= 10 MHz, internal references, differential full-

scale input signal, 50 % duty cycle clock, and 10nF reference decoupling unless otherwise noted )

Symbol

Parameter (condition)

Test
level

Min.

Typ.

Max.

Unit

SWITCHING PERFORMANCE

CLK,MAX

Maximum Conversion Rate

120

MSPS

CLK,MIN

Minimum Conversion Rate

MSPS

Input Clock Duty Cycle

Pipeline Delay ( Latency )

clocks

Output Data Delay Time

Output Data Hold Time

Aperture Delay Time

0.9

jitter

Aperture Uncertainty ( Jitter )

1.5

ps rms

standby

Start-up Time from Standby Mode

clocks

sleep

Start-up Time from Sleep Mode

0.5

power down

Start-up Time from Power Down Mode

out-of-range

Out-of-Range Recovery Time

SNR

SIGNAL-TO-NOISE RATIO

120 MSPS, F

= 10 MHz

dBFS

120 MSPS, F

= 40 MHz

58.5

dBFS

120 MSPS, F

= 72 MHz

dBFS

SINDR

SIGNAL-TO-NOISE-AND DISTORTION
RATIO

120 MSPS, F

= 10 MHz

dBFS

120 MSPS, F

= 40 MHz

dBFS

120 MSPS, F

= 72 MHz

dBFS

SFDR

SPURIOUS FREE DYNAMIC RANGE

120 MSPS, F

= 10 MHz

dBc

120 MSPS, F

= 40 MHz

dBc

120 MSPS, F

= 72 MHz

ENOB

EFFECTIVE NUMBER OF BITS

120 MSPS, F

= 5 MHz

9.6

Bit

120 MSPS, F

= 10 MHz

9.4

Bit

120 MSPS, F

= 40 MHz

8.3

Bit

120 MSPS, F

= 72 MHz

8.0

Bit

Table 3. nAD10120-13a Dynamic Specifications

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 4 of 13

Revision: 1.0A

DEFINITIONS OF SPECIFICATIONS

Integral Non Linearity ( INL )
The deviation of the ADC transfer function from
the ideal transfer function. The ideal transfer
function is defined as a straight line between the
end points of the transfer characteristic corrected
for gain and offset. INL for each code is calculated
at the code transitions.

Differential Non Linearity ( DNL )
In an ideal ADC every code transition to its
neighbours equals to 1 LSB. DNL is the deviation
of each code transition from the ideal value.

Gain Error
The deviation of the actual difference between the
first and last code transition and the ideal
difference.

Offset Error
Mid code ideally occurs for zero differential input.
The offset error is the differential input voltage that
gives mid code.

Analog Input Bandwidth
The analog input frequency for which the measured
input signal power has dropped by 3 dB.

Temperature Drift
The temperature drift specifies the maximum
change from the nominal junction temperature to
the minimum and maximum junction temperature.

Maximum Conversion Rate
The maximum conversion rate is the conversion
rate at which electrical specifications are tested.

Minimum Conversion Rate
The minimum conversion rate is the slowest
conversion rate where the ADC is functional.

Pipeline Delay ( Latency )
The pipeline delay is the time it takes from a
sample is taken at the input to the sample is
converted and put on the digital output.

Output Data Delay Time
Output data delay time is the time from the clock
edge that defines valid output data to all data
outputs have reached valid logical levels for the
next data sample.

Output Data Hold Time
Output data hold time is the time from the clock
edge that defines valid output data to the output
data is no longer valid.

Aperture Delay Time
The delay between the sampling clock edge and the
time when the input signal is held for conversion.

Aperture Uncertainty ( Jitter )
Aperture uncertainty or jitter is the variation of the
aperture delay time for successive samples.

Clock Duty Cycle
The fraction of the time the clock spends above the
logic threshold.

Start-up Time from Idle Mode
The time it takes to reach full performance after a
transition from an idle mode to active mode.

Out of Range Recovery Time
The time required for the ADC to return to
specified

characteristics

after

out-of-range

sample.

Signal-to-Noise Ratio ( SNR )
SNR is the rms ratio of the measured input signal
to the sum of all other spectral components
excluding the dc and the first eight harmonics.

Spurious-Free Dynamic Range ( SFDR )
SFDR is the amplitude difference between the
measured input signal and the highest harmonic
component.

Signal-to-Noise and Distortion Ratio ( SNDR )
SNDR is the rms ratio of the measured input signal
to the sum of all other spectral harmonics
excluding the dc component.

Effective Number of Bits ( ENOB )
Effective number of bits specifies the total rms
noise in terms of bits of resolution the ADC
effectively performs. Generally ENOB depends on
the amplitude and frequency of the input signal
used to test it. The ENOB can be calculated
directly from the SNDR as follows:

6.02

1.76

SNDR

ENOB

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 5 of 13

Revision: 1.0A

ABSOLUTE MAXIMUM RATINGS

Pin / Condition

Min

Max

Unit

All pins referred to AVSS pin

-0.2

1.5

Operating Junction Temperature

-40

125

Storage Temperature

-65

125

Table 4. Absolute maximum ratings

EXPLANATION OF TEST LEVELS

Test Level I:

100% production tested at +25°C

Test Level II:

100% production tested at +25°C and sample tested at specified temperatures

Test Level III:

Sample tested only

Test Level IV:

Parameter is guaranteed by design and characterization testing

Test Level V:

Parameter is typical value only

Test Level VI:

100% production tested at +25°C. Guaranteed by design and characterization testing for
industrial temperature range

Stress above one or more of the limiting values may cause permanent damage to the device

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 6 of 13

Revision: 1.0A

COMPLETE PINOUT LIST

Name

Type

Description

INP, INN

Differential Voltage Inputs

VCM

Common Mode Voltage Output

REFP, REFN

Differential Voltage References

CLK

Conversion Clock

BITO[9:0]

Digital Output Code. BITO[9] is MSB, BITO[0] is LSB

RFLAG[2:0]

Digital Over-Range Indicator Output Code

OPM[1:0]

Operational Mode Control Input Code

OECTRL

Enables Output bits when high, disables when low.

AVDD

Positive 1.2 V Analog Supply

VDD

Positive 1.2 V Digital Supply

AVSS

Ground

D = Digital, A = Analog, I = In, O = Out, B = Bidirectional, T = Tristate, P = Power, G = Ground.

Table 5. nAD10120-13a pinout list

PHYSICAL DESCRIPTION

Dimensions and pin-out configuration for the core
is

shown

Figure

The

core

occupies

approximately 1.34 mm

of silicon area, and

includes necessary shielding and guardring. It is
implemented in TSMC 0.13

m CMOS process,

using no extra mixed signal options. All the 8
available metal layers are utilized by the core. No
fill pattern is necessary to meet TSMC density
rules, it meets all TSMC density rules on poly and
metal.

It is designed for, and verified with standard TSMC
I/O pads with ESD protection. I/O Pads are not
included in the core. Recommended pad type for
each pin, if exiting the die, is available in the
integration instruction document. This document
also contains guidelines for padring design and
package requirements.

1400

INP

INN

VCM

CLK

RFLAG[0]

RFLAG[1]

RFLAG[2]

BITO[0]

BITO[1]

BITO[2]

BITO[3]

BITO[4]

BITO[5]

BITO[6]

BITO[7]

BITO[8]

BITO[9]

REFP

REFN

OP
M
[
1]

OP
M
[
0]

940

nAD10120-13a

TOP VIEW

(Pin size and placment not to scale)

OECTRL

Figure 2. Core dimensions and pinout configuration

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 7 of 13

Revision: 1.0A

THEORY OF OPERATION

General Description

The nAD10120-13a employs a fully differential
pipelined architecture with digital error correction.
The pipeline has 8 stages with a low-resolution
flash at the end. Each stage converts with the
sufficient redundancy to digitally correct for errors
introduced by the preceding stage. The first stage
samples and holds the differential analog input at
the positive edge of the conversion clock. Outputs
from all stages are combined into the final 10-bit
word by the digital correction logic.

An internal reference circuit creates the positive
and negative reference voltages, V

REFP

and V

REFN

that define the full-scale range of the ADC. The
reference voltages are generated from internal
bandgap voltage.

The fully differential architecture effectively makes
the ADC robust towards noise. It thus represents an
ideal ADC with optimum performance even in
highly integrated systems.

Analog Inputs

The

analog

input

the

nAD10120-13a

differential switched capacitor pipeline stage with
internal

sample-and-hold

functionality.

designed for optimum performance processing a
differential input signal with a common mode equal
to the common mode output voltage V

VCM

available at the VCM pin. Referring to Figure 3,
the input stage switches between the sample and
the hold phase. In the sample phase the signal
source must be able to charge the internal sample
capacitors and settle within half a clock cycle. Best
dynamic performance is obtained by matching the
source impedance of the sources driving the inputs
to

ensure

the

common

mode

errors

are

symmetrical. This error is further reduced by the
common mode rejection ratio of the ADC. Proper
termination of the inputs is important to maintain
input signal purity. Small resistor in series with the
inputs reduces peak currents and kickback between
the source and the input. A small capacitor between
the inputs further reduces kickback noise from the
sample-an-hold and provides dynamic

charge

current. The precise values of this series resistors
and parallel capacitor should be chosen to fit the
application. For low input signal frequencies these
can be used to provide extra filtering of the input,
for high input frequencies, for example IF signals,
these components should have very small values
not to attenuate the input.

1 pF

INP

INN

Figure 3. Switched capacitor input principle

The full-scale range of the ADC is defined by the
internally generated voltage references V

REFP

and

REFN.

,nominally 0.9 and 0.4 V respectively. These

references

are

symmetrical

around

the

internally generated common mode voltage V

VCM

nominally 0.65 V. The full-scale range V

FSR

defined as twice the difference between the
reference voltages V

, as shown in Figure 4 and

Figure 5

1.2

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

REFP

INN

INP

Figure 4. Analog input voltage swing

0.6

0.5

0.4

0.3

0.2

0.1

0.2

0.3

0.4

0.5

0.6

FSR

Figure 5. Definition of full-scale range

Figure 4 shows a differential full-scale input signal
relative to the supply voltages.

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 8 of 13

Revision: 1.0A

TIMING DIAGRAM

N-7

N-8

N-6

N-5

N-4

N-3

N-2

N-1

N+1

N+2

N+3

N+4

N+5

N+6

N+7

INP

-V

INN

CLK

BIT0[9:0]

Figure 6. Timing diagram

Timing

Figure 6 shows the timing diagram for the
nAD10120-13a. Th analog input voltage is sampled
at the negative edge of the conversion clock.
Latched digital output data is provided with a
pipeline delay of 6 clock cycles, and available after
one propagation delay t

after the falling edge of

the conversion clock. BITO and RFLAG have
identical timing.

Differential Input Configuration

Optimum performance will be achieved by driving
the

nAD10120-13a

differential

input

configuration. An example of a DC coupled input
configuration using an off-chip amplifier is shown
in Figure 7. The AD8138 differential amplifier
provides

adequate

performance

for

baseband

applications.

For

low

sampling,

input

frequencies in the range 50 to 100 MHz, the
AD8351 is recommended. The output common
mode of the driving amplifier should be controlled
by the common mode output of the nAD10120-
13a. Series resistors and small capacitors to ground
should be used to attenuate kick back noise from
the sample and hold.

Chip with

nAD IP

VCM

INN

INP

Figure 7. Differential DC coupled input using an

off-chip amplifier

Figure 8 shows an example of an AC coupled input
configuration using an off-chip amplifier. In this
configuration the common mode pin can be
bypassed on-chip, thus reducing external pin count.

Chip with

nAD IP

VCM

INN

INP

Figure 8. Differential AC coupled input using an

off-chip amplifier

An AC coupled input can also be implemented
using a transformer with a centre tapped secondary
winding. As shown in Figure 9, the center tap
should be connected to the common mode output
pin of the nAD10120-13a.

Chip with

nAD IP

VCM

INN

INP

Figure 9. Differential AC coupled input using a

off-chip transformer

In order to obtain low distortion, it is important that
the transformer exhibit core saturation at full-scale.

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 9 of 13

Revision: 1.0A

Excellent results can be obtained with the Mini
Circuits T1-6T or T1-1T

Single-ended Input Configuration

If a single ended input is preferred, a solution based
on operational amplifiers is recommended. The
AD8138 can be used in a single ended to
differential configuration. A simple low cost
alternative is shown in Figure 10. The negative
input is connected to the common mode output, and
only the positive input is used input. In this
configuration the input full-scale range is halved,
and

degradation

performance

should

expected.

Chip with

nAD IP

VCM

INN

INP

Figure 10. Single-ended input configuration

Internal References

A nominal differential full-scale range of 1.0 V
peak-to-peak is generated by the internal voltage
reference. However for stable operation the REFP
and REFN pins should be bypassed to ground using
at least 10 nF capacitor. The internal references are
buffered with a low output impedance buffer,
which is disabled for external reference operation.

External Reference Configuration

The internal references can be overridden by
externally generated references. This can be used to
set the full-scale range between

0.25 to

0.50 V.

Externally

generated

reference

must

symmetrical about the 0.65 V common mode
voltage.

Clock Input

The nAD10120-13a uses both edges of the input
clock to generate internal timing signals, and thus
is sensitive to the conversion clock duty cycle. To
maintain specified performance the clock must
have 50 % duty cycle within 5 % tolerance. In
order to preserve performance at high input
frequencies, it is critical that the clock has low jitter
and steep edges. The ADC can be considered as a
mixer

the

clock

and

the

input

signal.

Multiplication in the time domain is equivalent to
convolution in the frequency domain. Aperture
jitter on the clock is a wide band noise. This noise
will be sampled and effectively folded into the
output spectrum. This noise will degrade the SNDR
of the ADC.

The ideal SNDR of an N bit ADC is given by:

SNDR = 6.02

N + 1.76 [dB]

Which yields 62 dB for a 10-bit converter.
Degradation of the SNDR only due to the effect of
aperture jitter is given by:

SNDR

jitter

= 20log(2

rms

)

where

rms

is rms value of the conversion clock

jitter. This form of degradation applies to any
number of bits and sampling frequencies. When
considering overall system performance it should
be noted that the clock jitter is summed as root
mean square. If the conversion clock applied to the
converter has a jitter of

, this jitter will be added

to the internal jitter t

jitter

of the ADC. The total

degradation due to jitter is then given by:

SNR

jitter

= 20log(2

(

rms

+ t

jitter

)

This equation provides much insight into the noise
performance that can be expected from the ADC
with a given clock source. A second effect is
harmonic noise on the clock, generated for example
by circuitry running at a frequency different from
the sampling frequency. These frequencies will
also be mixed with the input signal and show up in
the output spectrum. Although the clock is a signal
with digital levels and transitions it should be
treated very carefully to ensure optimum dynamic
performance.

Digital Outputs

The digital output data BITO[9:0] appears in 10-bit
offset binary code at CMOS levels. Three extra bits
RFLAG[2:0] are provided to indicate out-of range
conditions. Table 7 shows the digital output coding.
A nominal full-scale range of 1.0 V peak-to-peak is
used in the table. The RFLAG[2] output indicates
that the analog input is under-range, RFLAG[1]
that the analog input is over-range. Out-of range is
indicated by RFLAG[0], which is the logical OR of
RFLAG[1] and RFLAG[2].

The digital output drivers are scaled to provide
necessary current to drive on-chip logic. For
applications that require driving of large capacitive
loads, extra buffering should be added to avoid
performance degradations.

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 10 of 13

Revision: 1.0A

Operational Mode Control

In addition to the active mode, in which the ADC is
operating normally, the nAD10120-13a provides
standby, sleep and power down modes. These idle
modes can be used to save power while the ADC is
not required to be active. The different modes
reflects different trade-offs between power saving
and start-up time to active mode. The start-up time
is defined as the time it takes to reach full
performance in active mode switching from the idle
mode. Table 6 shows how to set the operational
mode with the input digital control code OPM[1:0].

Mode of Operation

OPM[1:0]

Active

Standby

Sleep

Power Down

Table 6. Operational mode control settings

For power consumption and start-up times for the
idle modes refer to electrical specifications in Table
2 and Table 3.

Dynamic Power Scaling

The

bias

level

the

nAD10120-13a

automatically adjusted based on the conversion
rate. This means that the ADC is not just functional
at lower conversion rates than the maximum, but
the

power

dissipation

also

continuously

minimized for the current conversion speed. The
power consumption is roughly proportional to the
conversion rate, so halving the conversion rate
roughly halves the power dissipation.

Required Off-Chip Components

In addition to components required by the specific
input configuration, a set of off-chip components is
necessary for correct operation.

The differential reference pins, REFP and REFN
must be bypassed to each other with 10 nF. The
analog power pin, AVDD must be bypassed to
external ground with 100 nF in parallel with 1 nF.

DIGITAL OUTPUT CODING

Code

INP

-V

INN

1.0 V p-p FSR

Digital Output
BIT0[9:0]

Over-Range Indicator
RFLAG[2:0]

1023

> 0.5 V

1 111 111 111

011

512

0.5 mV

1 000 000 000

000

511

-0.5 mV

0 111 111 111

000

< - 0.5 V

0 000 000 000

101

Table 7. nAD10120-13a digital output coding

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 11 of 13

Revision: 1.0A

DELIVERABLES

Upon a licensing we provide a complete set of
deliverables. It includes all necessary files for
design-in and integration, like streamfile, HDL
model, timing model and footprint files. In addition
we provide a set of documentation covering
everything

from

integration

guidelines

production test specification. Table 8 lists and
describes the deliverables.

ENGINEERING SUPPORT

An IP licensing also includes 40 hours of support
from our highly experienced engineers. We have
experience with integration of our IPs in broadband
communication,

imaging

and

video

chips.

Examples of areas where our support can be
valuable are:

Design-in
Specification
IP configuration
Extra IP features

Layout integration
Floorplanning
Signal routing and connection
Power supply strategies
Clock strategies
Padring and bond-out

System Verification
LVS , DRC and Antenna check

Functional verification
Timing closure

Characterization
PCB design
Test software
Test instrumentation

Production test
Test strategy
Test software

CUSTOMIZATION

We also offer customization of this IP to meet extra
requirements set by your application.

COMPLETE DESIGN HANDOFF

Using the Nordic VLSI PhysicalExpress service we
are able to offer a complete design handoff. Using
our extended mixed signal experience we take your
RTL code, netlist or gds2 and integrate it with our
IP. We can deliverer a complete gds2 or packaged
tested components back to you. Please refer to our
website for more details about this service.

COMPLETE DELIVERABLE LIST

Deliverable

Description

Physical Layout

Physical layout stream file in gds2 format. The stream file includes the
complete IP with necessary guardring and shielding.

Netlist

Flat spice compatible netlist for LVS and simulations.

Footprint

IP footprint in LEF format for floorplanning and placement.

Timing Models

Synopsys .lib files for timing closure.

HDL Models

Verilog or VHDL behavioral models for system simulation and
verification.

Evaluation Board and Samples

Packaged IP samples on evaluation board for performance measurements
and prototype systems.

Application Notes

Various application notes related to the IP.

Characterization Report

Full characterization report of the packaged IP.

Integration Instructions

Guidelines for IP integration, including signal connection, recommendation
of pads and bond-out, power supply and clock strategies. Includes
description of advanced IP features and system trade-offs.

Test Specification

Guidelines for production test of the integrated IP.

Evaluation Board User Guide

Complete user guide for the evaluation board and samples.

Table 8. List of deliverables

PRELIMINARY PRODUCT SPECIFICATION

nAD10120-13a - 10-bit 120 MSPS Analog-to-Digital Converter IP

Nordic VLSI

Page 12 of 13

Revision: 1.0A

DOCUMENT INFO

Preliminary Product Specification

nAD10120-13a

Product description:

10-bit 120 MSPS Analog-to-Digital Converter IP

Revision:

1.0A

Revision Date:

2003-04-10

Template ID:

1159140_045 r.1.1A

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of
these products can reasonably be expected to result in personal injury. Nordic VLSI ASA customers using or
selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic
VLSI ASA for any damages resulting from such improper use or sale.

DEFINITIONS

Data sheet status

Objective product specification

This datasheet contains target specifications for product development.

Preliminary product specification

This datasheet contains preliminary data; supplementary data may be
published from Nordic VLSI ASA later.

Product specification

This datasheet contains final product specifications.

Limiting values

Stress above one or more of the limiting values may cause permanent damage to the device. These are stress
ratings only and operation of the device at these or at any other conditions above those given in the
Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may
affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Table 9. Definitions

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: nAD10120-13

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: nAD10120-13