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Semiconductor
MSM80C31F/80C51F
Semiconductor
MSM80C31F/MSM80C51F
CMOS 8-Bit Microcontroller
GENERAL DESCRIPTION
The OKI MSM80C31F/MSM80C51F microcontroller is a low-power, 8-bit device implemented
in OKI's silicon-gate complementary metal-oxide semiconductor process technology. The
device includes 4K bytes of mask programmable ROM (MSM80C51F only), 128 bytes of
data RAM, 32 I/O lines, two 16-bit timer/counters, a five-source two-level interrupt
structure, a full duplex serial port, and an oscillator and clock circuitry. In addition, the device
has two software selectable modes for further power reduction -- Idle and Power Down. Idle
mode freezes the CPU's in-struction execution while maintaining RAM and allowing the timers,
serial port and interrupt system to continue functions. Power Down mode saves the RAM
contents but freezes the oscillator causing all other device functions to be inoperative.
FEATURES
Low power consumption by 2 mm silicon gate CMOS process technology
Fully static circuit
Internal program memory
:
4K bytes (MSM80C51F)
External program memory space
:
64K bytes
Internal data memory (RAM)
:
128 bytes
External data memory (RAM) space
:
64K bytes
I/O ports
:
8-bit 4 ports
Two 16-bit timer/counters
Multifunctional serial port (UART)
Five interrupt sources (Priority can be set)
Four sets of working registers (R0-7 4)
Stack
:
Internal data memory (RAM)
128-byte area can be used arbitrarily (by SP specified)
Two CPU power-down modes
(1) Idle mode
:
CPU stopped while oscillation continued.
(Software setting)
(2) PD mode
:
CPU and oscillation all stopped.
(Software setting)
(Setting I/O ports to floating status possible)
Operating temperature
:
40 to +85
C (@ 12 MHz, V
CC
= 5 V
20%)
20 to +70
C (@ 16 MHz, V
CC
= 5 V
5%)
2-byte 1-machine cycle instructions
:
1 msec. @ 12 MHz
0.75 msec. @ 16 MHz
Multiplication/division instructions
:
4 msec. @ 12 MHz
3 msec. @ 16 MHz
Instruction code addressing method
Byte specification
:
Data addressing (direct)
Bit specification
:
Bit addressing
E2E1037-19-41
This version: Mar. 1995
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Semiconductor
MSM80C31F/80C51F
Package options
40-pin plastic DIP (DIP40-P-600-2.54)
:
(MSM80C31F-RS) (MSM80C51F-RS)
44-pin plastic QFP (QFP44-P-910-0.80-2K)
:
(MSM80C31F-GS) (MSM80C51F-GS)
44-pin plastic QFJ (PLCC) (QFJ44-P-S650-1.27) :
(MSM80C31F-JS) (MSM80C51F-JS)
indicates the code number.
DIFFERENCES BETWEEN MSM80C31F/MSM80C51F AND MSM80C31/MSM80C51
Operating frequency
0.5 to 16 MHz ..................... MSM80C31F-1/MSM80C51F-1
0.5 to 12 MHz ..................... MSM80C31/MSM80C51/MSM80C31F/MSM80C51F
External clock input terminal
XTAL1 ................................. MSM80C31F(-1)/MSM80C51F(-1)
XTAL2 ................................. MSM80C31/MSM80C51
Emulation mode
Output impedance of ALE and PSEN pins becomes about 20 kW while CPU is being reset in
MSM80C31F/MSM80C51F.
Any other functions and electrical characteristics of MSM80C31F/MSM80C51F except for
above three differences are the same as those of MSM80C31/MSM80C51.
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