Semiconductor
MD56V62160/H
1/28
DESCRIPTION
The MD56V62160/H is a 4-bank 1,048,576-word 16-bit synchronous dynamic RAM,
fabricated in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs
and outputs are LVTTL compatible.
FEATURES
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
4-bank 1,048,576-word 16-bit configuration
3.3 V power supply,
0.3 V tolerance
Input
: LVTTL compatible
Output
: LVTTL compatible
Refresh : 4096 cycles/64 ms
Programmable data transfer mode
CAS latency (2, 3)
Burst length (2, 4, 8)
Data scramble (sequential, interleave)
CBR auto-refresh, Self-refresh capability
Package:
54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62160/H-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Semiconductor
MD56V62160/H
4-Bank
1,048,576-Word 16-Bit SYNCHRONOUS DYNAMIC RAM
Preliminary
Family
Access Time (Max.)
MD56V62160-10
MD56V62160-12
Max.
Frequency
100 MHz
83 MHz
9 ns
14 ns
t
AC2
9 ns
10 ns
t
AC3
MD56V62160H-15
66 MHz
9 ns
9 ns
This version: Mar. 1998
E2G1052-17-X1
Semiconductor
MD56V62160/H
2/28
PIN CONFIGURATION (TOP VIEW)
V
CC
1
V
SS
DQ1
2
V
CC
Q
3
DQ2
4
DQ3
5
V
SS
Q
6
DQ4
7
DQ5
8
V
CC
Q
9
DQ6
10
DQ7
11
V
SS
Q
12
DQ8
13
V
CC
14
LDQM
15
WE
16
CAS
17
RAS
18
CS
19
A13/BA0
20
A12/BA1
21
A10
22
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DQ16
V
SS
Q
DQ15
DQ14
V
CC
Q
DQ13
DQ12
V
SS
Q
DQ11
DQ10
V
CC
Q
DQ9
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A0
23
A1
24
A2
25
32
31
30
A7
A6
A5
54-Pin Plastic TSOP (
II)
(K Type)
A3
26
V
CC
27
29
28
A4
V
SS
Pin Name
Function
System Clock
Clock Enable
Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
CLK
CKE
A0 - A11
RAS
CAS
WE
UDQM, LDQM
DQi
V
CC
V
SS
V
CC
Q
V
SS
Q
Chip Select
CS
Bank Select Address
A12, A13
No Connection
NC
Pin Name
Function
Note:
The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
Semiconductor
MD56V62160/H
3/28
PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 RA11
Column address: CA0 CA7
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
UDQM,
LDQM
Masks the read data of two clocks later when UDQM and LDQM are set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when UDQM and LDQM are set "H" at the "H" edge of the clock signal.
UDQM controls upper byte and LDQM controls lower byte.
Address
DQi
Data inputs/outputs are multiplexed on the same pin.
CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
UDQM and LDQM.
Bank Access pins. These pins are dedicated to select one of 4 banks.
A12, A13
(BA1, BA0)
Semiconductor
MD56V62160/H
4/28
BLOCK DIAGRAM
CLOCK
BUFFER
CLK
CKE
Command
Buffers
CS
RAS
CAS
WE
UDQM
LDQM
Address
Buffers
A0 -
A13
Command
Decoding
Logic
Mode
Register
BANK D
Row Decoders
Word Drivers
Memory
Cells
Column Decoders
Sense Amplifiers
BANK A
BANK B
BANK C
DQ1 - DQ16
Input
Buffers
Input
Data
Register
Output
Buffers
Output
Data
Register
Latency
& Burst
controller
Control
Logic
Row
Address
Latches
& Refresh
Counter
Column
Address
Latches
& Counter
Semiconductor
MD56V62160/H
5/28
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltages referenced to V
SS
)
Parameter
Unit
Symbol
Voltage on Any Pin Relative to V
SS
Rating
V
IN
, V
OUT
0.5 to V
CC
+ 0.5
V
V
CC
Supply Voltage
V
CC
, V
CC
Q
0.5 to 4.6
V
Storage Temperature
T
stg
55 to 150
C
Power Dissipation
P
D
*
1
W
Short Circuit Current
I
OS
50
mA
Operating Temperature
T
opr
0 to 70
C
*: Ta = 25
C
(Voltages referenced to V
SS
= 0 V)
Parameter
Unit
Symbol
Power Supply Voltage
V
CC
, V
CC
Q
Input High Voltage
V
IH
Input Low Voltage
V
IL
Min.
3.0
2.0
0.3
V
V
V
Typ.
3.3
--
--
Max.
3.6
V
CC
+ 0.3
0.8
Recommended Operating Conditions
Capacitance
(V
CC
= 3.3 V 0.3 V, Ta = 25C, f = 1 MHz)
Parameter
Unit
Symbol
Input Capacitance (CLK, CKE,
CS,
RAS, CAS, WE, UDQM, LDQM)
Input/Output Capacitance
(DQ1 - DQ16)
C
IN2
C
OUT
2
2
pF
pF
Input Capacitance (A0 - A13)
C
IN1
2
pF
5
5
7
Min.
Max.
Semiconductor
MD56V62160/H
6/28
DC Characteristics
Parameter
Condition
Version
Unit Note
CKE
Others
-10
-12
Symbol
Output High Voltage
Output Low Voltage
Input Leakage Current
2.4
--
10
V
V
mA
--
--
--
I
OH
= 2 mA
I
OL
= 2 mA
--
V
OH
V
OL
I
LI
--
0.4
10
2.4
--
10
--
0.4
10
Output Leakage Current
10
mA
--
--
I
LO
10 10 10
Min. Max.Min. Max.
Average Power
Supply Current
(Operating)
--
mA
1, 2
CKE V
IH
t
CC
= min
t
RC
= min
No Burst
I
CC
1
145 -- 125
Power Supply
Current (Stand by)
--
mA
3
CKE V
IH
t
CC
= min
I
CC
2
40
--
35
Average Power
Supply Current
(Clock Suspension)
--
mA
2
CKE V
IL
t
CC
= min
I
CC
3S
15
--
15
Power Supply
Current (Burst)
--
mA
1, 2
CKE V
IH
t
CC
= min
I
CC
4
210 -- 180
Power Supply
Current
(Auto-Refresh)
--
mA
2
CKE V
IH
t
CC
= min
t
RC
= min
I
CC
5
185 -- 155
Average Power
Supply Current
(Self-Refresh)
--
mA
CKE V
IL
t
CC
= min
I
CC
6
2
--
2
Average Power
Supply Current
(Power down)
--
mA
CKE V
IL
t
CC
= min
I
CC
7
2
--
2
Average Power
Supply Current
(Active Stand by)
--
mA
3
CKE V
IH
t
CC
= min
I
CC
3
95
--
85
H-15
2.4
--
10
--
0.4
10
10 10
Min. Max.
--
--
--
--
--
--
--
--
120
30
15
160
155
2
2
75
Notes:
1. Measured with outputs open.
2. The address and data can be changed once or left unchanged during one cycle.
3. The address and data can be changed once or left unchanged during two cycles.
Semiconductor
MD56V62160/H
7/28
Mode Set Address Keys
A6
A5
A4
CL
A3
BT
A2
A1
A0
BT = 0
BT = 1
CAS Latency
Burst Type
Burst Length
0
0
0
Reserved
0
Sequential
0
0
0
Reserved Reserved
0
0
1
Reserved
1
Interleave
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved Reserved
1
0
1
Reserved
1
0
1
Reserved Reserved
1
1
0
Reserved
1
1
0
Reserved Reserved
1
1
1
Reserved
1
1
1
Reserved Reserved
Note:
A7, A8, A9, A10, A11, A12 and A13 should stay "L" during mode set cycle.
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and start the system clock.
2. After the V
CC
voltage has reached the specified level, pause for 200 ms or more with
the input kept in NOP state.
3. Issue the precharge all bank command.
4. Apply a CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
Semiconductor
MD56V62160/H
8/28
AC Characteristics
Clock "H" Pulse Time
Clock "L" Pulse Time
Input Setup Time
Input Hold Time
Output Low Impedance
Time from Clock
Output High Impedance
Time from Clock
Output Hold from Clock
RAS Cycle Time
RAS Precharge Time
RAS Active Time
Write Recovery Time
Refresh Time
Power-down Exit Set-up Time
RAS to CAS Delay Time
t
CH
t
CL
t
SI
t
HI
t
RC
t
RP
t
RAS
t
WR
t
REF
t
PDE
t
RCD
t
OLZ
t
OHZ
3
3
3
1
90
30
60
15
--
t
SI
+ 1 CLK
30
3
--
--
--
--
--
--
--
10
5
--
64
--
--
--
8
3
3
3
1.5
115
45
70
24
--
t
SI
+ 1 CLK
35
3
--
--
--
--
--
--
--
10
5
--
64
--
--
--
10
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
RAS to RAS Bank Active
Delay Time
t
RRD
20
--
24
--
ns
Input Level Transition Time
t
T
--
3
--
3
ns
t
OH
3
--
3
--
ns
3
CAS to CAS Delay Time (Min.) l
CCD
1
1
Cycle
1
1
Clock Disable Time from CKE
l
CKE
Cycle
2
2
Data Output High Impedance
Time from UDQM, LDQM
l
DOZ
Cycle
0
0
Data Input Mask Time from
UDQM, LDQM
l
DOD
Cycle
0
0
Data Input Time from Write
Command
l
DWD
Cycle
Data Output High Impedance
Time from Precharge Command
3
3
Active Command Input Time from Mode
Register Set Command Input (Min.)
l
MRD
Cycle
2
2
l
ROH
Cycle
Access Time from
Clock
CL = 3
CL = 2
--
--
9
9
--
--
10
14
ns
ns
3, 4
3, 4
Parameter
MD56V62160-10
MD56V62160-12
Clock Cycles Time
CL = 3
CL = 2
Symbol
t
CC
Min.
10
15
Max.
--
--
Min.
12
17.5
Max.
--
--
Unit
ns
ns
Note
Note 1, 2
2
2
Write Command Input Time
from Output
l
OWD
Cycle
t
AC
3
3
3
--
t
SI
+ 1 CLK
3
--
--
--
--
--
--
--
10
5
--
64
--
--
--
--
--
3
3
--
1
1
2
0
0
3
2
--
--
MD56V62160H-15
Min.
Max.
--
--
2
105
30
70
15
30
24
8
15
15
9
9
1
Semiconductor
MD56V62160/H
9/28
Notes : 1. AC measurements assume that t
T
= 1 ns.
2. The reference level for timing of input signals is 1.4 V.
3. Output load.
Output
Z = 50 W
50 pF
50 W
1.4 V
4. The access time is defined at 1.4 V.
5. If t
T
is longer than 1 ns, then the reference level for timing of input signals is V
IH
and
V
IL
.
Semiconductor
MD56V62160/H
10/28
TIMING WAVEFORM
Read & Write Cycle (Same Bank)
@ CAS Latency = 2, Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
Ra
Ca0
Qa0
t
OH
t
RC
,
CS
t
RP
t
RCD
A12
A10
Rb
Cb0
,
,
,
,
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
t
OHZ
Row Active
Read Command
Precharge Command
Row Active
Write Command
Precharge Command
Ra
Rb
t
WR
t
AC
A13
Semiconductor
MD56V62160/H
11/28
Single Bit Read-Write-Read Cycle (Same Page)
@ CAS Latency = 2, Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
,
,,
Ra
Ca
Qa
CS
A12
A10
Cb
Cc
Db
Qc
Row Active
Read Command
Read Command
Write Command
Precharge Command
t
CH
t
CC
t
CL
t
SI
t
HI
t
SI
t
HI
t
SI
l
CCD
t
HI
t
SI
t
SI
t
HI
Ra
t
HI
t
SI
t
AC
t
OLZ
t
OHZ
,,
t
HI
t
SI
t
OH
High
l
OWD
A13
Semiconductor
MD56V62160/H
12/28
A12
0
Operation
After the end of burst, bank A holds the idle status.
A13
0
0
0
After the end of burst, bank B holds the idle status.
1
1
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B is precharged automatically.
0
0
A10
0
0
1
1
1
After the end of burst, bank C holds the idle status.
0
0
1
After the end of burst, bank D holds the idle status.
1
1
After the end of burst, bank C is precharged automatically.
After the end of burst, bank D is precharged automatically.
1
1
0
0
1
1
*
Notes:
1. When
CS is set "High" at a clock transition from "Low" to "High", all inputs except CKE, UDQM, and
LDQM are invalid.
2. When issuing an active, read or write command, the bank is selected by A12 and A13.
3. The auto precharge function is enabled or disabled by the A10 input when the read or write command
is issued.
A13
0
1
Active, read or write
Bank A
Bank B
A12
0
0
0
1
Bank C
Bank D
1
1
4. When issuing a precharge command, the bank to be precharged is selected by the A10, A12 and A13
inputs.
A12
0
0
1
A13
0
1
0
Operation
Bank A is precharged.
Bank B is precharged.
Bank C is precharged.
A10
0
0
0
1
X
1
X
Bank D is precharged.
All banks are precharged.
0
1
5. The input data and the write command are latched by the same clock (Write latency = 0).
6. The output is forced to high impedance by (1 CLK + t
OHZ
) after UDQM, LDQM entry.
Semiconductor
MD56V62160/H
13/28
Page Read & Write Cycle (Same Bank)
@ CAS Latency = 2, Burst Length = 4
*
Notes:
1. To write data before a burst read ends, UDQM and LDQM should be asserted three cycles prior to the
write command to avoid bus contention.
2. To assert row precharge before a burst write ends, wait t
WR
after the last write data input.
Input data during the precharge input cycle will be masked internally.
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
,
,
,,
Ca0
Cb0
,
CS
,
A12
A10
Cc0
Cd0
Qa0
Read Command
Write Command
Precharge Command
,
t
WR
,
,
,
,
,
,
,
Bank A Active
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
,
,
,
,
,
,
,
Read Command
Write Command
High
l
CCD
*Note2
*Note1
A13
l
OWD
Semiconductor
MD56V62160/H
14/28
Read & Write Cycle with Auto Precharge
@ Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
WE
DQ
UDQM,
LDQM
RAa
,
CS
,,
A12
A10
RDb
CAa
Row Active
(A-Bank)
Row Active
(D-Bank)
A-Bank Precharge Start
D Bank Write with
Auto Precharge
,
,
,,
,
CDb
CAS Latency = 2
DQ
UDQM,
LDQM
CAS Latency = 3
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
,
,
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
A Bank Read with
Auto Precharge
D Bank Precharge
Start Point
High
t
RRD
A-Bank Precharge Start
t
WR
RAa
RDb
A13
Semiconductor
MD56V62160/H
15/28
Bank Interleave Random Row Read Cycle
@ CAS Latency = 2, Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
RAa
CAa
,
,
CS
A12
A10
,
QAa0
,
,
Row Active
(A-Bank)
Row Active
(A-Bank)
Read Command
(C-Bank)
Precharge Command
(C-Bank)
t
RC
RAa
,
,
,
,
t
RRD
RCb
CCb
RAc
CAc
RCb
RAc
QAa1 QAa2 QAa3
QCb0 QCb1 QCb2 QCb3
QAc0
QAc1
QAc2
,
,
,
Read Command
(A-Bank)
Row Active
(C-Bank)
Precharge Command
(A-Bank)
Read Command
(A-Bank)
High
,
,
QAc3
A13
Semiconductor
MD56V62160/H
16/28
Bank Interleave Random Row Write Cycle
@ CAS Latency = 2, Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
,
,
,,
RAa
CAa
CS
A12
A10
,
DAa0
Row Active
(A-Bank)
Precharge Command
(A-Bank)
RAa
RBb
CBb
,
RAc
CAc
DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3
DAc0
DAc1
Write Command
(A-Bank)
Row Active
(B-Bank)
,
,
,
,
,
RAc
RBb
,,
Write Command
(B-Bank)
Precharge
Command
(A-Bank)
Row Active
(A-Bank)
Precharge Command
(B-Bank)
Write Command
(A-Bank)
High
A13
Semiconductor
MD56V62160/H
17/28
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
RAa
CAa
CS
A12
A10
,
QAa0
Row Active
(A-Bank)
Read Command
(A-Bank)
RAa
RCb
CCb
CAc
CCd
QAa1 QAa2 QAa3 QCb0 QCb1 QCb2 QCb3
QAe0 QAe1
Read Command
(A-Bank)
Row Active
(C-Bank)
RCa
Read Command
(C-Bank)
Read Command
(A-Bank)
Read Command
(C-Bank)
,
,
,
,
CAe
QAc0 QAc1 QCd0 QCd1
,
Precharge Command
(A-Bank)
High
l
ROH
*Note1
A13
Bank Interleave Page Read Cycle
@ CAS Latency = 2, Burst Length = 4
*Note:
1.
CS is ignored when RAS, CAS and WE are high at the same cycle.
Semiconductor
MD56V62160/H
18/28
Bank Interleave Page Write Cycle
@ CAS Latency = 2, Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
RBa
CBa
,
CS
A12
A10
DBa0
Row Active
(B-Bank)
Precharge Command
(All Banks)
RBa
,
,
RDb
CDb
CBc
CDd
,
,
DBa1 DBa2 DBa3 DDb0 DDb1 DDb2 DDb3 DBc0 DBc1
Write Command
(B-Bank)
Row Active
(D-Bank)
,
,
RDb
,,
,
,
Write Command
(D-Bank)
Write Command
(B-Bank)
Write Command
(D-Bank)
,
,
,
DDd0
,
,
High
,
A13
Semiconductor
MD56V62160/H
19/28
Bank Interleave Random Row Read/Write Cycle
@ CAS Latency = 2, Burst Length = 4
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
,
,
RAa
CAa
CS
A12
A10
QAa0
Row Active
(A-Bank)
RAa
,
RCb
CCb
,
RAc
QAa1 QAa2 QAa3
Read Command
(A-Bank)
Row Active
(C-Bank)
,
,
Precharge Command
(A-Bank)
,
,
,
,
,
CAc
RAc
RCb
DCb0 DCb1 DCb2 DCb3
QAc0 QAc1 QAc2 QAc3
Write Command
(C-Bank)
Row Active
(A-Bank)
Read Command
(A-Bank)
High
A13
Semiconductor
MD56V62160/H
20/28
Bank Interleave Page Read/Write Cycle
@ CAS Latency = 2, Burst Length = 4
,,
,,
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
,
,
,,
CAa0
QAc3
CS
,
CDb0
CAc0
A12
A10
High
Read Command
(A-Bank)
Write Command
(D-Bank)
Read Command
(A-Bank)
,
,
,,
,
,
,,
DDb3
QAa3
QAa2
QAa1
QAa0
DDb2
DDb1
DDb0
QAc2
QAc1
QAc0
,,
,,
A13
,
,,
Semiconductor
MD56V62160/H
21/28
Clock Suspension & DQM Operation Cycle
@ CAS Latency = 2, Burst Length = 4
*Notes:
1. When Clock Suspension is asserted, the next clock cycle is ignored.
2. When LDQM and UDQM are asserted, the read data after two clock cycles is masked.
3. When LDQM and UDQM are asserted, the write data in the same clock cycle is masked.
4. When LDQM is set High, the input/output data of DQ1 - DQ8 is masked.
When UDQM is set High, the input/output data of DQ9 - DQ16 is masked.
,
CLOCK
Suspension
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ1 - 8
WE
UDQM
,
Ra
CS
,
Ca
Cb
A12
A10
Row Active
,
Qb1
Qb0
Read
Command
Read
Command
Read DQM
Write
Command
CLOCK
Suspension
Write
DQM
Read DQM
,
,
Cc
,
,
,
,
,
,
t
OHZ
Dc2
Dc0
Qa1
Qa0
Qa2
t
OHZ
Write
DQM
*Note1
*Note1
*Note4
Qb1
Qb0
Dc1
Dc0
Qa2
DQ9 - 16
,
LDQM
,
,
*Note4
Qa0
Qa3
*Note2
*Note3
Read
DQM
A13
,
,
,
,
,
Ra
Semiconductor
MD56V62160/H
22/28
Read Interruption by Precharge Command
@ Burst Length = 8
*Note:
1. If row precharge is asserted before burst read ends, then the read data will not output after the second
clock cycle of the precharge command.
WE
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
UDQM,
LDQM
,
,
,,,
CS
Ca
A12
A10
High
Row Active
Read Command
Precharge Command
Qa3
,
,,
Qa2
Qa1
Qa0
DQ
UDQM,
LDQM
,,
,
,
,
,
,,
CAS Latency = 3
CAS Latency = 2
Qa4
Qa3
Qa2
Qa1
Qa0
Qa4
Ra
Qa5
*Note1
*Note1
Ra
A13
Semiconductor
MD56V62160/H
23/28
Power Down Mode
@ CAS Latency = 2, Burst Length = 4
*Notes:
1. When all banks are in precharge state, and if CKE is set low, then the MD56V62160/H enters power-down
mode and maintains the mode while CKE is low.
2. To release the circuit from power-down mode, CKE has to be set high for longer than t
PDE
(t
SI
+ 1 CLK).
Clock
Suspention
Exit
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
CS
A12
A10
Qa2
Qa1
Qa0
t
SI
t
PDE
t
SI
t
SI
,
,
Ra
Ca
,
,
Row Active
Power-down
Entry
Power-down
Exit
Clock
Suspention
Entry
Read
Command
Precharge
Command
,
,
,
*Note1
*Note2
Ra
A13
Semiconductor
MD56V62160/H
24/28
Self Refresh Cycle
,
CLK
0
1
2
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
CS
A12
A10
t
SI
,
,
Hi - Z
Hi - Z
Self
Refresh
Entry
,,,
,
,,,
,
Self
Refresh
Exit
Row
Active
Ra
Ra
BS
A13
,
,,,
,
BS
t
RC
Semiconductor
MD56V62160/H
25/28
Mode Register Set Cycle
CLK
0
1
2
3
4
5
0
1
2
3
4
5
6
7
8
9
10
CKE
RAS
CAS
ADDR
DQ
WE
UDQM,
LDQM
,,
CS
key
Ra
MRS
High
High
Hi - Z
Hi - Z
New Command
Auto Refresh
t
RC
,,
,,
6
11
12
l
MRD
Auto Refresh
Auto Refresh Cycle
Semiconductor
MD56V62160/H
26/28
FUNCTION TRUTH TABLE (Table 1) (1/2)
Current State
1
CS RAS CAS WE BA
ADDR
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
X
BA
CA
L
L
H
H
BA
RA
L
L
H
L
BA
A10
L
L
L
H
X
X
H
X
X
X
X
X
L
H
H
X
X
X
L
H
L
H
BA
CA, A10
L
H
L
L
BA
CA, A10
L
L
H
H
BA
RA
L
L
H
L
BA
A10
L
L
L
X
X
X
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
H
BA
CA, A10
L
H
L
L
BA
CA, A10
L
L
H
H
BA
RA
L
L
H
L
BA
A10
L
L
L
X
X
X
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
H
BA
CA, A10
L
H
L
L
BA
CA, A10
L
L
H
H
BA
RA
L
L
H
L
BA
A10
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
H
BA
CA, A10
L
H
L
L
X
X
L
L
H
X
BA
RA, A10
L
L
L
X
X
X
Idle
Row Active
Read
Write
Read with
Auto Precharge
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
H
BA
CA, A10
L
H
L
L
X
X
L
L
H
X
BA
RA, A10
L
L
L
X
X
X
Write with
Auto Precharge
Action
NOP
NOP
ILLEGAL
2
ILLEGAL
2
Row Active
NOP
4
Auto-Refresh or Self-Refresh
5
NOP
NOP
Read
Write
ILLEGAL
2
Precharge
ILLEGAL
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved
Term Burst, start new Burst Read
Term Burst, start new Burst Write
ILLEGAL
2
Term Burst, execute Row Precharge
ILLEGAL
NOP (Continue Row Active after Burst ends)
NOP (Continue Row Active after Burst ends)
Reserved (Term Burst) --> Row Active
Term Burst, start new Burst Read
Term Burst, start new Burst Write
ILLEGAL
2
Term Burst, execute Row Precharge
ILLEGAL
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL
2
ILLEGAL
NOP (Continue Burst to End and enter Row Precharge)
NOP (Continue Burst to End and enter Row Precharge)
ILLEGAL
2
ILLEGAL
2
ILLEGAL
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
L
L
L
L
OP Code
Mode Register Write
L
Semiconductor
MD56V62160/H
27/28
FUNCTION TRUTH TABLE (Table 1) (2/2)
Notes:
1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs.
2. Illegal to bank in specified state, but may be legal in some cases depending on the state of bank
selection.
3. Satisfy the timing of t
CCD
and t
WR
to prevent bus contention.
4. NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5. Illegal if any bank is not idle.
Current State
1
CS RAS CAS WE BA
ADDR
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
X
BA
CA
L
L
H
H
BA
RA
L
L
H
L
BA
A10
L
L
L
X
X
X
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
X
BA
CA
L
L
H
H
BA
RA
L
L
H
L
BA
A10
L
L
L
X
X
X
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
BA
X
L
H
L
X
BA
CA
L
L
H
H
BA
RA
L
L
H
L
BA
A10
L
L
L
X
X
X
H
X
X
X
X
X
L
H
H
X
X
X
L
H
L
X
X
X
L
L
H
X
X
X
L
L
L
X
X
X
H
X
X
X
X
X
L
H
H
H
X
X
L
H
H
L
X
X
L
H
L
X
X
X
L
L
X
X
X
X
Precharge
Write Recovery
Row Active
Refresh
Mode Register
Access
Action
NOP --> Idle after t
RP
NOP --> Idle after t
RP
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
NOP
4
ILLEGAL
NOP
NOP
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
NOP --> Row Active after t
RCD
NOP --> Row Active after t
RCD
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
2
ILLEGAL
NOP --> Idle after t
RC
NOP --> Idle after t
RC
ILLEGAL
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL
ILLEGAL
ILLEGAL
ABBREVIATIONS
RA = Row Address
BA = Bank Address
NOP = No OPeration command
CA = Column Address
AP = Auto Precharge
Semiconductor
MD56V62160/H
28/28
Current State
(n) CKEn-1
CS RAS CAS WE
ADDR
H
X
X
X
X
X
L
H
X
X
X
X
L
L
H
H
H
X
L
L
H
H
L
X
L
L
H
L
X
X
L
L
L
X
X
X
L
X
X
X
X
X
H
X
X
X
X
X
L
H
X
X
X
X
L
L
H
H
H
X
L
L
H
H
L
X
L
L
H
L
X
X
L
L
L
X
X
X
L
X
X
X
X
X
H
X
X
X
X
X
H
H
X
X
X
X
H
L
H
H
H
X
H
L
H
H
L
X
H
L
H
L
X
X
H
L
L
H
L
X
H
L
L
L
H
X
H
X
X
X
X
X
H
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
Self Refresh
Power Down
All Banks Idle
6
Any State Other
Action
INVALID
Exit Self Refresh --> ABI
Exit Self Refresh --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
6
NOP (Continue power down mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
ILLEGAL
Enter Self Refresh
Refer to Operations in Table 1
Begin Clock Suspend Next Cycle
Enable Clock of Next Cycle
Continue Clock Suspension
CKEn
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
H
L
H
L
(ABI)
than Listed Above
H
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
L
FUNCTION TRUTH TABLE for CKE (Table 2)
Note:
6. Power-down and self refresh can be entered only when all the banks are in an idle state.
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