Semiconductor
MD56V62400/H
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DESCRIPTION
The MD56V62400/H is a 4-bank 4,194,304-word 4-bit synchronous dynamic RAM, fabricated
in Oki's CMOS silicon-gate process technology. The device operates at 3.3 V. The inputs and
outputs are LVTTL compatible.
FEATURES
Silicon gate, quadruple polysilicon CMOS, 1-transistor memory cell
4-bank 4,194,304-word 4-bit configuration
3.3 V power supply,
0.3 V tolerance
Input
: LVTTL compatible
Output
: LVTTL compatible
Refresh : 4096 cycles/64 ms
Programmable data transfer mode
CAS latency (2, 3)
Burst length (2, 4, 8)
Data scramble (sequential, interleave)
CBR auto-refresh, Self-refresh capability
Package:
54-pin 400 mil plastic TSOP (Type II) (TSOPII54-P-400-0.80-K) (Product : MD56V62400/H-xxTA)
xx indicates speed rank.
PRODUCT FAMILY
Semiconductor
MD56V62400/H
4-Bank
4,194,304-Word 4-Bit SYNCHRONOUS DYNAMIC RAM
Preliminary
Family
Access Time (Max.)
MD56V62400-10
MD56V62400-12
Max.
Frequency
100 MHz
83 MHz
9 ns
14 ns
t
AC2
9 ns
10 ns
t
AC3
MD56V62400H-15
66 MHz
9 ns
9 ns
This version: Mar. 1998
E2G1050-17-X1
Semiconductor
MD56V62400/H
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PIN CONFIGURATION (TOP VIEW)
V
CC
1
V
SS
NC
2
V
CC
Q
3
NC
4
DQ1
5
V
SS
Q
6
NC
7
NC
8
V
CC
Q
9
NC
10
DQ2
11
V
SS
Q
12
NC
13
V
CC
14
NC
15
WE
16
CAS
17
RAS
18
CS
19
A13/BA0
20
A12/BA1
21
A10
22
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NC
V
SS
Q
NC
DQ4
V
CC
Q
NC
NC
V
SS
Q
NC
DQ3
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A0
23
A1
24
A2
25
32
31
30
A7
A6
A5
54-Pin Plastic TSOP (
II)
(K Type)
A3
26
V
CC
27
29
28
A4
V
SS
Pin Name
Function
System Clock
Clock Enable
Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply (3.3 V)
Ground (0 V)
Data Output Power Supply (3.3 V)
Data Output Ground (0 V)
CLK
CKE
A0 - A11
RAS
CAS
WE
DQM
DQi
V
CC
V
SS
V
CC
Q
V
SS
Q
Chip Select
CS
Bank Select Address
A12, A13
No Connection
NC
Pin Name
Function
Note:
The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
Semiconductor
MD56V62400/H
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PIN DESCRIPTION
CLK
Fetches all inputs at the "H" edge.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 RA11
Column address: CA0 CA9
RAS
CAS
WE
Functionality depends on the combination. For details, see the function truth table.
DQM
Masks the read data of two clocks later when DQM is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM is set "H" at the "H" edge of the clock signal.
Address
DQi
Data inputs/outputs are multiplexed on the same pin.
CS
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and DQM.
Bank Access pins. These pins are dedicated to select one of 4 banks.
A12, A13
(BA1, BA0)
Semiconductor
MD56V62400/H
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BLOCK DIAGRAM
CLOCK
BUFFER
CLK
CKE
Command
Buffers
CS
RAS
CAS
WE
DQM
Address
Buffers
A0 -
A13
Command
Decoding
Logic
Mode
Register
BANK D
Row Decoders
Word Drivers
Memory
Cells
Column Decoders
Sense Amplifiers
BANK A
BANK B
BANK C
DQ1 - DQ4
Input
Buffers
Input
Data
Register
Output
Buffers
Output
Data
Register
Latency
& Burst
controller
Control
Logic
Row
Address
Latches
& Refresh
Counter
Column
Address
Latches
& Counter
Semiconductor
MD56V62400/H
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(Voltages referenced to V
SS
)
Parameter
Unit
Symbol
Voltage on Any Pin Relative to V
SS
Rating
V
IN
, V
OUT
0.5 to V
CC
+ 0.5
V
V
CC
Supply Voltage
V
CC
, V
CC
Q
0.5 to 4.6
V
Storage Temperature
T
stg
55 to 150
C
Power Dissipation
P
D
*
1
W
Short Circuit Current
I
OS
50
mA
Operating Temperature
T
opr
0 to 70
C
*: Ta = 25
C
(Voltages referenced to V
SS
= 0 V)
Parameter
Unit
Symbol
Power Supply Voltage
V
CC
, V
CC
Q
Input High Voltage
V
IH
Input Low Voltage
V
IL
Min.
3.0
2.0
0.3
V
V
V
Typ.
3.3
--
--
Max.
3.6
V
CC
+ 0.3
0.8
Recommended Operating Conditions
Capacitance
(V
CC
= 3.3 V 0.3 V, Ta = 25C, f = 1 MHz)
Parameter
Unit
Symbol
Input Capacitance (CLK, CKE,
CS,
RAS, CAS, WE, DQM)
Input/Output Capacitance
(DQ1 - DQ4)
C
IN2
C
OUT
2
2
pF
pF
Input Capacitance (A0 - A13)
C
IN1
2
pF
5
5
7
Min.
Max.
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