MK32VT1664A-8YC (98.07.17)
Page 1/11
Semiconductor
MK32VT1664A-8YC
16,777,216 Word x 64 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):
DESCRIPTION
The Oki MK32VT1664A-8YC is a fully decoded, 16,777,216 x 64bit synchronous
dynamic random access memory composed of sixteen 64Mb DRAMs (8Mx8) in TSOP
packages mounted with decoupling capacitors on a 168-pin glass epoxy Dual-in-Line
Package supports any application where high density and large capacity of storage
memory are required, like for example PCs or servers.
FEATURES
16-Meg Word x 64-bit (2Bank 8Byte) organization
168-pin Dual Inline Memory Module
All DQ Pins have 10
Damping Resister
Single 3.3V power supply, 0.3V tolerance
Input
:LVTTL compatible
Output
:LVTTL compatible
Refresh : 4,096 cycles/64 ms
Programmable data transfer mode
/CAS latency (2, 3)
Burst length (1, 2, 4, 8, Full)
Data scramble (sequential, interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
PRODUCT ORGANIZATION
Operation
Access Time (Max.)
Product Name
Frequency (Max.)
t
AC2
t
AC3
MK32VT1664A-8YC
125 MHz
10.0ns
6.0ns
Note. Specification are subject to change without notice.
MK32VT1664A-8YC (98.07.17)
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BLOCK DIAGRAM
/CS0
CKE0
DQMB0
DQMB1
DQ0
DQ7
DQ0
DQ7
DQ8
DQ15
DQMB4
DQ0
DQ7
DQM
CKE
/CS
DQM
CKE
/CS
DQ40
DQ47
DQMB5
DQMB2
DQMB3
DQ0
DQ7
DQ16
DQ23
DQ0
DQ7
DQ24
DQ31
DQMB7
DQ0
DQ7
DQ48
DQ55
DQ0
DQ7
DQ56
DQ63
DQM
CKE
/CS
DQM
CKE
/CS
DQM
CKE
/CS
DQM
CKE
/CS
/CS2
DQMB6
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
/CS1
/CS3
CKE1
DQ32
DQ39
DQ0
DQ7
DQM
CKE
/CS
DQ0
DQ7
DQM
CKE
/CS
10K
Vcc
Vss
Two Decoupling Capacitors
per SDRAM
0.1uF
0.33uF
/RAS,/CAS,/WE
A0-A11,BA0,BA1
1
16
SCL
SDA
A0 A1
A2
SA0 SA1 SA2
Serial PD
CLK2
3.3pF
5
6
CLK0
1
2
CLK3
3.3pF
CLK1
10
11
14
15
7
8
3
4
12
13
16
WP
47K
9
6
10
3
4
9
11
12
15
16
13
14
1
8
7
2
17
5
3.3pF
3.3pF
Note. The Value of all resistors is 10
expect WP and CKE1
MODULE OUTLINE
(Front)
(Back)
1
85
10
94
11
95
40
124
41
125
84
168
MK32VT1664A-8YC (98.07.17)
Page 3/11
PIN CONFIGURATION
Front
Back side
Front side
Back side
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
Vss
85
Vss
43
Vss
127
Vss
2
DQ0
86
DQ32
44
N.C
128
CKE0
3
DQ1
87
DQ33
45
/CS2
129
/CS3
4
DQ2
88
DQ34
46
DQMB2
130
DQMB6
5
DQ3
89
DQ35
47
DQMB3
131
DQMB7
6
Vcc
90
Vcc
48
N.C
132
N.C
7
DQ4
91
DQ36
49
Vcc
133
Vcc
8
DQ5
92
DQ37
50
N.C
134
N.C
9
DQ6
93
DQ38
51
N.C
135
N.C
10
DQ7
94
DQ39
52
N.C
136
N.C
11
DQ8
95
DQ40
53
N.C
137
N.C
12
Vss
96
Vss
54
Vss
138
Vss
13
DQ9
97
DQ41
55
DQ16
139
DQ48
14
DQ10
98
DQ42
56
DQ17
140
DQ49
15
DQ11
99
DQ43
57
DQ18
141
DQ50
16
DQ12
100
DQ44
58
DQ19
142
DQ51
17
DQ13
101
DQ45
59
Vcc
143
Vcc
18
Vcc
102
Vcc
60
DQ20
144
DQ52
19
DQ14
103
DQ46
61
N.C
145
N.C
20
DQ15
104
DQ47
62
N.C
146
N.C
21
N.C
105
N.C
63
CKE1
147
N.C
22
N.C
106
N.C
64
Vss
148
Vss
23
Vss
107
Vss
65
DQ21
149
DQ53
24
N.C
108
N.C
66
DQ22
150
DQ54
25
N.C
109
N.C
67
DQ23
151
DQ55
26
Vcc
110
Vcc
68
Vss
152
Vss
27
/WE
111
/CAS
69
DQ24
153
DQ56
28
DQMB0
112
DQMB4
70
DQ25
154
DQ57
29
DQMB1
113
DQMB5
71
DQ26
155
DQ58
30
/CS0
114
/CS1
72
DQ27
156
DQ59
31
N.C
115
/RAS
73
Vcc
157
Vcc
32
Vss
116
Vss
74
DQ28
158
DQ60
33
A0
117
A1
75
DQ29
159
DQ61
34
A2
118
A3
76
DQ30
160
DQ62
35
A4
119
A5
77
DQ31
161
DQ63
36
A6
120
A7
78
Vss
162
Vss
37
A8
121
A9
79
CLK2
163
CLK3
38
A10
122
BA0
80
N.C
164
N.C
39
BA1
123
A11
81
WP
165
SA0
40
Vcc
124
Vcc
82
SDA
166
SA1
41
Vcc
125
CLK1
83
SCL
167
SA2
42
CLK0
126
N.C
84
Vcc
168
Vcc
Pin Name
Function
Pin Name
Function
Vcc
Power Supply (3.3V)
/WE
Write Enable
Vss
Ground (0V)
DQMB#
Data Input/Output Mask
CLK#
System Clock
DQ#
Data Input/Output
/CS#
Chip Select
WP
Write Protect
CKE#
Clock Enable
SDA
Data I/O for SPD
A0-A11
Address
SCL
CLK input for SPD
BA0,BA1
Bank Select Address
SA#
Socket Position Address for SPD
/RAS
Row Address Strobe
N.C
No Connection
/CAS
Column Address Strobe
MK32VT1664A-8YC (98.07.17)
Page 4/11
SERIAL PRESENCE DETECT
Byte
No.
SPD
Hex Value
Remark
Notes
0
80
Defines the number of bytes written into
SPD memory
128 byte
1
08
Total number of bytes of SPD memory
256 byte
2
04
Fundamental memory type
SDRAM
3
0C
Number of rows
12 rows
4
09
Number of columns
9 columns
5
02
Number of module banks
2 bank
6
40
Data width of this assembly
64 bits
7
00
... Data width continuation
0
8
01
Voltage interface level
LVTTL
9
80
Cycle time (CL=3)
CL=3 t
CC
=8ns
10
60
Access time from CLK (CL=3)
CL=3 t
AC3
=6ns
11
00
DIMM configuration type
None Parity
12
80
Refresh rate / type
Normal / Self
13
08
Primary SDRAM width
x8
14
00
Error checking SDRAM width
15
01
Minimum CLK delay
t
CCD
: 1 CLK
16
8F
Burst lengths supported
1, 2, 4, 8, F
17
04
Number of banks on each SDRAM
4 banks
18
06
/CAS latency
2, 3
19
01
/CS latency
0
20
01
/WE latency
0
21
00
SDRAM module attributes
22
0E
SDRAM device attributes : General
23
C0
Cycle time (CL=2)
CL=2 t
CC2
=12ns
24
A0
Access time from CLK (CL=2)
CL=2 t
AC2
=10ns
25
00
Cycle time (CL=1)
Not support
26
00
Access time from CLK (CL=1)
Not support
27
1E
Minimum ROW pulse width
t
RP
=30ns
28
10
/RAS to /RAS bank delay
t
RRD
=16ns
29
14
/RAS to /CAS delay
t
RCD
=20ns
30
30
Minimum /RAS precharge time
t
RAS
=48ns
31
10
Density of each bank on module
64MB
32
20
Command and address signal input setup time
2ns
33
10
Command and address signal input hold time
1ns
34
20
Data signal input setup time
2ns
35
10
Data signal input hold time
1ns
36-61
00-00
R.F.U
62
12
SPD data revision code
1.2
63
4A
Checksum for byte 0-62
64-71
41, 45, 20, 20, 20, 20, 20, 20
Manufacturer's JEDEC ID code
72
01/06
Manufacturing location
73-90
4D, 4B, 33, 32, 56, 54, 31, 36, 36,
34, 41, 2D, 38, 59, 43, 20, 20, 20
Manufacturer's part number
MK32VT1664A-
8YC
91,92
20,20
Revision code
93-125
00-00
R.F.U
126
64
Intel specification frequency
100MHz
127
F5
Intel specification /CAS latency
CLK0-3, CL=3
128-255
FF-FF
Unused storage locations
MK32VT1664A-8YC (98.07.17)
Page 5/11
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 to Vcc+0.5
V
Vcc supply voltage
Vcc, VccQ
-0.5 to 4.6
V
Storage temperature
Tstg
- 55 to 125
C
Power dissipation
P
D
*
16
W
Short circuit current
I
OS
50
mA
Operating temperature
Topr
0 to 70
C
*: Ta=25
C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
Vcc,VccQ
3.0
3.3
3.6
V
Input high voltage
V
IH
2.0
-
Vcc+0.3
V
Input low voltage
V
IL
-0.3
-
0.8
V
Capacitance
(Vcc = 3.3V
0.3V,Ta = 25C f =1MHz)
Parameter
Symbol
Max.
Unit
Input capacitance(A0-A11,BA0,BA1,/RAS, /CAS,/WE)
C
IN1
98
pF
Input capacitance(/CS0,/CS1,/CS2,/CS3)
C
IN2
34
pF
Input capacitance(DQMB0-DQMB7)
C
IN3
22
pF
Input capacitance(CKE0,CKE1)
C
IN4
58
pF
I/O capacitance(DQ0-DQ63)
C
I/O
25
pF
Input capacitance(CLK0,CLK1,CLK2,CLK3)
C
CLK
50
pF
MK32VT1664A-8YC (98.07.17)
Page 6/11
DC CHARACTERISTICS
(Vcc = 3.3V
0.3V, Ta = 0 to 70C)
Condition
Module Spec.
Parameter
Symbo
l
CKE
Others
Min.
Max.
Unit
Note
Output High Voltage
V
OH
-
I
OH
= -2.0mA
2.4
-
V
Output Low Voltage
V
OL
-
I
OL
= 2.0mA
-
0.4
V
Input Leakage Current
I
LI
-
-
-80
80
uA
Output Leakage
Current
I
LO
-
-
-10
10
uA
Average Power Supply
Current
(Operating)
I
CC
1
CKE
V
IH
t
CC
=min.
t
RC
=min.
No Burst
-
1240
mA
1, 2
Power Supply Current
(Stand by)
I
CC
2
CKE
V
IH
t
CC
=min.
-
480
mA
3
Average Power
Supply Current
(Clock Suspension)
I
CC
3S
CKE
V
IL
t
CC
=min.
-
96
mA
2
Average Power
Supply Current
(Active Stand by)
I
CC
3
CKE
V
IH
,
/CS
V
IH
t
CC
=min.
-
720
mA
3
Power Supply
Current
(Burst)
I
CC
4
CKE
V
IH
t
CC
=min.
-
1560
mA
1, 2
Power Supply
Current
(Auto-Refresh)
I
CC
5
CKE
V
IH
t
CC
=min.
t
RC
=min.
-
1720
mA
2
Average Power
Supply Current
(Self-Refresh)
I
CC
6
CKE
0.2V
t
CC
=min.
-
16
mA
Average Power
Supply Current
(Power down)
I
CC
7
CKE
V
IL
t
CC
=min.
-
32
mA
Notes: 1. Measured with the output open.
2. Address and data can be changed once or not be changed during one cycle.
3. Address and data can be changed once or not be changed during two cycle.
MODE SET ADDRESS KEYS
Write Burst
/CAS Latency
Burst Type
Burst Length
A9
Write Burst
A6
A5
A4
CL
A3
BT
A2
A1
A0
BT=0
BT=1
0
Burst Write
0
0
0
Reserved
0
Sequential
0
0
0
Reserved
Reserved
1
Single bit Write
0
0
1
Reserved
1
Interleave
0
0
1
2
2
0
1
0
2
0
1
0
4
4
0
1
1
3
0
1
1
8
8
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
1
1
1
Full page
Reserved
Note: A7,A8, A10,A11,BA0,BA1 and All should stay "L" during mode set cycle.
MK32VT1664A-8YC (98.07.17)
Page 7/11
POWER ON SEQUENCE
1. With inputs in NOP state, turn on the power supply and enter the system clock.
2. After the Vcc voltage has reached the specified level, take a pause of 200us or more
with the input being NOP.
3. Enter the precharge all bank command.
4. Apply CBR auto-refresh eight or more times.
5. Enter the mode register setting command.
MK32VT1664A-8YC (98.07.17)
Page 8/11
AC CHARACTERISTIC
(Vcc = 3.3V
0.3V, Ta = 0 ~70C)
NOTE 1, 2 .
Parameter
Symbol
Module Spec.
Unit
Note
Min.
Max.
Clock Cycle Time
CL=3
t
CC
8
-
ns
CL=2
12
-
ns
Access Time from Clock
CL=3
t
AC
-
6
ns
3, 4
-
10
ns
3, 4
Clock "H" Pulse Time
t
CH
3
-
ns
Clock "L" Pulse Time
t
CL
3
-
ns
Input Setup Time
t
SI
2
-
ns
Input Hold Time
t
HI
1
-
ns
Output Low Impedance Time from Clock
t
OLZ
3
-
ns
Output High Impedance Time from Clock
t
OHZ
-
8
ns
Output Hold from Clock
t
OH
3
-
ns
3
/RAS Cycle Time
t
RC
80
-
ns
/RAS Precharge Time
t
RP
30
-
ns
/RAS Active Time
t
RAS
48
100,000
ns
/RAS to /CAS Delay Time
t
RCD
20
-
ns
Write Recovery Time
t
WR
8
-
ns
/RAS to /RAS Bank Active Delay Time
t
RRD
16
-
ns
Refresh Time
t
REF
-
64
ms
Power-down Exit Set-up Time
t
PDE
t
SI
+1CLK
-
ns
Input Level Transition Time
t
T
-
3
ns
/CAS to /CAS Delay Time (Min)
I
CCD
1
Cycle
Clock Disable Time from CKE
I
CKE
1
Cycle
Data Output High Impedance Time from DQMB
I
DOZ
2
Cycle
Data Input Mask Time from DQMB
I
DOD
0
Cycle
Data Input Time from Write Command
I
DWD
0
Cycle
Data Output High Inpedance
CL=3
I
ROH
3
Cycle
Time from Precharge Command
CL=2
2
Cycle
Active Command Input Time from MODE
Register Set Command Input (Min)
I
MRD
2
Cycle
Write Command Input Time from Output
t
OWD
2
Cycle
NOTES:
1) AC measurements assume t
T
=1ns.
2) The reference level for timing of input signals is 1.4V.
3) This parameter is measured with a load circuit equivalent to 1 TTL load and 50pF
(R
Load
is 50ohm).
4) An access time is measured at 1.4V.
5) If t
T
is longer than 1ns, the reference level for timing of input signals are V
IH
and V
IL
.
OUTPUT
50pF
OUTPUT LOAD
50
1.4v
MK32VT1664A-8YC (98.07.17)
Page 9/11
FUNCTION TRUTH TABLE (Table1)(1/2)
Current State
/CS
/RAS
/CAS
/WE
BA
ADDR
Action
Idle
H
X
X
X
X
X
NOP
L
H
H
H
X
X
NOP
L
H
H
L
BA
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
Row Active
L
L
H
L
BA
A10
NOP
4
L
L
L
H
X
X
Auto-Refresh or Self-Refresh
5
L
L
L
L
L
OP Code
Mode Register write
Row Active
H
X
X
X
X
X
NOP
L
H
H
X
X
X
NOP
L
H
L
H
BA
CA, A10
Read
L
H
L
L
BA
CA, A10
Write
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
Precharge
L
L
L
X
X
X
ILLEGAL
Read
H
X
X
X
X
X
NOP(Continue Row Active after Burst ends)
L
H
H
H
X
X
NOP(Continue Row Active after Burst ends)
L
H
H
L
BA
X
Burst Stop
L
H
L
H
BA
CA, A10
Term Burst,start new Burst Read
3
L
H
L
L
BA
CA, A10
Term Burst,start new Burst Write
3
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
Term Burst,execute Row Precharge
L
L
L
X
X
X
ILLEGAL
Write
H
X
X
X
X
X
NOP(Continue Row Active after Burst ends)
L
H
H
H
X
X
NOP(Continue Row Active after Burst ends)
L
H
H
L
BA
X
Burst Stop
L
H
L
H
BA
CA, A10
Term Burst,start new Burst Read
3
L
H
L
L
BA
CA, A10
Term Burst,start new Burst Write
3
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
Term Burst,execute Row Precharge
3
L
L
L
X
X
X
ILLEGAL
Read with
H
X
X
X
X
X
NOP(Continue Burst to End and enter Row Precharge)
Auto Precharge
L
H
H
H
X
X
NOP(Continue Burst to End and enter Row Precharge)
L
H
H
L
BA
X
ILLEGAL
2
L
H
L
H
BA
CA, A10
ILLEGAL
2
L
H
L
L
X
X
ILLEGAL
L
L
H
X
BA
RA, A10
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
Write with
H
X
X
X
X
X
NOP(Continue Burst to End and enter Row Precharge)
Auto Precharge
L
H
H
H
X
X
NOP(Continue Burst to End and enter Row Precharge)
L
H
H
L
BA
X
ILLEGAL
2
L
H
L
H
BA
CA, A10
ILLEGAL
2
L
H
L
L
X
X
ILLEGAL
L
L
H
X
BA
RA, A10
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
MK32VT1664A-8YC (98.07.17)
Page 10/11
FUNCTION TRUTH TABLE (Table1)(2/2)
Current State
/CS
/RAS
/CAS
/WE
BA
ADDR
Action
Precharge
H
X
X
X
X
X
NOP
Idle after t
RP
L
H
H
H
X
X
NOP
Idle after t
RP
L
H
H
L
BA
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
NOP
4
L
L
L
X
X
X
ILLEGAL
Write
H
X
X
X
X
X
NOP
Recovery
L
H
H
H
X
X
NOP
L
H
H
L
BA
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
Row Active
H
X
X
X
X
X
NOP Row Active after t
RCD
L
H
H
H
X
X
NOP Row Active after t
RCD
L
H
H
L
BA
X
ILLEGAL
2
L
H
L
X
BA
CA
ILLEGAL
2
L
L
H
H
BA
RA
ILLEGAL
2
L
L
H
L
BA
A10
ILLEGAL
2
L
L
L
X
X
X
ILLEGAL
Refresh
H
X
X
X
X
X
NOP
Idle after t
RC
L
H
H
X
X
X
NOP
Idle after t
RC
L
H
L
X
X
X
ILLEGAL
L
L
H
X
X
X
ILLEGAL
L
L
L
X
X
X
ILLEGAL
Auto Resister
H
X
X
X
X
X
NOP
Access
L
H
H
H
X
X
NOP
L
H
H
L
X
X
ILLEGAL
L
H
L
X
X
X
ILLEGAL
L
L
X
X
X
X
ILLEGAL
ABBREVIATIONS
RA = Row Address
BA = Bank Address
NOP = No Operation command
CA = Column Address AP = Auto Precharge
Notes:
1.
All inputs will be enabled when CKE is set high for at least 1 cycle prior to the inputs.
2.
Illegal to bank in specified state, but may be legal in some cases depending on the state of
bank selection.
3.
Satisfy the timing of t
CCD
and t
WR
to prevent bus contention.
4.
NOP to bank precharging or in idle state. Precharges activated bank by BA or A10.
5.
Illegal if any bank is not idle.
MK32VT1664A-8YC (98.07.17)
Page 11/11
FUNCTION TRUTH TABLE (CKE) (Table2)
Current State(n)
CKEn-1
CKEn
/CS
/RAS
/CAS
/WE
ADDR
Action
Self Refresh
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Self Refresh
ABI
L
H
L
H
H
H
X
Exit Self Refresh
ABI
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
L
X
X
X
ILLEGAL
L
L
X
X
X
X
X
NOP(Maintain Self Refresh)
Power Down
H
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
Exit Power Down
ABI
L
H
L
H
H
H
X
Exit Power Down
ABI
L
H
L
H
H
L
X
ILLEGAL
L
H
L
H
L
X
X
ILLEGAL
L
H
L
X
X
X
X
ILLEGAL
6
L
L
X
X
X
X
X
NOP(Continue power down mode)
All Banks idle
6
H
H
X
X
X
X
X
Refer to Table 1
(ABI)
H
L
H
X
X
X
X
Enter Power Down
H
L
L
H
H
H
X
Enter Power Down
H
L
L
H
H
L
X
ILLEGAL
H
L
L
H
L
X
X
ILLEGAL
H
L
L
L
H
L
X
ILLEGAL
H
L
L
L
L
H
X
Enter Self Refresh
H
L
L
L
L
L
X
ILLEGAL
L
L
X
X
X
X
X
NOP
Any State
H
H
X
X
X
X
X
Refer to Operations in Table 1
Other than
H
L
X
X
X
X
X
Begin Clock Suspend Next Cycle
Listed Above
L
H
X
X
X
X
X
Enable Clock of Next Cycle
L
L
X
X
X
X
X
Continue Clock Suspension
Notes:
6.
Power-down and self refresh can be entered only when all the banks are in an idle state.
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