MK32VT832-10YC
98.07.21
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Semiconductor
MK32VT832-10YC
8,388,608 Word x 32 Bit SYNCHRONOUS DYNAMIC RAM MODULE (2BANK):
DESCRIPTION
The Oki MK32VT832-10YC is a fully decoded, 8,388,608 x 32bit synchronous dynamic
random access memory composed of four 64Mb DRAMs (4Mx16) in TSOP packages
mounted with decoupling capacitors on a 100-pin glass epoxy Dual-in-Line Package
supports any application where high density and large capacity of storage memory are
required, like for example PCs or servers.
FEATURES
8-Meg Word x 32-Bit (2Bank 4 Byte) organization
100-pin Dual Inline Memory Module
10
Damping Resister for DQ and CLK Pins
Single 3.3V power supply, 0.3V tolerance
Input
:LVTTL compatible
Output
:LVTTL compatible
Refresh : 4,096 cycles/64 ms
Programmable data transfer mode
/CAS latency (2, 3)
Burst length (2, 4, 8)
Data scramble(sequential, interleave)
/CAS before /RAS auto-refresh, Self-refresh capability
Serial Presence Detect (SPD) With EEPROM
PRODUCT ORGANIZATION
Operation
Access Time (Max.)
Product Name
Frequency (Max.)
t
AC2
t
AC3
MK32VT832 - 10YC
100 MHz
13.0ns
9.0ns
Note. Specification are subject to change without notice.
MK32VT832-10YC
98.07.21
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BLOCK DIAGRAM
2
CLK0
1
CLK1
/CS0
CKE0
UDQM
DQ0
DQ7
LDQM
CKE
/CS
1
DQ15
DQ8
LDQM
UDQM
CKE
/CS
2
DQ0
DQ7
DQ15
DQ8
4
3
10pF
/CS2
/CS3
/CS1
CKE1
DQMB0
DQMB1
DQ0
DQ7
DQ24
DQ31
DQMB2
LDQM
DQ16
DQ23
DQMB3
DQ0
DQ7
UDQM
CKE
/CS
DQ8
DQ15
Vcc
Vss
SDRAMs
0.22
F x2
/RAS,/CAS,/WE
A0-A11,BA0,BA1
1
4
SCL
SDA
A0 A1 A2
Serial PD
3
5
DQ15
DQ8
UDQM
LDQM
CKE
/CS
4
DQ0
DQ7
DQ15
DQ8
SA0 SA1 SA2
10pF
Note. The Value of all resistors is 10
.
MODULE OUTLINE
(Front)
(Back)
1
51
6
56
7
57
22
72
23
73
50
100
MK32VT832-10YC
98.07.21
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PIN CONFIGURATION
Front side
Back side
Front side
Back side
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
51
VSS
26
VSS
76
VSS
2
DQ0
52
DQ8
27
CKE0
77
CKE1
3
DQ1
53
DQ9
28
/WE
78
NC
4
DQ2
54
DQ10
29
/CS0
79
/CS1
5
DQ3
55
DQ11
30
/CS2
80
/CS3
6
VCC
56
VCC
31
VCC
81
VCC
7
DQ4
57
DQ12
32
NC
82
NC
8
DQ5
58
DQ13
33
NC
83
NC
9
DQ6
59
DQ14
34
NC
84
NC
10
DQ7
60
DQ15
35
NC
85
NC
11
DQMB0
61
DQMB1
36
VSS
86
VSS
12
VSS
62
VSS
37
DQMB2
87
DQMB3
13
A0
63
A1
38
DQ16
88
DQ24
14
A2
64
A3
39
DQ17
89
DQ25
15
A4
65
A5
40
DQ18
90
DQ26
16
A6
66
A7
41
DQ19
91
DQ27
17
A8
67
A9
42
VCC
92
VCC
18
A10
68
BA0
43
DQ20
93
DQ28
19
BA1
69
A11
44
DQ21
94
DQ29
20
NC
70
NC
45
DQ22
95
DQ30
21
VCC
71
VCC
46
DQ23
96
DQ31
22
NC
72
/RAS
47
VSS
97
VSS
23
NC
73
/CAS
48
SDA
98
SA0
24
NC
74
NC
49
SCL
99
SA1
25
CLK0
75
CLK1
50
VCC
100
SA2
Pin Name
Function
Pin Name
Function
VCC
Power Supply (3.3V)
/WE
Write Enable
VSS
Ground (0V)
DQMB#
Data Input / Output Mask
CLK#
System Clock
DQ#
Data Input / Output
/CS#
Chip Select
SDA
Data I/O for SPD
CKE#
Clock Enable
SCL
CLK input for SPD
A0-A11
Address
SA#
Socket Position Address for SPD
BA0, BA1
Bank Select Address
NC
No Connection
/RAS
Row Address Strobe
/CAS
Column Address Strobe
MK32VT832-10YC
98.07.21
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SERIAL PRESENCE DETECT
Byte
No.
SPD
Hex Value
Remark
Notes
0
80
Defines the number of bytes written into
128 byte
SPD memory
1
08
Total number of bytes of SPD memory
256 byte
2
04
Fundamental memory type
SDRAM
3
0C
Number of rows
12 rows
4
08
Number of columns
8 columns
5
02
Number of module banks
2 bank
6
20
Data width of this assembly
32 bits
7
00
... Data width continuation
0
8
01
Voltage interface level
LVTTL
9
A0
Cycle time (CL=3)
CL=3 t
CC
=10ns
10
90
Access time from CLK (CL=3)
CL=3 t
AC3
=9ns
11
00
DIMM configuration type
None Parity
12
80
Refresh rate / type
Normal / Self
13
10
Primary SDRAM width
x16
14
00
Error checking SDRAM width
15
01
Minimum CLK delay
t
CCD
: 1 CLK
16
0E
Burst lengths supported
2, 4, 8
17
04
Number of banks on each SDRAM
4 banks
18
06
/CAS latency
2, 3
19
01
/CS latency
0
20
01
/WE latency
0
21
00
SDRAM module attributes
22
06
SDRAM device attributes : General
23
F0
Cycle time (CL=2)
CL=2 t
CC2
=15ns
24
90
Access time from CLK (CL=2)
CL=2 t
AC2
=9ns
25
00
Cycle time (CL=1)
Not support
26
00
Access time from CLK (CL=1)
Not support
27
1E
Minimum ROW pulse width
t
RP
=30ns
28
14
/RAS to /RAS bank delay
t
RRD
=20ns
29
1E
/RAS to /CAS delay
t
RCD
=30ns
30
3C
Minimum /RAS precharge time
t
RAS
=60ns
31
08
Density of each bank on module
32MB
32
30
Command and address signal input setup time
3ns
33
10
Command and address signal input hold time
1ns
34
30
Data signal input setup time
3ns
35
10
Data signal input hold time
1ns
36-61
00-00
Superset Information
R.F.U
62
02
SPD data revision code
02
63
3A
Checksum for byte 0-62
64-71
41,45,20,20,20,20,20,20
Manufacturer's JEDEC ID code
72
01 / 06
Manufacturing location
73-90
4D,4B,33,32,56,54,38,33,32,
2D,31,30,59,43,20,20,20,20
Manufacturer's part number
MK32VT832-10YC
91, 92
20, 20
Revision code
93-125
00-00
R.F.U
126
66
Intel specification frequency
66MHz
127
06
Intel specification /CAS latency
CL=2,3
128-255
FF-FF
Unused storage locations
MK32VT832-10YC
98.07.21
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
OUT
-0.5 to Vcc+0.5
V
Vcc supply voltage
Vcc, VccQ
-0.5 to 4.6
V
Storage temperature
Tstg
- 55 to 150
C
Power dissipation
P
D
*
4
W
Short circuit current
I
OS
50
mA
Operating temperature
Topr
0 to 70
C
*: Ta=25
C
Recommended Operating Conditions
(Voltages referenced to Vss = 0V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
Vcc, VccQ
3.0
3.3
3.6
V
Input high voltage
V
IH
2.0
-
Vcc+0.3
V
Input low voltage
V
IL
-0.3
-
0.8
V
Capacitance
(Vcc=3.3V
0.3V, Ta=25 C f=1MHz)
Parameter
Symbol
Max.
Unit
Input capacitance (A0-A11, BA0, BA1, /RAS, /CAS, /WE)
C
IN1
27
pF
Input capacitance (/CS0-/CS3)
C
IN2
16
pF
Input capacitance (DQMB0-DQMB3)
C
IN3
16
pF
Input capacitance (CKE0,CKE1)
C
IN4
16
pF
I/O capacitance (DQ0-DQ32)
C
I/O
20
pF
Input capacitance (CLK0, CLK1)
C
CLK
25
pF
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