ML60851A
Semiconductor
1/44
GENERAL DESCRIPTION
The ML60851A is a general purpose Universal Serial Bus (USB) device controller. The ML60851A
provides a USB interface, control/status block, application interface, and FIFOs. The FIFO interface
and two types of transfer have been optimized for BulkOut devices such as printers and BulkIn
devices such as digital still cameras and image scanners. In addition, Mass Storage devices are
also applicable to this device.
FEATURES
USB 1.0 compliant
Built-in USB transceiver circuit
Full-speed (12 Mb/sec) support
Supports printer device class, image device class, and Mass Storage device class
Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer
Built-in FIFOs for control transfer
Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)
Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO)
One 64-byte FIFO
Two 64-byte FIFOs
Built-in FIFO for interrupt transfer
One 8-byte FIFO
Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint
address
Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer
Supports 8 bit/16 bit DMA transfer
V
CC
is 3.0 V to 3.6 V
Supporting dual power supply enables 5 V application interface
Built-in 48 MHz oscillator circuit
Package options:
44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML60851AGA)
44-pin plastic TQFP (TQFP44-P-1010-0.80-K) (Product name: ML60851ATB)
Semiconductor
ML60851A
USB Device Controller
E2N0026-18-Y3
This version: Nov. 1998
Preliminary
ML60851A
Semiconductor
2/44
BLOCK DIAGRAM
48 MHz
XIN
XOUT
D+
D
USB Bus
Oscillator
USB
Transceiver
DPLL
Protocol
Engine
Status/Control
Endpoint FIFO/
8-byte Setup Register
Application
Interface
Application
Module
(Local MCU)
A7:A0
D15:D0
CS, WR, RD
RESET
INTR
DREQ
DACK
ML60851A
ML60851A
Semiconductor
3/44
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
23
24
25
26
27
28
29
30
31
32
33
D+
D
V
CC3
TEST1
TEST2
XIN
XOUT
CS
RD
WR
RESET
INTR
D15
D14
D13
D12
V
SS
V
CC5
D11
D10
D9
D8
ALE
ADSEL
A7
A6
A5
A4
A3
A2
A1
A0
DACK
DREQ
AD7
AD6
AD5
AD4
V
SS
V
CC5
AD3
AD2
AD1
AD0
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
44-Pin Plastic TQFP
44-Pin Plastic QFP
1
2
3
4
5
6
7
8
9
10
11
23
24
25
26
27
28
29
30
31
32
33
D+
D
V
CC3
TEST1
TEST2
XIN
XOUT
CS
RD
WR
RESET
INTR
D15
D14
D13
D12
V
SS
V
CC5
D11
D10
D9
D8
ALE
ADSEL
A7
A6
A5
A4
A3
A2
A1
A0
DACK
DREQ
AD7
AD6
AD5
AD4
V
SS
V
CC5
AD3
AD2
AD1
AD0
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
ML60851A
Semiconductor
4/44
PIN DESCRIPTION
Pin
1, 2
6, 7
13 to 16,
19 to 22
35 to 38,
41 to 44
25 to 32
8
9
10
12
34
33
23
24
11
Symbol
Type
I/O
--
I/O
I/O
I
I
I
I
O
O
I
I
I
I
Description
D+, D
USB data
Pin for external crystal oscillator
Data bus (MSB)
Data bus (LSB)/address input
Address input
Chip select signal input pin. LOW active
Read signal input pin. LOW active
Write signal input pin. LOW active
Interrupt request signal output pin
DMA request output pin
DMA acknowledge signal input pin
Address latch enable signal input pin
Address input mode select input pin. "H": address/data multiplex
System Reset signal input pin. LOW active
XIN, XOUT
D15:D8
AD7:AD0
A7:A0
CS
RD
WR
INTR
DREQ
DACK
ALE
ADSEL
RESET
4, 5
I
Test Pins (normally "L")
TEST1, 2
ML60851A
Semiconductor
5/44
INTERNAL REGISTERS
Addresses and Names of Registers
A5:A0
A7, A6
Read
Address
A7, A6
Write
Register name
Device Address Register
Device State Register
Packet Error Register
Receive FIFO Register
Transmit FIFO Register
Endpoint Packet-Ready Register
Endpoint 0 Receive-Byte Count Register
Endpoint 1 Receive-Byte Count Register
Endpoint 2 Receive-Byte Count Register
Flash Transmit FIFO
System Control
bmRequestType Setup Register
bRequest Setup Register
wValue LSB Setup Register
wValue MSB Setup Register
wIndex LSB Setup Register
wIndex MSB Setup Register
wLength LSB Setup Register
wLength MSB Setup Register
Assertion Select Register
Interrupt Enable Register
Interrupt Status Register
DMA Control Register
DMA Interval Register
Endpoint 0 Receive Control Register
Endpoint 0 Receive General Register
Endpoint 0 Receive Payload Register
Reserved
Endpoint 1 Control Register
Endpoint 1 General Register
Endpoint 1 Payload Register
Reserved
01b
01b
--
--
--
01b
--
--
--
01b
01b
--
--
--
--
--
--
--
--
01b
01b
--
01b
01b
--
--
--
01b
--
01b
01b
01b
--
11b
11b
11b
11b
11b
11b
11b
11b
11b
--
--
11b
11b
11b
11b
11b
11b
11b
11b
11b
11b
11b
11b
11b
--
11b
11b
11b
--
11b
11b
11b
--
00h
01h
02h
03h
04h
08h
09h
0Ah
0Bh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
Reserved
PDF 
ZIP