Semiconductor
ML63293
Preliminary
4-Bit Microcontroller with Built-in LCD Driver ( 68SEG.
32COM. ) and Melody Circuit
1 of 5
This version : Feb.10,1999
GENERAL DESCRIPTION
The ML63293 is a CMOS 4-bit microcontroller with built-in LCD driver and Melody circuit.
The ML63293 is an M63xxx series mask ROM-version product of OLMS-63K family, which employs
Oki's original CPU core nX-4/250.
The ML63293 contains 64K-word program memory, 3K-nibble data memory, 4-bit input port, 16-bit
output ports, 24-bit input/output port, LCD driver for up to 2176 segments, and melody circuit.
The ML63Q290 is the flash EEPROM version of ML63293.
The ML63Q290 is used to evaluate the software development.
APPLICATION
The ML63293 is suitable for applications such as games, toys, watches, etc. which are provided with
an LCD display and Melody output.
FEATURES
Extensive instruction set
408 instructions
Transfer, rotate, increment,/decrement, arithmetic operations, comparison, logic operations,
mask operations, bit operations, ROM table reference, external memory transfer, stack
operations, flag operations, jump, conditional branch, call / return, control.
Wide variety of addressing modes
Indirect addressing of four data memory types, with current bank register, extra bank register,
HL register and XY register.
Data memory bank internal direct addressing mode.
Processing speed
2 clocks per machine cycle, with most instructions executed in 1 machine cycle.
Minimum instruction execution time : 61
s ( @32.768kHz system clock )
1
s ( @2MHz system clock )
Clock generation circuit
Low-speed clock
: Crystal oscillation or RC oscillation selected with mask
option ( 30k to 80kHz )
High-speed clock
: Ceramic oscillation or RC oscillation selected with
software ( 2MHz max. )
The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
Semiconductor
ML63293
Preliminary Ver.1.1
Feb.10,1999
2 of 5
Program memory space
64K words
Basic instruction length is 16 bits / 1 word
Data memory space
3K nibbles
External data memory space
64K bytes ( expandable by using an I/O port )
Stack level
Call stack level
: 16 levels
Register stack level
: 16 levels
I/O ports
Input ports
: Selectable as input with pull-up resistance/ input with pull-down
resistance / high-impedance input
Output ports
: Selectable as P-channel open drain output / N-channel open drain
output / CMOS output / high-impedance output
Input-output ports
: Selectable as input with pull-up resistance / input with pull-down
resistance / high-impedance input
Selectable as P-channel open drain output / N-channel open drain
output / CMOS output / high-impedance output
Can be interfaced to external devices having different power supplies.
Number of ports:
Input ports
: 4bits
( 1port
4bits )
Output ports
: 16bits ( 4ports
4bits )
Input-output ports : 24bits ( 6ports
4bits )
Melody output function
Melody sound frequency
: 529 to 2979Hz
Tone length
: 63 varieties
Tempo
: 15 varieties
Melody data
: Stored in program memory
Buzzer driver signal output
: 4kHz
LCD driver
Number of segments
: 2176 segments max. ( 68seg.
32com. )
Duty
: Selectable as 1/2,1/4,1/6,1/8,1/10,1/12,1/14.1/16,1/18,1/20,
1/22,1/24,1/26,1/28,1/30, 1/32
Bias
: Selectable as 1/5 or 1/6 ( internal Voltage regulator )
Frame frequency
: 64 Hz
Contrast
: 8 levels
Display modes
: Selectable as all-ON mode, all-OFF mode, power down mode,
and normal display mode
Semiconductor
ML63293
Preliminary Ver.1.1
Feb.10,1999
3 of 5
Multiplier / divider circuits
Multiplier
: ( 8 bits )
( 8 bits )
Product ( 16bits )
Divider
: ( 16 bits )
/
( 8 bits )
Quotient ( 16bits ), Remainder ( 8 bits )
System reset function
System reset by RESET pin
System reset by power-on detection
System reset by detection that low-speed clock has stopped oscillation
Battery check
Function that detects battery low voltage
Selection of judgment voltage by software ( LD1 and LD0 bit settings of BLDCON )
LD1
LD0
Judgement voltage ( V )
Comments
1
0
1.80
0.10
Ta=25
C
1
1
2.40
0.10
Ta=25
C
Timers and Counter
8-bit timer
: 4 channels
Selectable as auto-reload mode, capture mode,
clock frequency measurement mode
Watchdog timer
: 1 channel
100Hz timer
: 1 channels
1/100 sec. Measurement possible
15-bit time-base counter
: 1Hz, 2Hz, 4Hz, 8Hz, 16Hz, 32Hz, 64Hz, and 128Hz
signals
can be read
Serial port
Mode
: Selectable as UART mode, synchronous mode
UART communication speed
: 1200 bps, 2400 bps, 4800 bps, 9600bps
Clock frequency in synchronous mode :
Internal clock mode (32.768kHz ), External clock frequency
Data length
: 5 to 8 bits
Shift register
Shift clock
: System clock
1,
1/2,
Timer 1 overflow ( 16-bit timer mode ), External clock
Data length
: 8 bits
Interrupt sources
External interrupt
: 5
Internal interrupt
: 14
Semiconductor
ML63293
Preliminary Ver.1.1
Feb.10,1999
4 of 5
Operating temperature
- 20 to +70
C
Operating voltage
1.8 to 3.5V
Shipping products
Chip ( 169 pads )
: ( Product name : ML63293 - xxx )
176-pin flat package (176LQFP )
LQFP176-P-2424-0.50-BK
: ( Product name : ML63293 - xxxUA )
xxx indicates a ROM code number.
Semiconductor
ML63293
Preliminary Ver.1.1
Feb.10,1999
5 of 5
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function.
nX-4/250
TIMING
CON-
TROL
CBR
EBR
H
L
X
Y
RA
MIE
A
INSTRUCTION
DECODER
IR
BUS
CON-
TROL
ROM
64KW
SP
RSP
C
G
Z
STACK
CAL.S:16-level
REG.S:16-level
PC
ALU
RAM
3KN
INT293
TBC
RST
TST
XT0
XT1
OSC0
OSC1
OSC
RESET
TM0CAP/TM1CAP*
TIMER
8bit (4ch)
TM0OVF/TM1OVF*
T02CK*
T13CK*
SIO
RXC*
TXC*
MELODY
MD
V
DDH
BACK
UP
V
DD
INT
4
RXD*
LCD
&
DSPR
COM1 - 32
INT
4
TST2
DATA BUS
SEG0 - 67
BLD
WDT
INT
1
TST1
CB1
CB2
MDB
100HzTC
INT
1
V
DD1
BIAS
V
DD2
V
DD3
V
DD4
V
DD5
C1
C2
V
DDI
V
SS
INPUT
PORT
INT
1
I/O
PORT
INT
4
INT
1
INT
2
MULDIV
TXD*
SFT
SCLK*
SIN*
SOUT*
INT
1
V
DDL
V
DD6
P8.0 - P8.3
P9.0 - P9.3
PA.0 - PA.3
PB.0 - PB.3
PC.0 - PC.3
PE.0 - PE.3
P0.0 - P0.3
OUTPUT
PORT
P4.0 - P4.3
P5.0 - P5.3
P6.0 - P6.3
P7.0 - P7.3
EXTMEM
64KB
RD*
WR*
D0 - D7*
A0 - A15*
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