Audio Controllers
ML675200/ML67Q5200
Digital Audio Controller
Description
The Oki ML675200 and ML67Q5200 Application Specific Standard Products (ASSP) devices are targeted at the growing
market for applications using the MP3/WMA audio-processing compression protocols. Available in two versions, ROM-
less or Flash ROM, the ML675200 and ML67Q5200 devices incorporate an advanced dual processor core architecture
featuring an ARM7TDMITM 32-bit RISC CPU core and a TeakTM 16-bit DSP core.
The CPU-DSP architecture offers system developers both performance and flexibility. The ARM7TDMI RISC core pro-
vides 32-bit performance for application level software with access to general purpose I/O. The DSP core offers the nu-
merical processing power dedicated to repetitive tasks such as MP3/WMA decoding.
In addition to the two processor cores, the ML675200 and ML67Q5200 devices offer a wide variety of integrated pe-
ripherals, allowing system designers to implement a complete MP3/WMA system requiring minimum external devices.
Among these useful features are a USB 1.1 device controller, 32 Kbytes of SRAM, serial UART ports, GPIO, timers, and
analog channels. Other powerful features include a 4-channel DMA controller for efficient data movement, a PLL circuit,
a built-in controller for external memory, and a built-in voice Codec.
Features
ARM7TDMI 32-bit RISC CPU
30 MHz CPU frequency, 60 MHz DSP frequency
256 Kbyte internal Flash ROM (ML67Q5200)
32 Kbyte internal RAM
Audio codec: MP3/WMA decoder
Voice codec: 4-bit ADPCM2
4-channel DMA controller
4-channel A/D converter
USB controller (version 1.1)
Applications
Digital audio players (Portable MP3/WMA player, etc.)
Educational toys
Personal Digital Assistants (PDA)
Home audio systems
ML675200/Q5200 Digital Audio Controllers
Part Number
Clock Frequency
Built-in Flash Size
Packages
ML675200-LA
30 MHz CPU,
60 MHz DSP
None
(External Max 1 Mbyte)
144-pin plastic LFBGA (P-LFBGA144-1111-0.80)
ML67Q5200-NLA
30 MHz CPU,
60 MHz DSP
256 KB
144-pin plastic LFBGA (P-LFBGA144-1111-0.80)
ML675200/ML67Q5200
2
Oki Semiconductor
Block Diagram
AHB/APB
Bridge
Memory Controller
TIC
Interrupt
Controller
AMBA AHB
AMBA APB Bus
CPU (PLAT-7D)
SDRAM Contr.
Extended
Interrupt Cont.
RAM
32 Kb
I2C
1ch
AHB APB
Bridge
TXD0
RXD0
OSC0
OSC1_N
OSC2
OSC3_N
CLKG
TCKA
TMSA
TRSTA_N
TDIA
TDOA
Expanded Peripheral Bus (AMBA APB)
Flash ROM
256 kB
[1]
ARM7TDMI
AHB Bridge
Cache Cont.
Unified
Cache
Arbiter
System
TIMER
UART
System
Controller
EXINT0
EXINT1
EXINT3
USB Device
Controller
NAND Flash
Mem. Contr
Clock Sync.
2ch
16-bit PWM
1ch
8-bit ADC
4ch
NAND Flash Memory Data
Transfer Buffer
512B x 4
CGCON
WDT / Reset
16-bit
Auto-Reload Timer
3ch
GPIO
PC I/F
VBUSIN
PUCTL
D+
D
NAND Flash
Memory I/F
FD[7:0]
FRD_N
FWR_N
FCLE
FALE
FRB
User I/F
TXD1
RXD1
SIOCK1
TXD2
RXD2
SIOCK2
User I/F
SDAT
SCL
User I/F
PortA
PortB
PortC
PortD
PortE
User I/F
PWMOUT
User I/F
AIN[3:0]
MUX
1. ML67Q5200 only. The Ml675200 does not contain a built-in Flash ROM.
ZRAM 8kW
ZRAM 8kW
Dual Port
RAM
2.25kB
Dual Port
RAM
2.25kB
AHB I/F
BIU
Boot ROM
PRAM 32kW
Z-Bus
P-Bus
OCEM
CLKG
JTAG
JAM
XRAM 8kW
XRAM 8kW
X-Bus
YRAM 8kW
YRAM 8kW
Y-Bus
Teak DSP
Core
ICU
RSTGEN
CGCON
PCM Buffer
9kB
SAI trans.
Buffer
64B
SAI Recv.
SIO
DAC I/F
CKOUTD
SDD
WSD
SCLD
ADC I/F
CKOUTA
SDA
WSA
SCLA
TCKT
TMST
TDIT
TINTP
TDOT
DSPOUT0
DSPOUT1
DDSPTXD
Flash ROM
and/or RAM
SDRAM
SRAM
I/O
XD[15:0]
XA[19:1]
ROMCS_N
RAMCS_N
IOCS_N
XOE_N
XWE_N
XBS0_N
XBS1_N
External Bus I/F
EZ-Bus
DSP Module
DMA Controller
4ch
Oki Semiconductor 3
ML675200/ML67Q5200
Functional Description
High-Performance ARM-based CPU
Instructions: ARM (32-bit length) and Thumb (16-bit length) can be
mixed.
General register bank: 31 x 32 bits
Built-in barrel shifter: ALU and barrel shift operations can be executed
by one instruction.
Multiplier: 32 bits x 8 bits (Modified Booth Algorithm)
Cache: 8 Kbyte, 4-way copy back unified cache
Built-in debug function: JTAG interface
DSP Module
The Teak DSP decodes MP3/WMA digital audio data. Also decodes voice data
as Oki ADPCM.
X-RAM: 16 Kwords (32 Kbytes)
Y-RAM: 16Kwords (32 Kbytes)
Z-RAM: 16 Kwords (32 Kbytes)
P-program RAM: 32 Kwords (64 Kbytes)
Built-in debug function: JTAG interface
MP3 decoder:
- MPEG-1 layer3, MPEG-2 layer3, MPEG-2.5
WMA decoder:
- Bit rate: 64 kbps, 96 kbps, 128 kbps, 160 kbps, 192 kbps
- Sampling rate: 32 kHz, 44.1 kHz, 48 kHz
USB Control
The USB controller is compliant with the USB specification (version 1.1) and
can transfer data at 12 Mbps.
The controller has 6 types of endpoints for control/bulk/isochronous/interrupt
transfers.
NAND Flash Memory Control
The NAND Flash memory circuit automatically reads data from and writes
data to an external 528-byte NAND Flash Memory.
Also includes an ECC circuit that detects and corrects multiple-bit data errors.
DMA Control
The 4-channel DMA controller transfers data between:
Memory and memory
I/O and memory
I/O and I/O
External Memory Control
The external memory controller provides access to externally-connected
devices such as ROM (FLASH), SRAM, SDRAM and I/O.
Connect 16-bit data bus length device and byte unit access device which have
byte select function.
Power Management
The HALT, STOP, and SLEEP functions are supported as power-save functions.
Switching the CPU clock to the 1/2, 1/4, or 1/8 of the main clock enables
operation in a low power consumption mode.
HALT mode: Stops the ARM7TDMI and AHB/APB bus.
STOP mode: Stops the DSP module clock first, then the clock for the
entire device.
SLEEP mode: Stops the power supply to the DSP module first, then
stops the clock for the entire device.
Oki Semiconductor 5
ML675200/ML67Q5200
Pin Descriptions
In the Type column, an "I" indicates the signal is an input, an "O" indicates
the signal is an output, and an "I/O" indicates the signal is bi-directional.
Signals with a "_N" suffix are active low.
Pin Descriptions
Classification
Primary Function
Secondary Function
Symbol
Type
Description
Symbol
Type
Description
Port
PIOA0
I/O
16-bit I/O port A.
XD0
I/O
External access data I/O port.
PIOA1
I/O
XD1
I/O
PIOA2
I/O
XD2
I/O
PIOA3
I/O
XD3
I/O
PIOA4
I/O
XD4
I/O
PIOA5
I/O
XD5
I/O
PIOA6
I/O
XD6
I/O
PIOA7
I/O
XD7
I/O
PIOA8
I/O
XD8
I/O
PIOA9
I/O
XD9
I/O
PIOA10
I/O
XD10
I/O
PIOA11
I/O
XD11
I/O
PIOA12
I/O
XD12
I/O
PIOA13
I/O
XD13
I/O
PIOA14
I/O
XD14
I/O
PIOA15
I/O
XD15
I/O
Port
PIOB0
I/O
16-bit I/O port B.
XA1
O
External access address output port.
PIOB1
I/O
XA2
O
PIOB2
I/O
XA3
O
PIOB3
I/O
XA4
O
PIOB4
I/O
XA5
O
PIOB5
I/O
XA6
O
PIOB6
I/O
XA7
O
PIOB7
I/O
XA8
O
PIOB8
I/O
XA9
O
PIOB9
I/O
XA10
O
PIOB10
I/O
XA11
O
PIOB11
I/O
XA12
O
PIOB12
I/O
XA13
O
PIOB13
I/O
XA14
O
PIOB14
I/O
XA15
O
PIOB15
I/O
XA16
O
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