OKI Semiconductor

FEDL674001-01

Issue Date: Dec. 15, 2003

ML674001/Q4002/Q4003

32-bit ARM-Based General-Purpose Microcontroller

ARM, ARM7TDMI, Multi-ICE and AMBA are registered trademarks of ARM Ltd., UK.
µPLAT is Oki's trademark.
The contents of this data sheet are subject to change for modification without notice.

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GENERAL DESCRIPTION

The ML674001, ML67Q4002, and ML67Q4003 microcontrollers (MCUs) are the members of an extensive and
growing family of 32-bit ARM

-based standard products for general-purpose applications that require 32-bit

CPU performance and low cost afforded by MCU integrated features.
ML674001/67Q4002/67Q4003 provide built-in 32Kbyte SRAM, built-in 4Kbyte boot ROM, and a host of other
useful peripherals such as auto-reload timers, watchdog timer (WDT), pulse-width modulators (PWM), A-to-D
converter, expanded UARTs, synchronous serial port, I2C serial interface, GPIOs, DMA controller, external
memory controller, and boundary scan capability. In addition, the ML67Q4002 and ML67Q4003 offer 256
Kbytes and 512 Kbytes of built-in Flash memory respectively. The ML674001, ML67Q4002 and ML67Q4003
are pin-to-pin compatible with each other for easy performance updates.
Oki's ML674K Family MCUs are capable of executing both the 32-bit ARM instruction set for
high-performance applications as well as the 16-bit Thumb

instruction set for high code-density,

power-efficient applications. With an ARM7TDMI

core operating at 33 MHz maximum frequency, ARM

ThumbTM capabilities, and robust feature sets, the ML674001 Series MCUs are suitable for an array of
applications including high performance industrial controllers and instrumentation, telecom, PC peripherals,
security/surveillance, test equipment, and a variety of consumer electronics devices.

The ARM7TDMI

Advantage

Oki's ML674K Family of low-cost ARM-based MCUs offers system designers a bridge from 8- and 16-bit
proprietary MCU architectures to ARM's higher-performance, affordable, widely-accepted industry standard
architecture and its industry-wide support infrastructure. The ARM industry infrastructure offers the system
developers many advantages including software compatibility, many ready-to-use software applications, large
choices among hardware and software development tools. These ARM-based advantages allow Oki's
customers to better leverage engineering resources, lower development costs, minimize project risks, and reduce
their product time to market. In addition, migration of a design with an Oki standard MCU to an Oki custom
solution is easily facilitated with its award-winning uPLATTM product development architecture.

FEATURES

· CPU

32-bit RISC CPU (ARM7TDMI)

32-bit instructions (ARM Instructions) and 16-bit instructions (Thumb Instructions) mixed
General purpose registers : 31 x 32 bits
Built-in Barrel shifter and multiplier (32 bit x 8 bit, Modified Booth's Algorithm)
Little endian
Built-in debug function

· Internal memory

RAM

32KB (32-bit access)

FLASH

(16-bit

access)

ML674001 :

ROM-less

version

ML67Q4002

256Kbytes

ML67Q4003

512Kbytes

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· External memory controller

ROM (FLASH): 16 Mbytes
SRAM: 16 Mbytes
DRAM: 64 Mbytes (SDRAM and EDO-DRAM support)
External IO devices: 16 Mbytes x 2 banks, 4 Chip select pins

Wait control input signal for each bank

Independent programmable wait settings for each bank

· Interrupt controller

28 sources: 23 internals and 5 externals (IRQ: 4, FIQ: 1)

· DMA controller

2 channels: Dual address mode, cycle steal and burst tranfer mode

· Timer

1 channel: 16-bit auto reload for operating system
6 channels: 16-bit auto reload for application
1 channel: 16 bit watchdog timer

· Serial interface

1 channel: UART
1 channel: UART with 16-byte FIFO
1 channel: synchronous
1 channel: I2C (single master)

· Parallel I/O Port

4 ports x 8 bits (bitwise input/output settings)

1 port x 10 bit (bitwise input/output settings)

· PWM

2 channels x 16 bits

· Analog-to-Digital Converter

4 channels x 10 bits

· Power down mechanism

Standby (all clock stop) and Halt (clock stop by each function block)
Clock gear (selectable 1/1, 1/2, 1/4, 1/8, 1/16 input clock frequency)

· JTAG interface

Connectable to JTAG ICE

· Power supply voltage

Core section: 2.25 V to 2.75 V

IO section: 3.0 V to 3.6 V

Analog section: 3.0 V to 3.6 V

· Operating frequency

1-33

MHz

· Operating temperature (ambient temperature)

°C to +85°C

· Package

144-pin plastic LQFP (LQFP144-P-2020-0.50)
144-pin plastic LFBGA (P-LFBGA144-1111-0.80)

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BLOCK DIAGRAM

TIC

Internal &

External

Memory

controller

IRC

AHB

Bridge

ARM7TDMI

APB

Bridge

UART

System

Control

System

TMR

µPLAT-7B

CGB

AMBA

AHB bus

AMBA

APB bus

TDI

TDO

nTRST

TMS

TCK

RESET_N

OSC0
OSC1_N

VDD_CORE

VDD_IO

GND

AVDD

AGND
DRAME_N

TEST

BSEL[1:0]

FWR

JSEL

PIOE[8:5] / EXINT[3:0]

PIOE[9] / EFIQ_N

PIOB[6] / STXD

PIOB[7] / SRXD

PIOC[6:2] / XA[23:19]

XA[18:0]

XD[15:0]

PIOC[7] / XWR

XOE_N

XWE_N

XBWE_N[1:0]

XROMCS_N

XRAMCS_N

XIOCS_N[3:0]

XBS_N[1:0]

PIOD[0] / XWAIT

PIOD[1] / XCAS_N

PIOD[2] / XRAS_N

PIOD[3] / XSDCLK

PIOD[4] / XSDCS_N

PIOD[5] / XSDCKE

PIOD[6] /

XDQM[1]/XCAS_N[1]

PIOD[7] /

XDQM[0]/XCAS_N[0]

DRAMC

Internal RAM

32KB

APB

Bridge

WDT

UART

(16550)

PIOA[0] / SIN

PIOA[1] / SOUT

PIOA[2] / CTS

PIOA[3] / DSR

PIOA[4] / DCD

PIOA[5] / DTR

PIOA[6] / RTS

PIOA[7] / RI

Exp.

IRC

APB bus

TMR

16 bit x 6ch

A/D

AIN[3:0]

VREF

PWM

16 bit x 2ch

PIOC[1:0] / PWMOUT[1:0]

GPIO

DMAC

PIOA[7:0]

PIOB[7:0]

PIOC[7:0]

PIOD[7:0]

PIOE[9:0]

PIOB[0] / DREQ[0]

PIOB[2] / DREQ[1]

PIOB[1] / DREQCLR[0]

PIOB[3] / DREQCLR[1]

PIOB[4] / TCOUT[0]

PIOB[5] / TCOUT[1]

SSIO

PIOE[0] / SCLK

PIOE[1] / SDI

PIOE[2] / SDO

I2C

PIOE[3] / SDA

PIOE[4] / SCL

Internal (MCP)

FLASH ROM

ML67Q4002 : 256KB
ML67Q4003 : 512KB

Boot ROM

4KB

CKOE_N
CKO

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PIN CONFIGURATION (TOP VIEW)

144-Pin Plastic LFBGA

PIOD[6]/
XDQM[1

]

XIOCS_

N[3]

XIOCS_

N[1]

XRAMC

S_N

XBWE_

N[0]

XOE_N

PIOC[4]/

XA[21]

XA[16]

XA[14]

XA[11]

XA[9]

XA[7]

XA[6]

PIOD[7]/
XDQM[0

]

XIOCS_

N[2]

XIOCS_

N[0]

XWE_N

PIOC[7]/

XWR

PIOC[6]/

XA[23]

PIOC[2]/

XA[19]

XA[17]

XA[15]

XA[13]

XA[10]

XA[4]

XA[5]

PIOB[1]/

DREQC

LR[0]

PIOB[2]/

DREQ[1]

PIOB[0]/

DREQ[0]

XROMC

S_N

XBWE_

N[1]

PIOC[5]/

XA[22]

PIOC[3]/

XA[20]

XA[18]

XA[12] VDD_IO

XA[8]

XA[2]

GND

PIOB[3]/

DREQC

LR[1]

PIOB[5]/

TCOUT[

VDD_IO

GND

VDD_IO

VDD_C

ORE

VDD_IO

GND

XA[3]

XA[0]

XD[13]

XA[1]

PIOC[0]/

PWMOU

T[0]

GND

PIOB[4]/

TCOUT[

PIOC[1]/

PWMOU

T[1]

VDD_IO XD[15]

XD[11]

XD[14]

XBS_N[

PIOD[0]/

XWAIT

VDD_C

ORE

VDD_C

ORE

XD[10]

XD[12]

PIOD[2]/

XRAS_N

PIOD[1]/

XCAS_N

VDD_IO

GND

VDD_IO

XD[8]

XD[9]

BSEL[1]

PIOD[5]/

XSDCK

PIOD[3]/

XSDCLK

PIOD[4]/

XSDCS_

GND

XD[7]

XD[6]

XD[5]

PIOE[7]/

EXINT[2]

BSEL[0]

PIOE[8]/

EXINT[3]

PIOE[5]/

EXINT[0]

GND

XD[2]

XD[4]

PIOE[0]/

SCLK

PIOE[6]/

EXINT[1]

PIOE[9]/

EFIQ_N

PIOE[2]/

SDO

OSC1_N

PIOA[1]/

SOUT

AIN[0]

VDD_IO

GND

VDD_IO

XD[3]

XD[1]

TDI

PIOE[1]/

SDI

CKO

TMS

CKOE_

AVDD

AIN[1]

AIN[3]

VDD_C

ORE

PIOA[5]/

DTR

FWR

XD[0]

RESET_

nTRST

TDO

TCK

GND

VDD_IO

PIOA[0]/

SIN

VREF

AGND

GND

PIOA[3]/

DSR

PIOA[7]/

PIOE[4]/

SCL

PIOB[7]/

SRXD

JSEL

DRAME

OSC0

TEST

AIN[2]

PIOA[2]/

CTS

PIOA[4]/

DCD

PIOA[6]/

RTS

PIOE[3]/

SDA

PIOB[6]/

STXD

144pin LFBGA

(TOP VIEW)

Notes: NC pins are electrically unconnected in the package.

NC pins can be connected to Vdd or GND.

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144-Pin Plastic LQFP

(Secondary fun(Primary function)

(Primary functi (Secondary f

XIOCS_N[3]

XIOCS_N[2]

CKO

XIOCS_N[1]

JSEL

GND

TMS

XIOCS_N[0]

TCK

XRAMCS_N

DRAME_N

XROMCS_N

CKOE_N

XBWE_N[1]

GND

XBWE_N[0]

OSC0

XWE_N

OSC1_N

VDD_IO

XOE_N

TEST

PIOC[7]

XWR

SIN

PIOA[0]

PIOC[6]

XA[23]

SOUT

PIOA[1]

VDD_CORE

AVDD

PIOC[5]

XA[22]

VREF

PIOC[4]

XA[21]

AIN[0]

PIOC[3]

XA[20]

AIN[1]

VDD_IO

AIN[2]

PIOC[2]

XA[19]

AIN[3]

XA[18]

GND

AGND

XA[17]

GND

XA[16]

CTS

PIOA[2]

XA[15]

VDD_IO

GND

DSR

PIOA[3]

XA[14]

DCD

PIOA[4]

XA[13]

VDD_CORE

XA[12]

DTR

PIOA[5]

XA[11]

RTS

PIOA[6]

XA[10]

PIOA[7]

VDD_IO

GND

XA[9]

SDA

PIOE[3]

XA[8]

SCL

PIOE[4]

XA[7]

STXD

PIOB[6]

XA[6]

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

XDQM[0]/XCAS_N[0]

XDQM[1]/XCAS_N[1]

DREQ[0]

DREQCLR[0]

DREQCLR[1] DREQ[1]

TDO

nTRST

TCOUT[1]

PWMOUT[0]

PWMOUT[1]

XBS

N[0]

XBS

N[1]

PIOE[0]

PIOE[1]

PIOE[2]

TDI

PIOE[6]

PIOE[7]

PIOE[8]

PIOE[9]

PIOD[5]

BSEL[0]

BSEL[1]

PIOE[5]

PIOD[1]

GND

VDD

PIOD[2]

PIOB[5]

PIOC[0]

PIOD[0] VDD

CORE

(
Pri

y

f

(
Second

PIOB[0] PIOD[7]

TCOUT[0]

XWAIT

PIOC[1]

GND

PIOB[3]

PIOB[4]

PIOD[6]

PIOB[1]

VDD

PIOB[2]

XA[5]

VDD

SRXD

XCAS

XRAS

XSDCLK

XSDCS

XSDCKE

EXINT[0]

XA[2] XA[3] GND XA[4]

XD[14] XD[15] XA[0] XA[1]

XD[11] XD[12] VDD

XD[13]

XD[9] XD[10] VDD

COR

XD[7] NC

XD[8]

EXINT[1]

NC XD[5] XD[6] GND

PIOD[3]

PIOD[4]

XD[2] XD[3] XD[4] GND

VDD

XD[0] XD[1]

EXINT[2]

EXINT[3]

EFIQ

SCLK

SDI

102

101

NC PIOB[7] FWR RESET

(
Pri

y

f

(
Second

SDO

100

108

107

106

105

104

103

109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

144pin LQFP

(TOP VIEW)

Notes: NC pins are electrically unconnected in the package.

NC pins can be connected to Vdd or GND.

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LIST OF PINS

Primary Function

Secondary Function

LQFP BGA

Symbol

I/O

Description Symbol

I/O

Description

1 A1

PIOB[7]

I/O

General port (with interrupt function)

SRXD

SIO receive signal

3 C3

FWR

I Test

mode

4 C1

RESET_N

I Reset

input

VDD_IO

VDD

IO power supply

XD[0]

I/O

External data bus

XD[1]

I/O

External data bus

XD[2]

I/O

External data bus

XD[3]

I/O

External data bus

XD[4]

I/O

External data bus

11 E4

GND

12 E2

-- NC

XD[5]

I/O

External data bus

XD[6]

I/O

External data bus

15 F4

GND

XD[7]

I/O

External data bus

17 G2

-- NC

VDD_IO

VDD

I/O power supply

XD[8]

I/O

External data bus

XD[9]

I/O

External data bus

XD[10]

I/O

External data bus

VDD_CORE

VDD

CORE power supply

23 H2

-- NC

XD[11]

I/O

External data bus

XD[12]

I/O

External data bus

VDD_IO

VDD

I/O power supply

XD[13]

I/O

External data bus

XD[14]

I/O

External data bus

XD[15]

I/O

External data bus

XA[0]

External address output

XA[1]

External address output

XA[2]

External address output

XA[3]

External address output

34 L1

GND

XA[4]

External address output

XA[5]

External address output

XA[6]

External address output

XA[7]

External address output

XA[8]

External address output

XA[9]

External address output

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Primary Function

Secondary Function

LQFP BGA

Symbol

I/O

Description Symbol

I/O

Description

VDD_IO

VDD

I/O power supply

XA[10]

External address output

XA[11]

External address output

XA[12]

External address output

XA[13]

External address output

XA[14]

External address output

47 K5

GND

XA[15]

External address output

XA[16]

External address output

XA[17]

External address output

51 K6

GND

XA[18]

External address output

PIOC[2]

I/O

General port (with interrupt function)

XA[19]

External address output

VDD_IO

VDD

I/O power supply

PIOC[3]

I/O

General port (with interrupt function)

XA[20]

External address output

PIOC[4]

I/O

General port (with interrupt function)

XA[21]

External address output

PIOC[5]

I/O

General port (with interrupt function)

XA[22]

External address output

VDD_CORE

VDD

CORE power supply

PIOC[6]

I/O

General port (with interrupt function)

XA[23]

External address output

PIOC[7]

I/O

General port (with interrupt function)

XWR

Transfer direction of
external bus

XOE_N

Output enable (excluding SDRAM)

VDD_IO

VDD

I/O power supply

63 M10

XWE_N

O Write

enable

XBWE_N[0]

Byte write enable (LSB)

XBWE_N[1]

Byte write enable (MSB)

L10

XROMCS_N

External ROM chip select

N10

XRAMCS_N

External RAM chip select

M11

XIOCS_N[0]

IO chip select 0

69 K10

GND

N11

XIOCS_N[1]

IO chip select 1

M12

XIOCS_N[2]

IO chip select 2

N12

XIOCS_N[3]

IO chip select 3

N13

PIOD[6]

I/O

General port (with interrupt function)

XDQM[1]/XCAS
_N[1]

O INPUT/OUTPUT

mask/CAS (MSB)

M13

PIOD[7]

I/O

General port (with interrupt function)

XDQM[0]/XCAS
_N[0]

O INPUT/OUTPUT

mask/CAS (LSB)

L11

PIOB[0]

I/O

General port (with interrupt function)

DREQ[0]

DMA

request signal

(CH0)

L13

PIOB[1]

I/O

General port (with interrupt function)

DREQCLR[0]

DREQ Clear Signal
(CH0)

K11

VDD_IO

VDD

I/O power supply

L12

PIOB[2]

I/O

General port (with interrupt function)

DREQ[1]

DMA request signal
(CH1)

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Primary Function

Secondary Function

LQFP BGA

Symbol

I/O

Description Symbol

I/O

Description

K13

PIOB[3]

I/O

General port (with interrupt function)

DREQCLR[1]

DREQ Clear Signal
(CH1)

J11

PIOB[4]

I/O

General port (with interrupt function)

TCOUT[0]

DMAC Terminal Count
(CH0)

K12

PIOB[5]

I/O

General port (with interrupt function)

TCOUT[1]

DMAC Terminal Count
(CH1)

J13

PIOC[0]

I/O

General port (with interrupt function)

PWMOUT[0]

PWM output (CH0)

J10

PIOC[1]

I/O

General port (with interrupt function)

PWMOUT[1]

PWM output (CH1)

84 J12

GND

85 H13

XBS_N[0]

External bus byte select (LSB)

86 H12

XBS_N[1]

External bus byte select (MSB)

H10

VDD_CORE

VDD

CORE power supply

H11

PIOD[0]

I/O

General port (with interrupt function)

XWAIT

Wait input signal for I/O
Banks

G12

PIOD[1]

I/O

General port (with interrupt function)

XCAS_N

Column address strobe
(SDRAM)

90 G10

GND

91 G11 VDD_IO

VDD I/O

power

supply

G13

PIOD[2]

I/O

General port (with interrupt function)

XRAS_N

Row address strobe
(SDRAM/EDO)

F11

PIOD[3]

I/O

General port (with interrupt function)

XSDCLK

Clock for SDRAM

F10

PIOD[4]

I/O

General port (with interrupt function)

XSDCS_N

Chip select for SDRAM

F12

PIOD[5]

I/O

General port (with interrupt function)

XSDCKE

Clock enable (SDRAM)

E12

BSEL[0]

Select boot device

97 F13

BSEL[1]

Select boot device

E10

PIOE[5]

I/O

General port (with interrupt function)

EXINT[0]

Interrupt input

D12

PIOE[6]

I/O

General port (with interrupt function)

EXINT[1]

Interrupt input

100

E13

PIOE[7]

I/O

General port (with interrupt function)

EXINT[2]

Interrupt input

101

E11

PIOE[8]

I/O

General port (with interrupt function)

EXINT[3]

Interrupt input

102

D11

PIOE[9]

I/O

General port (with interrupt function)

EFIQ_N

FIQ input

103

D13

PIOE[0]

I/O

General port (with interrupt function)

SCLK

I/O

SSIO clock

104 C12 PIOE[1]

I/O

General port (with interrupt function)

SDI

SSIO Serial Data In

105 D10 PIOE[2]

I/O

General port (with interrupt function)

SDO

SSIO Serial Data Out

106

C13

TDI

JTAG data Input

107

B12

TDO

JTAG data out

108 B13 nTRST

I JTAG

reset

109 A13 NC

-- NC

110 A12 NC

-- NC

111 C11 CKO

O Clock

output

112 A11 JSEL

I JTAG

select

113

C10

TMS

JTAG mode select

114 B11 TCK

I JTAG

clock

115 A10 DRAME_N

I DRAM

enable

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Primary Function

Secondary Function

LQFP BGA

Symbol

I/O

Description Symbol

I/O

Description

116

CKOE_N

Clock out enable

117 B10 GND

GND

118

OSC0

Oscillation input pin

119

OSC1_N

Oscillation output pin

120

VDD_IO

VDD

IO power supply

121

TEST

Test mode input

122

PIOA[0]

I/O

General port (with interrupt function)

SIN

UART Serial Data In

123

PIOA[1]

I/O

General port (with interrupt function)

SOUT

UART Serial Data Out

124

AVDD

VDD

A/D CONVERTER power supply

125

VREF

A/D CONVERTER Reference
voltage

-- --

126 D7 AIN[0]

I A/D

CONVERTER

analog input port

-- --

127 C7 AIN[1]

I A/D

CONVERTER

analog input port

-- --

128 A7 AIN[2]

I A/D

CONVERTER

analog input port

-- --

129 C6 AIN[3]

I A/D

CONVERTER

analog input port

-- --

130 D6 NC

-- NC

131

AGND

GND GND for A/D CONVERTER

132 B5 GND

GND

133

PIOA[2]

I/O

General port (with interrupt function)

CTS

UART Clear To Send

134

VDD_IO

VDD

IO power supply

135

PIOA[3]

I/O

General port (with interrupt function)

DSR

UART Set Ready

136

PIOA[4]

I/O

General port (with interrupt function)

DCD

UART Carrier Detect

137

VDD_CORE

VDD

CORE power supply

138

PIOA[5]

I/O

General port (with interrupt function)

DTR

UART Data Terminal
Ready

139

PIOA[6]

I/O

General port (with interrupt function)

RTS

UART Request To Send

140

PIOA[7]

I/O

General port (with interrupt function)

UART Ring Indicator

141 D4 GND

GND

142 A3 PIOE[3]

I/O

General port (with interrupt function)

SDA

I/O

I2C Data In/Out

143 B2 PIOE[4]

I/O

General port (with interrupt function)

SCL

I2C Clock out

144

PIOB[6]

I/O

General port (with interrupt function)

STXD

SIO send data output

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PIN DESCRIPTION

Pin Name

I/O

Description

Primary/

Secondary

Logic

System

RESET_N I

Reset

input

Negative

BSEL[1:0]

Boot device select signal

BSEL[1] BSEL[0] Boot device

0 0 Internal Flash (External ROM for ML674001)

0 1 External ROM

1 * Boot mode

The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF)
after reset.

-- Positive

OSC0

Crystal connection or external clock input.

Connect a crystal (16 MHz to 33 MHz), if used, to OSC0 and OSC1_N.

It is also possible to input a direct clock.

-- --

OSC1_N O

Crystal

connection.

When not using a crystal, leave this pin unconnected.

-- --

CKO O

Clock

out

-- --

CKOE_N

Clock out enable

Negative

Debugging support.

TCK

Debugging pin. Normally connect to ground level.

TMS

Debugging pin. Normally drive at High level.

Positive

nTRST

Debugging pin. Normally connect to ground level.

Negative

TDI

Debugging pin. Normally drive at High level.

Positive

TDO

Debugging pin. Normally leave open.

Positive

General-purpose I/O ports

PIOA[7:0] I/O

General-purpose

port.

Not available for use as port pins when secondary functions are in use.

Primary Positive

PIOB[7:0] I/O

General-purpose

port.

Not available for use as port pins when secondary functions are in use.

Primary Positive

PIOC[7:0] I/O

General-purpose

port.

Not available for use as port pins when secondary functions are in use.

Primary Positive

PIOD[7:0] I/O

General-purpose

port.

Not available for use as port pins when secondary functions are in use.
Note that enabling DRAM controller with DRAME_N inputs permanently
configures PIOD[7:0] for their secondary functions, making them
unavailable for use as port pins.

Primary Positive

PIOE[9:0] I/O

General-purpose

port.

Not available for use as port pins when secondary functions are in use.

Primary Positive

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Pin Name

I/O

Description

Primary /

Secondary

Logic

External Bus

XA[23:19]

Address bus to external RAM, external ROM, external I/O banks, and
external DRAM. After a reset, these pins are configured for their primary
function (PIOC[6:2]).

Secondary Positive

XA[18:0]

Address bus to external RAM, external ROM, external I/O banks, and
external DRAM.

-- Positive

XD[15:0]

I/O

Data bus to external RAM, external ROM, external I/O banks, and external
DRAM.

-- Positive

External bus control signals (ROM/SRAM/IO)

XROMCS_N

ROM bank chip select

Negative

XRAMCS_N

SRAM bank chip select

Negative

XIOCS_N[0]

IO chip select 0

Negative

XIOCS_N[1]

IO chip select 1

Negative

XIOCS_N[2]

IO chip select 2

Negative

XIOCS_N[3]

IO chip select 3

Negative

XOE_N

Output enable/ Read enable

Negative

XWE_N O

Write

enable

Negative

XBS_N[1:0]

Byte select: XBS_N[1] is for MSB, XBS_N[0] is for LSB

Negative

XBWE_N[0]

LSB Write enable

Negative

XBWE_N[1]

MSB Write enable

Negative

XWR

Data transfer direction for external bus, used when connecting to Motorola
I/O devices. This represent the secondary function of pin PIOC[7].

L: read , H: write. Available for I/O bank 0/1.

Secondary --

XWAIT

External I/O bank 0/1, 2/3 WAIT signal.

This input permits access to devices slower than register settings.

Secondary Positive

External bus control signals (DRAM)

XRAS_N

Row address strobe. Used for both EDO DRAM and SDRAM

Secondary

Negative

XCAS_N

Column address strobe signal (SDRAM)

Secondary

Negative

XSDCLK

SDRAM clock (same frequency as internal HCLK)

Secondary

XSDCKE

Clock enable (SDRAM)

Secondary

XSDCS_N

Chip select (SDRAM)

Secondary

Negative

XDQM[1]/XCAS_N[1]

Connected to SDRAM: DQM (MSB)

Connected to EDO DRAM: column address strobe signal (MSB)

Secondary Positive/

Negative

XDQM[0]/XCAS_N[0]

Connected to SDRAM: DQM (LSB)

Connected to EDO DRAM: column address strobe signal (LSB)

Secondary Positive/

Negative

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ML674001/67Q4002/67Q4003

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Pin Name

I/O Description

Primary

Secondary

Logic

DMA control signals

DREQ[0]

Ch 0 DMA request signal, used when DMA controller configured for
DREQ type

Secondary Positive

DREQCLR[0]

Ch 0 DREQ signal clear request. The DMA device responds to this
output by negating DREQ.

Secondary Positive

TCOUT[0]

Indicates to Ch 0 DMA device that last transfer has started.

Secondary

Positive

DREQ[1]

Ch 1 DMA request signal, used when DMA controller configured for
DREQ type

Secondary Positive

DREQCLR[1]

Ch 1 DREQ signal clear request. The DMA device responds to this
output by negating DREQ.

Secondary Positive

TCOUT[1]

Indicates to Ch 1 DMA device that last transfer has started

Secondary

Positive

UART

SIN

SIO receive signal

Secondary

Positive

SOUT

SIO transmit signal

Secondary

Positive

CTS

Clear To Send.

Indicates that modem or data set is ready to transfer data. Bit 4 in
modem status register reflects this input.

Secondary Negative

DSR

Data Set Ready.

Indicates that modem or data set is ready to establish a
communications link with UART.

Bit 5 in modem status register reflects this input.

Secondary Negative

DCD

Data Carrier Detect.

Indicates that modem or data set has detected data carrier signal. Bit
7 in modem status register reflects this input.

Data Carrier Detect

Secondary Negative

DTR

Data Terminal Ready.

Indicates that UART is ready to establish a communications link with
modem or data set. Bit 0 in modem control register controls this
output.

Secondary Negative

RTS

Request To Send.

Indicates that UART is ready to transfer data to modem or data set. Bit
1 in modem control register controls this output.

Secondary Negative

Ring Indicator. Indicates that modem or data set has received
telephone ring indicator. Bit 6 in modem status register reflects this
input.

Secondary Negative

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Pin Name

I/O

Description

Primary

Secondary

Logic

SIO

STXD

SIO transmit signal

Secondary

Positive

SRXD

SIO receive signal

Secondary

Positive

I2C

SDA

I/O

I2C Data. This pin operates as NMOS Open drain. Connect pull-up
resistor.

Secondary Positive

SCL

I2C Clock. This pin operates as NMOS Open drain. Connect pull-up
resistor.

Secondary

Synchronous SIO

SCLK I/O

Serial

clock

Secondary

SDI

Serial receive data

Secondary

Positive

SDO

Serial transmit data

Secondary

Positive

PWM signals

PWMOUT[0]

PWM output of CH0

Secondary

Positive

PWMOUT[1]

PWM output of CH1

Secondary

Positive

Analog-to-digital converter

AIN[0]

Ch0 analog input

AIN[1]

Ch1 analog input

AIN[2]

Ch2 analog input

AIN[3]

Ch3 analog input

VREF I

Analog-to-digital

converter convert reference voltage

AVDD

Analog-to-digital

converter power supply

AGND

Analog-to-digital converter ground

Interrupt signals

EXINT[3:0]

External interrupt input signals.

Secondary

Positive

Negative

EFIQ_N

External fast interrupt input signal.

Interrupt controller connects this to CPU FIQ input.

Secondary

Negative

MODE configuration

DRAME_N

DRAM enable mode

Negative

TEST I

Test

mode

Positive

FWR I

Test

mode

Positive

JSEL

JTAG select signal. L: On-board debug, H: Boundary scan.

Power supplies

VDD_CORE

Core power supply

VDD_IO

I/O power supply

GND

GND for core and I/O

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DESCRIPTION OF FUNCTIONS

CPU
CPU core:

ARM7TDMI

Operating frequency:

1 MHz to 33 MHz

Byte ordering:

Little endian

Instructions:

ARM instruction (32-bit length) and Thumb instruction (16-bit length) can be mixed.

General register bank:

× 32 bits

Built-in barrel shifter:

ALU and barrel shift operations can be executed by one instruction.

Multiplier: 32

bits

× 8 bits (Modified Booth's Algorithm)

Built-in debug function: JTAG interface, break point register

Built-in Memory
FLASH ROM:

ML674001 : ROM-less version

ML67Q4002 : 256Kbytes (128K x 16 bits)

ML67Q4003 : 512Kbytes (256K x 16 bits)

Access timing of this FLASH memory is configured by the ROM bank control register
of the external memory controller.

RAM:

32KB (8K x 32bits)

Read access(8/16/32bit): 1 cycle,

Write access(32bit): 1 cycle,

Write aceess(8/16bit): 2 cycle,

Interrupt Controller
Fast interrupt request (FIQ) and interrupt request (IRQ) are employed as interrupt input signals. The interrupt
controller controls these interrupt signals going to ARM core.

(1) Interrupt

sources

FIQ: 1 external source (external pin: EFIQ_N)

IRQ: total of 27 sources. 23 internal sources, and 4 external sources (external pins: EXINT[3:0])

(2) Interrupt priority level

Configurable, 8-level priority for each source

(3) External interrupt pin input

EXINT[3:0] can be set as Level or Edge sensing.
Configurable High or Low when Level sensing. Configurable Rise or Falling edge triggering when Edge
sensing.
EFIQ_N is set as Falling edge triggering.

Timers
7 channels of 16-bit reload timers are employed. Of these, 1 channel is used as system timer for OS.
The timers of other 6 channels are used in application software.

(1) System timer: 1 channel

16-bit auto reload timer: Used as system timer for OS. Interrupt request by timer overflow.

(2) Application timer: 6 channels

16-bit auto reload timer. Interrupt request by compare match.

One shot, interval

Clock can be independently set for each channel

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ML674001/67Q4002/67Q4003

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WDT
Functions as an interval timer or a watch dog timer.

(1) 16-bit

timer

(2) Watch dog timer or interval timer mode can be selected
(3) Interrupt or reset generation.
(4) Maximum period: longer than 200 msec

PWM
This LSI contains two channels of PWM (Pulse Width Modulation) function which can change the duty cycle of
a waveform with a constant period. The PWM output resolution is 16 bits for each channel.

Serial Interface

This LSI contains four serial interface.

(1) UART without FIFO

: 1 channel

This is the serial port which performs data transmission, taking a synchronization per character.
Selection of various parameters, such as addition of data length, a stop bit, and a parity bit, is possible.

Asynchronous full duplex operation

Sampling Rate = Baud rate x 16sample

Character Length

: 7, 8 bit

Stop Bit Length

: 1, 2 bit

Parity

: Even, Odd, none

Error Detection

: Parity, Framing, Over run

Loop Back Function

: ON/OFF, Parity, framing, Over run Compulsive addition

Baud Rate Generation

: Exclusive baud rate generator built-in (8bit counter)

Independent from a bus clock

Internal-Baud-Rate-Clock-Stop at the time of HALT Mode.

(2) UART with 16bytes FIFO

: 1channel

Features 16bytes FIFO in both send and receive. Uses the industry standard 16550A ACE
(Asynchronous Communication Element).
-

Asynchronous full duplex operation

Reporting function for all status

16 Byte Transmission and reception FIFO

Transmission, reception, interrupt of line status Data set and Independent FIFO control.

Modem control signals

: CTS, DCD, DSR, DTR, RI and RTS

Data length

: 5, 6, 7, 8 bit

Stop bit length

: 1, 1.5, 2 bit

parity

: Even, Odd, none

Error Detection

: Parity, Framing, Overrun

Baud Rate Generation

: Exclusive baud rate generator built-in

(3) Synchronous serial interface

: 1channel

It is a clock synchronous 8bit serial port

selectable 1/8, 1/16 or 1/32 of HCLK frequency.

Choose LSB First or MSB First.

Choose Master / Slave Mode

Transceiver Interruption, Transceiver buffer empty interrupt

Loopback Test Function

(4)

I2C

1channel

Based on the I2C BUS specifications. Operates as a single master device.

Communication mode

: Master transmitter /master receiver

Transmission Speed

: 100kbps (Standard mode) / 400kbps (Fast mode)

Addressing format

: 7 bit / 10 bit

Data buffer

: 1 Byte(1step)

Communication Voltage : 2.7V to 3.3V

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ML674001/67Q4002/67Q4003

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GPIO

42-bits parallel port (four 8-bit ports and one 10-bit port)

PIOA[7:0]

Combination

port UART

PIOB[7:0]

Combination port

DMAC, UART(uPLAT-7B),

PIOC[7:0]

Combination port

PWM, XA[23:19], XWR

PIOD[7:0]

Combination port

DRAM contorol signal etc.

PIOE[9:0]

Combination port

SSIO, I2C, External interrupt signal

(1) Input/output selectable at bit level.
(2) Each bit can be used as an interrupt source.
(3) Interrupt mask and interrupt polarity can be set for all bits.
(4) The ports are configured as input, immediately after reset.
(5) Primary/secondary function of each port can be set independently.

AD Converter
Successive approximation type AD converter.

(1) 10

bits

× 4 channels

(2) Sample hold function
(3) Scan mode and select mode are supported
(4) Interrupt is generated after completion of conversion.
(5) Conversion time: 5 µs minimum.

DMAC
Two channels of direct memory access controller which transfers data between memory and memory, between
I/O and memory and between I/O and I/O.

(1) Number of channels: 2 channels
(2) Channel priority level: Fixed mode

Channel priority level is always fixed (channel 0 > 1).

Roundrobin

Priority level of the channel requested for transfer is kept lowest.

(3) Maximum number of transfers: 65,536 times (64K times)
(4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
(5) Bus request system:

Cycle steal mode

Bus request signal is asserted for each DMA transfer cycle.

Burst

mode

Bus request signal is asserted until all transfers of transfer cycles are complete.

(6) DMA transfer request: Software request

By setting the software transfer request bit inside DMAC, the CPU starts DMA
transfer.

External

request

DMA transfer is started by external request allocated to each channel.

(7) Interrupt request: Interrupt request is generated to CPU after the end of DMA transfers for the set

number of transfer cycles or after occurrence of error.

Interrupt request signal is output separately for each channel.

Interrupt request signal output can be masked for each channel.

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External memory controller
Controls access of externally connected devices such as ROM (FLASH), SRAM, SDRAM (EDO DRAM), IO
devices, and internal FLASH memory.

(1) ROM (FLASH) access function

: 1 bank

Supports 16-bit devices.

Supports FLASH memory: Byte write (can be written only by IF equivalent to SRAM).

In ML67Q4002/ML67Q4003, control internal FLASH access.

Configurable access timing.

(2) SRAM access function

: 1 bank

Supports 16-bit devices.

Supports asynchronous SRAM

Configurable access timing.

(3) DRAM access function

: 1 bank

Supports 16-bit device

Supports EDO/SDRAM

: Simultaneous connections to EDO-DRAM and SDRAM cannot be

made.

Configurable access timing.

(4) External IO access function

: 2 banks

Supports 8-bit/16-bit access

: Independent configuration for each bank

Each bank has two chip selects

: XIOCS_N[3:0]

Supports external wait input

: XWAIT

Access Timing configurable for each bank independently

Power Management
HALT, STANDBY, clock gear, clock control functions are supported as power save functions.

(1) HALT

mode

HALT

object

CPU, internal RAM, AHB bus control

HALT mode setting: Set by the system control register.

Exit HALT mode due to: Reset, interrupt

(2) STANDBY

mode

Stops the clock of entire LSI.

STANDBY mode setting: Specified by the system control register.

Exit

STANDBY mode due to: Reset, external interrupt (other than EFIQ_N)

(3) Clock

gear

This LSI has two clock systems, HCLK and CCLK. Configure HCLK and CCLK frequency.

HCLK: CPU, bus control, synchronous serial interface, I2C.

CCLK: Timers, PWM, UART, AD converter, etc.

(4) Clock control by each function unit

AD converter, PWM, Timers, DRAMC, DMAC, UART(FIFO), UART, Synchronous SIO, I2C.

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ML674001/67Q4002/67Q4003

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BUILT-IN FLASH ROM PROGRAMMING

The robust features of the flash permit simple and optimized programming as well as maintaining the flash-ROM.

(1) Programming Method

· Programming via JTAG interface

· Programming using boot mode

Boot mode of this LSI is used for downloading data to be written to the FLASH through the UART

interface of the MCU from a host system. In boot mode, the program on the on-chip boot ROM
downloads a flash writing application, that will handle the serial transfer and writing of internal flash, to
internal RAM area of the MCU through the UART interface of the MCU.

· Programming via user application running from external memory

Internal flash can be programmed by executing a user flash programming application from external
memory.

(2) Single power source for Read/Program of FLASH: 3.0V to 3.6V
(3) Programming units : 2 bytes
(4) Selectable erasing size

· Sector erase: 2Kbytes/sector

· Block erase: 64Kbytes/block

· Chip erase: All memory cell

(5) Word program time: 30usec
(6) Sector/block erase time: 25msec
(7) Chip erase time: 100msec
(8) Write protection

· Block protect: top address 8Kwords can be protected

· Chip protect: all words can be protected

(9) Number of commands: 9
(10) Highly reliable read/program

· Sector programming: 1000 times

· Data hold period: 10 years

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OKI Semiconductor

ML674001/67Q4002/67Q4003

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ABSOLUTE MAXIMUM RATINGS

Item

Symbol

Conditions

Rating

Unit

Digital power supply
voltage (core)

DD_CORE

0.3 to +3.6

Digital power supply
voltage (I/O)

DD_IO

0.3 to +4.6

Input voltage

0.3 to V

DD_IO

+0.3

Output voltage

0.3 to V

DD_IO

+0.3

Analog power supply
voltage

0.3 to V

DD_IO

+0.3

Analog reference voltage

REF

0.3 to V

DD_IO

+0.3 and

0.3 to AV

+0.3

Analog input voltage

0.3 to V

REF

Input current

10 to +10

Output current *

20 to +20

Output current *

GND = AGND = 0 V
Ta = 25

°C

30 to +30

Power losses (LFBGA)

680

Power losses (LQFP)

Ta = 85

°C

per package

1000

Storage temperature

STG

50 to +150

°C

Note

1. These are maximum ratings not for general operation. Exceeding these maximum ratings could

cause damage or lead to permanent deterioration of the device.

2. All output pins except XA[15:0]
3. XA[15:0]

OPERATING CONDITIONS

(GND = 0 V)

Item

Symbol

Conditions

Minimum Typical Maximum Unit

Digital power supply voltage
(core)

DD_CORE

2.25

2.5

2.75

Digital power supply voltage
(I/O)

DD_IO

DD_CORE

3.0 3.3 3.6

Analog power supply
voltage

VDD

= V

DD_IO

3.0

3.3

3.6

Analog reference voltage

REF

= A

VDD

= V

DD_IO

3.0 3.3 3.6

Operating frequency *

DD_CORE

= 2.25 to 2.75

DD_IO

= 3.0 to 3.6

1 --

33.333

MHz

Ambient temperature

+85

°C

Note

Operating frequencies between 16 MHz and 33 MHz. Minimum of 2.56 MHz for external SDRAM.
Minimum of 6.4 MHz for external EDO DRAM. Minimum of 2 MHz for analog-to-digital converter.

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ML674001/67Q4002/67Q4003

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ELECTRICAL CHARACTERISTICS

DC Characteristics

DD_CORE

= 2.25 to 2.75V, V

DD_IO

= 3.0 to 3.6V, Ta = 40 to +85

°C)

Item

Symbol

Conditions

Minimum

Typical Maximum

Unit

High level input voltage

DD_IO

x0.8

-- V

DD_IO

+0.3

Low level input voltage

0.3

DD_IO

x0.2

T+

1.6

2.1

T-

0.7

1.1

Schmitt input buffer
threshold voltage

HYS

0.4 0.5 --

= 100 µA

0.2 --

High level output voltage

= 4 mA

2.35

Low level output voltage

= 100 µA

0.2

Low level output voltage *

= 4 mA

0.45

Low level output voltage *

= 6 mA

0.45

Input leak current *

= 0 V/V

DD_IO

50 -- 50

Input leak current *

= 0 V

Pull-up resistance of

50 k

200 66 10

Input leak current *

= AV

/ 0 V

5 -- 5

Output leak current

= 0 V/V

DD_IO

50 -- 50

µA

Input pin capacitance

-- 6 --

Output pin capacitance

-- 9 --

I/O pin capacitance

-- --

Analog-to-digital

converter operative *

-- 320 650

Analog reference power
supply current

REF

Analog-to-digital

converter stopped

-- 1 2

DDS_CORE

100

Current consumption
(STANDBY)

DDS_IO

Ta = 25

°C *

-- 5 20

µA

DDH_CORE

Current consumption
(HALT) *

DDH_IO

DD_CORE

Current consumption (RUN)
*

DD_IO

= 33 MHz

= 30 pF

-- 18 30

Notes

1. All output pins except XA[15:0]
2. XA[15:0]
3. All input pins except RESET_N
4. RESET_N pin, with 50 k

pull-up resistance

5. Analog input pins (AIN0 to AIN3)
6. Analog-Digital Converter operation ratio is 20%
7. V

DD_IO

or 0 V for input ports; no load for other pins

8. DRAM controller blocks stopped by DRAME_N pin setting
9. External ROM used

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Analog-to-Digital Converter Characteristics

DD_CORE

= 2.50 V, V

DD_IO

= 3.3 V, Ta = 25

°C)

Item

Symbol

Conditions

Minimum Typical Maximum

Unit

Resolution n

bit

Linearity error

±3 --

Differential linearity error

±3 --

Zero scale error

±3 --

Full scale error

Analog input

source impedance

Ri 1k

±3 --

LSB

Conversion time

CONV

-- 5

µs

Throughput

200

kHz

Notes: VDD_IO and AVDD should be supplied separately

· Definition of Terms

(1) Resolution: Minimum input analog value recognized. For 10-bit resolution, this is (V

REF

Aground)

÷ 1024.

(2) Linearity error: Difference between the theoretical and actual conversion characteristics.

(Note that it does not include quantization error.) The theoretical conversion characteristic
divides the voltage range between V

REF

and AGND into 1024 equal steps.

(3) Differential linearity error: Difference between the theoretical and actual input voltage

change producing a 1-bit change in the digital output anywhere within the conversion range.
This is an indicator of conversion characteristic smoothness. The theoretical value is (V

REF

Aground)

÷ 1024.

(4) Zero scale error: Difference between the theoretical and actual conversion characteristics at

the point where the digital output switches from "0x000" to "0x001."

(5) Full scale error: Difference between the theoretical and actual conversion characteristics at

the point where the digital output switches from "0x3FE" to "0x3FF."

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NOTICE
1. The information contained herein can change without notice owing to product and/or technical

improvements. Before using the product, please make sure that the information being referred to is
up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an

explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is

granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party's right which may result
from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML67Q4003

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML67Q4003