1/20

¡ Semiconductor

ML7000-01
ML7001-01

Single Rail CODEC

GENERAL DESCRIPTION

The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging
from 300 to 3400 Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the devices are
optimized for ISDN terminals, digital wireless systems, and digital PBXs.
The devices use the same transmission clocks as those used in the MSM7507.
With the differential analog signal outputs which can drive 600 W load, the devices can directly
drive a handset receiver.

FEATURES

· Single power supply: +5 V (ML7000-01)

+3 V (ML7001-01)

· Low power consumption

Operating mode:

25 mW Typ.

= 5.0 V (ML7000-01)

20 mW Typ.

= 3.0 V (ML7001-01)

Power-down mode:

0.05 mW Typ.

= 5.0 V (ML7000-01)

0.03 mW Typ.

= 3.0 V (ML7001-01)

· Conforms to ITU-T Companding law

m/A-law pin selectable

· Transmission characteristics conform to ITU-T G.714
· Short frame sync timing operation
· Built-in PLL eliminates a master clock
· Serial data rate: 64/96/128/192/200/256/384/512/

768/1024/1536/1544/2048 kHz

· Adjustable transmit gain
· Adjustable receive gain
· Built-in reference voltage supply
· Package options:

24-pin plastic SOP (SOP24-P-430-1.27-K)

(Product name: ML7000-01MA/ML7001-01MA)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: ML7000-01MB/ML7001-01MB)

FEDL7000-03

This version: Dec. 2000

Previous version: Feb. 2000

¡ Semiconductor

ML7000-01/ML7001-01

3/20

FEDL7000-03

PIN CONFIGURATION (TOP VIEW)

AOUT+

AOUT

PWI

VFRO

PDN

SGC

AIN+

AIN

GSX

BCLK

20-Pin Plastic SSOP

RSYNC

PCMIN

XSYNC

PCMOUT

AOUT+

AOUT

PWI

VFRO

PDN

SGC

AIN+

AIN

GSX

24-Pin Plastic SOP

RSYNC

PCMIN

XSYNC

PCMOUT

BCLK

ALAW

NC : No connect pin

¡ Semiconductor

ML7000-01/ML7001-01

4/20

FEDL7000-03

PIN FUNCTIONAL DESCRIPTION

AIN+, AIN, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed using any of the methods shown below. During
power-saving and power-down modes, the GSX output is at AG voltage.

Analog ground.

VFRO

Receive filter output.
The output signal has an amplitude of 2.4 V

for ML7000-01 and 2.0 V

for ML7001-01 above

and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN
and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving or power-down mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.

AIN
AIN+

Analog input

R1 : variable
R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

GSX

AIN+
AIN

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

GSX

Analog input

¡ Semiconductor

ML7000-01/ML7001-01

5/20

FEDL7000-03

PWI, AOUT+, AOUT

PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT. During power-saving or power down-mode,
the outputs of AOUT+ and AOUT are in a high impedance state. The output of AOUT+ is
inverted with respect to the output of AOUT. Since these outputs provide differential drive of
an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric
earphone or a line transformer. Refer to the application example.

Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)

PCMIN

PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.

R6 > 20 kW
ZL > 1.2 kW

Gain = VO/VI = 2 5 R7/R6 £ 2

VFRO

PWI

AOUT

AOUT+

Receive filter

20 kW

¡ Semiconductor

ML7000-01/ML7001-01

6/20

FEDL7000-03

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be
synchronized in phase with the BCLK. The frequency should be 8 kHz

50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not
guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.
The frequency should be 8 kHz

50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section. However, if the frequency characteristic of
an applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but the
electrical characteristics in this specification are not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

¡ Semiconductor

ML7000-01/ML7001-01

7/20

FEDL7000-03

Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to the
AG pin on the printed circuit board to make a common analog ground AG.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from
MSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
When A-law is selected, the ML7000-01 and ML7001-01 output the character signal, inverting the
even bits.

Input/Output Level

+Full scale

Full scale

PCMIN/PCMOUT

m-law

MSD

A-law

MSD

LSD

¡ Semiconductor

ML7000-01/ML7001-01

8/20

FEDL7000-03

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.
The output drive current capability is

300 mA for ML7000-01 and

200 mA for ML7001-01.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
The CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will
operate in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the
pin is left open, since the pin is internally pulled down.

¡ Semiconductor

ML7000-01/ML7001-01

9/20

FEDL7000-03

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Unit

Max.

Typ.

Min.

Condition

Symbol

Parameter

5.25

5.00

4.75

Power Supply Voltage

°C

+85

+25

Operating Temperature

2.4

Connect AIN and GSX

AIN

Analog Input Voltage

2.2

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

High Level Input Voltage

0.8

Low Level Input Voltage

64, 96, 128, 192, 200, 256,

384, 512, 768, 1024, 1536,

1544, 2048

BCLK

Clock Frequency

kHz

9.0

8.0

6.0

XSYNC, RSYNC (40 to +75 °C)

Sync Pulse Frequency

BCLK

Clock Duty Ratio

XSYNC, RSYNC, BCLK,

PCMIN, PDN

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

BCLKÆXSYNC, See Fig. 1

XSYNCÆBCLK, See Fig. 1

Receive Sync Pulse Setting Time

BCLKÆRSYNC, See Fig. 1

RSYNCÆBCLK, See Fig. 1

RSYNC Setup Time

RSYNC Hold Time

PCMIN Setup Time

PCMIN Hold Time

0.5

Pull-up resistor

100

Digital Output Load

+10

Transmit gain stage, Gain = 0 dB

off

+100

100

Transmit gain stage, Gain = +20 dB

Analog Input Allowable DC Offset

1000

XSYNC, RSYNC, BCLK

Allowable Jitter Width

3.30

3.00

2.70

1.2

0.45¥V

0.16¥V

XSYNC Setup Time

XSYNC Hold Time

10.0

8.0

6.0

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Symbol

AIN

DIN

Condition

Rating

0.3 to +7

0.3 to V

+ 0.3

0.3 to V

+ 0.3

Unit

Values above the dotted line are for ML7000-01; those below, for ML7001-01.

¡ Semiconductor

ML7000-01/ML7001-01

10/20

FEDL7000-03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

Parameter

Power Supply Current

High Level Input Voltage

Low Level Input Voltage

High Level Input Leakage Current

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Symbol

DD1

DD3

DD2

Condition

Operating mode

Power-saving mode, PDN = 1,

XSYNC Æ OFF

Power-down mode, PDN = 0,

BCLK OFF

Pull-up resistor = 500 W

Min.

2.2

0.0

Typ.

5.0

1.5

0.01

0.2

Max.

12.0

4.0

0.05

0.8

2.0

0.5

0.4

Unit

(ML7001-01: V

= 2.7 V to 3.3 V, Ta = 30 to +85

(ML7000-01: V

= +5.0 V

5%, Ta = 30 to +85

No signal

6.5

10.0

= 5.0 V

= 3.0 V

2.0

8.0

0.45¥V

0.0

0.16¥V

High Level Input Leakage Current

IH2

30.0

ALAW

Values above the dotted line are for ML7000-01; those below, for ML7001-01.

¡ Semiconductor

ML7000-01/ML7001-01

11/20

FEDL7000-03

Transmit Analog Interface Characteristics

Receive Analog Interface Characteristics

Input Resistance

Output Load Resistance

Output Load Capacitance

INPW

LVF

LAO

LVF

LAO

PWI

0.6

VFRO with respect to SG

Output Amplitude

Offset Voltage

OVF

OAO

OSVF

OSAO

1.2

1.3

100

+1.2

+1.3

+100

V0p

VFRO, R

= 20 kW with

respect to SG

AOUT+, AOUT (each) with

respect to SG

VFRO

AOUT+, AOUT

AOUT+, AOUT, R

= 0.6 kW

with respect to SG

VFRO with respect to SG

AOUT+, AOUT, Gain = 1 with

respect to SG

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

(ML7001-01: V

= 2.7 V to 3.3 V, Ta = 30 to +85

(ML7000-01: V

= +5.0 V

5%, Ta = 30 to +85

1.0

+1.0

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

INX

LGX

OGX

OSGX

AIN+, AIN

Gain = 1

1.2

+1.2

+20

V0p

GSX with respect to SG

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

(ML7001-01: V

= 2.7 V to 3.3 V, Ta = 30 to +85

(ML7000-01: V

= +5.0 V

5%, Ta = 30 to +85

0.7

+0.7

Values above the dotted line are for ML7000-01; those below, for ML7001-01.

¡ Semiconductor

ML7000-01/ML7001-01

12/20

FEDL7000-03

AC Characteristics

Condition

(ML7001-01: F

= 8 kHz, V

= 2.7 V to 3.3 V, Ta = 30 to +85

(ML7000-01: F

= 8 kHz, V

= +5.0 V

5%, Ta = 30 to +85

Parameter

Symbol

Min.

Typ.

Max.

Unit

Transmit Frequency Response

Loss T1

Level

(dBm0)

Freq.

(Hz)

Loss T2

300

0.15

+0.07

+0.2

Loss T3

1020

Reference

Loss T4

2020

0.15

0.04

+0.2

Loss T5

3000

0.15

+0.07

+0.2

Loss T6

3400

0.4

0.8

Receive Frequency Response

Loss R1

300

0.15

0.03

+0.2

Loss R2

1020

Reference

Loss R3

2020

0.15

0.00

+0.2

Loss R4

3000

0.15

+0.05

+0.2

Loss R5

3400

0.54

0.8

SD T1

SD T2

SD T3

35.0

38.0

Transmit Signal to Distortion Ratio

1020

SD T4

26.0

31.0

SD T5

24.0

25.0

SD R1

SD R2

SD R3

36.0

40.0

Receive Signal to Distortion Ratio

1020

SD R4

32.0

SD R5

27.0

Transmit Gain Tracking

GT T1

0.3

+0.01

+0.3

GT T2

Reference

GT T3

1020

0.3

0.05

+0.3

GT T4

0.6

0.05

+0.6

GT T5

1.2

0.08

+1.2

Receive Gain Tracking

GT R1

0.3

0.06

+0.3

GT R2

Reference

GT R3

1020

0.3

+0.08

+0.3

GT R4

0.6

+0.12

+0.6

GT R5

1.2

+0.15

+1.2

32.0

27.0

25.0

26.0

30.0

25.0

34.0

38.0

40.0

35.0

*1 Psophometric filter is used.

Values above the dotted line are for ML7000-01; those below, for ML7001-01.

¡ Semiconductor

ML7000-01/ML7001-01

13/20

FEDL7000-03

AC Characteristics (Continued)

Absolute Level (Initial Difference)

Nidle T

73.0

66.0

dBm0p

Nidle R

78.0

AV T

0.58

0.6007

0.622

AV R

0.338

0.35

0.362

Vrms

1020

Absolute Delay

AV Tt

0.2

AV Rt

0.2

1020

0.6

A to A

BCLK

= 64 kHz

Transmit Group Delay

0.19

0.75

0.11

0.35

0.02

0.125

0.05

0.125

0.07

0.75

Receive Group Delay

0.00

0.75

0.00

0.125

0.09

0.125

0.12

0.75

71.0

Idle Channel Noise

AIN = SG

*1 *2

= 5 V

5%, Ta = 30 to 85

= 2.7 to 3.3 V, Ta = 30 to 85

Absolute Level

(Deviation of Temperature and Power)

500

600

1000

2600

2800

Crosstalk Attenuation

CR T

CR R

1020

TRANS Æ RECV

RECV Æ TRANS

500

600

1000

2600

2800

0.35

Condition

(ML7001-01: F

= 8 kHz, V

= 2.7 V to 3.3 V, Ta = 30 to +85

(ML7000-01: F

= 8 kHz, V

= +5.0 V

5%, Ta = 30 to +85

Parameter

Symbol

Min.

Typ.

Max.

Unit

Level

(dBm0)

Freq.

(Hz)

65.0

69.5

65.0

75.0

= 5.0 V,

= 25

= 3.0 V,

Ta = 25

0.6007

0.58

0.622

0.483

0.518

0.5

*1 Psophometric filter is used.
*2 Input "0" code to PCMIN.
*3 AVR is defined at VFRO output.
*4 With respect to minimum value of the group delay distortion.

Values above the dotted line are for ML7000-01; those below, for ML7001-01.

¡ Semiconductor

ML7000-01/ML7001-01

14/20

FEDL7000-03

AC Characteristics (Continued)

*5 Measured under idle channel noise.

DIS

4.6 kHz to

Digital Output Delay Time

XD1

200

XD2

200

Discrimination

0 to

4000 Hz

= 100 pF + 1 LSTTL

Pull-up resistor = 500 W

300 to

37.5

dBm0

Out-of-band Spurious

4.6 kHz to

IMD

fa = 470

dBm0

Intermodulation Distortion

2fa fb

PSR T

0 to

Power Supply Noise Rejection Ratio

50 mV

Measured

inband *5

PSR R

72 kHz

3400

fd = 320

50 kHz

100 kHz

Condition

(ML7001-01: F

= 8 kHz, V

= 2.7 V to 3.3 V, Ta = 30 to +85

(ML7000-01: F

= 8 kHz, V

= +5.0 V

5%, Ta = 30 to +85

Parameter

Symbol

Min.

Typ.

Max.

Unit

Level

(dBm0)

Freq.

(Hz)

¡ Semiconductor

ML7000-01/ML7001-01

16/20

FEDL7000-03

APPLICATION CIRCUIT

PCMOUT

XSYNC

AIN

GSX

AIN+

1 mF

PCM signal output

8 kHz SYNC signal input

PCM shift clock input

PCM signal input

Control of companding law
1: A-law
0: m-law

0.1 mF 51 kW

AOUT+

RSYNC

BCLK

PCMIN

ALAW

AOUT

PWI

VFRO

SGC

0 V

+5 V

51 kW

10 mF

ML7000-01

PDN

0 to 20 W

+ 5V

Power down control input
1: Normal operation
0: Power down

600 W

600:600

600:600 300 W

300 W

1 kW

0.1 mF

PCMOUT

XSYNC

AIN

GSX

AIN+

1 mF

PCM signal output

8 kHz SYNC signal input

PCM shift clock input

PCM signal input

Control of companding law
1: A-law
0: m-law

0.1 mF 51 kW

AOUT+

RSYNC

BCLK

PCMIN

ALAW

AOUT

PWI

VFRO

SGC

0 V

+3 V

51 kW

10 mF

ML7001-01

PDN

0 to 20 W

+3 V

Power down control input
1: Normal operation
0: Power down

600 W

600:600

600:600 300 W

300 W

1 kW

0.1 mF

¡ Semiconductor

ML7000-01/ML7001-01

17/20

FEDL7000-03

NOTES ON USE

· To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

· Connect the AG pin and the DG pin as closely as possible. Connect to the system ground with

low impedance.

· Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the

use of IC socket is unavoidable, use the short lead type socket.

· When mounted on a frame, use electromagnetic shielding if any electromagnetic wave

sources such as power supply transformers surrounds the device.

· Keep the voltage on the V

pin not lower than 0.3 V even instantaneously to avoid latch-

up that may otherwise occur when power is turned on.

· Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

¡ Semiconductor

ML7000-01/ML7001-01

18/20

FEDL7000-03

(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SOP24-P-430-1.27-K

Mirrur finish

Package material
Lead frame material
Pin treatment
Package weight (g)

Oki Electric Industry Co., Ltd.

Rev. No./Last Revised

Epoxy resin
42 alloy
Solder plating (5 mm)
0.58 TYP.
5/Oct. 13, 1998

¡ Semiconductor

ML7000-01/ML7001-01

19/20

FEDL7000-03

(Unit : mm)

Notes for Mounting the Surface Mount Type Package

SSOP20-P-250-0.95-K

Mirror finish

Package material
Lead frame material
Pin treatment
Package weight (g)

Oki Electric Industry Co., Ltd.

Rev. No./Last Revised

Epoxy resin
42 alloy
Solder plating (5 mm)
0.18 TYP.
5/Oct. 13, 1998

20/20

FEDL7000-03

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML7000-01MA

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML7000-01MA