¡ Semiconductor

ML7005

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¡ Semiconductor

ML7005

DTMF Transceiver

GENERAL DESCRIPTION

The ML7005 is a multi-functional DTMF transceiver LSI with built-in a DTMF signal generator,
a DTMF signal receiver, a call progress tone generator, a call progress tone detector, and a FAX
(FX) signal detector.
Each functional block can be controlled by an external MCU via a 4-bit processor interface.
The ML7005 does not contains a modem. However, the DTMF system data transmission is
possible at less than 66 bps by setting the DTMF receiver to the high-speed detection mode.
The ML7005 operates with low-power consumption and is suitable for remote control systems,
especially for ACR (Automatic Cost Routing) controllers.

FEATURES

· Wide range of power supply voltage : +2.7 V to +5.5 V
· Low power consumption
Operating mode

: 4.0 mA (V

= 3 V) Typ.

Operating mode

: 5.0 mA (V

= 5 V) Typ.

Power down mode : 1 mA Typ.
· The 4-bit processor interface supports both the Intel processor mode in which a read signal and

a write signal are used independently of each other, and the Motorola processor mode in which
a read signal and a write signal are used in common.

· The DTMF receiver can select either the high-speed detection mode (signal repeat time: more

than 60 ms) or the normal detection mode (signal repeat time: more than 90 ms).

· Built-in call progress tone generator
· Built-in FAX signal (FX: 1300 Hz) detector
· The DTMF signal generator, DTMF signal detector, call progress tone generator, and call

progress tone detector can operate concurrently.

· Built-in 3.579545 MHz crystal oscillator circuit
· Package :
32-pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name: ML7005MB)

E2A0050-29-81

This version: Aug. 1999

Previous version: May 1999

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PIN DESCRIPTION

Pin

Symbol

Type

Description

DTRIO

Output pin for DTMF signal receiver input amplifier.
See the figure 8 for adjusting the receive signal level. See the figure 10 when the
DTMF signal receiver is not used.

DTRIM

Inverting input pin for DTMF signal receiver input amplifier.

DTRIP

Non-inverting input pin for DTMF signal receiver input amplifier.

Output pin for signal ground.
The output voltage is half of V

Connect SG and GND by a 1 µF capacitor.
This pin goes to a high impedance state when in power down mode.

CPAO

Output pin for amplifier used for adjusting the transmit output level of CPT
(Call Progress Tone) signal generator. The non-inverting input of this amplifier is
internally connected to SG. See the figure 11 for adjusting the transmit signal level.
When this amplifier is not used, the CPAO pin should be shorted to the CPAI pin.

CPAI

Inverting input pin for amplifier used to adjust the transmit level of the CPT signal
generator.

CPTGO

Analog output pin for CPT signal generator.
The tone amplitude is approximately - 3 dBm. The transmit signal level can be
changed by using the CPAO and CPAI pins. See the figure 11 for adjusting the
transmit signal level. Control the ON/OFF of CPT transmission by using CPGC of
the control register.

PTYPE

Input pin for selecting the processor mode.
This selection determines the functions of READ, CS, ALE, WR, D1 and D0 pins.
When this pin is "1", the Intel processor mode is selected. When this pin is "0", the
Motorola processor mode (MSM7524-compatible) is selected. This pin should be
fixed at "0" or "1".

Power supply pin.

Input pin for controlling the power down mode.
When this pin is set to "1", the entire LSI enters the power down mode and each
functional operation stops. The DC level of the analog output pin becomes undefined.
The digital output pins (FXD0, CPD0) and status register indicate a non-detection
state. At that time, the control register CR and DTMF transmit register DTMFT are
cleared. ("0" is written)
The internal circuits (timer, etc. for each detector) also are reset.
After turning on the power, set this pin to "1" to reset the LSI before using this LSI.
When this pin is set to "0", the normal operation starts.

X1 and X2 are connected to a 3.579545 MHz crystal.
See "Oscillation Circuit" of the FUNCTIONAL DESCRIPTION for reference.

CLKO

3.579545 MHz clock output pin. This pin can drive one ML7005 device.

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Pin

Symbol

Type

Description

READ

Input pin for processor interface.
When PTYPE is "1" (Intel processor mode) :
This pin is the read control input pin. When this pin is set to "0", data in the
specified register is output to the bus lines (D3 to D0). At that time, CS must be "0".
See the figure 4 for processor interface timing.
When PTYPE is "0" (Motorola processor mode) :
This pin is the clock input pin (equivalent to SCLK of the MSM7524).
When in Write mode, data in D3 to D0 is written to the specified register at the
falling edge of the READ signal.
When in Read mode, data in the specified register is output to D3 to D0 when the
READ signal is "1", and D3 to D0 is opened when the READ signal is "0".
The READ signal is not necessarily a periodical signal.
See the figure 5 for processor interface timing.

Chip select input pin for processor interface.
When the CS signal is "0", read and write operations are possible.
When the CS signal is "1", read and write operations are impossible.

ALE

Input pin for processor interface.
When PTYPE is "1" (Intel processor mode) :
This pin is the address latch enable input pin.
The register address data in D1 to D0 is latched at the falling edge of ALE.
When PTYPE is "0" (Motorola processor mode) :
This pin is the address data input pin (equivalent to AD0 of the MSM7524).
When this pin is "1", data can be written to the control register (CR) and data can
be read from the status register (STR).
When this pin is "0", data can be written to the DTMF transmit register (DTMFT)
and data can be read from the DTMF receive register (DTMFR).

Input pin for processor interface.
When PTYPE is "1" (Intel processor mode) :
This pin is the Write control input.
Data in the data bus lines (D3 to D0) is written to the specified register. At that time,
CS must be "0".
When PTYPE is "0" (Motorola processor mode) :
This is the signal input pin for controlling the Read and Write modes
(equivalent to R/W of the MSM7524).
When this pin is "1", the LSI enters the Read mode. When this pin is "0", the LSI
enters the Write mode.

18 - 21

I/O

D3 - D0

4-bit data bus I/O pins for processor interface.
When PTYPE is "1" (Intel processor mode), D1 and D0 are also used for addressing.

CPDO

Digital output pin for CPT detector.
When a 400 Hz signal is input to the CPDIP and CPDIM pins, this pin is "1".
When the DOEN register is "0", this pin is fixed at "0".

GND

Ground pin.

DTGO

Analog output pin for DTMF signal generator.
The tone amplitude is approximately - 9.0 dBm for a low group and approximately
- 7.0 dBm for a high group. The transmit signal level can be changed by using the
DTAI and DTAO pins. See the figure 11 for adjusting the transmit signal level.
Control the ON/OFF of signal transmission by using MFC of the control register.

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Pin

Symbol

Type

Description

DTAI

Inverting input pin for operational amplifier used for adjusting the transmit output
level of the DTMF signal generator. The non-inverting input of this amplifier is
internally connected to SG. See the figure 11 for adjusting the transmit signal level.
When this amplifier is not used, the DTAO pin should be shorted to the DTAI pin.

DTAO

Output pin for operational amplifier used for adjusting the transmit output level of
the DTMF signal generator.

FXDO

Digital output pin for FAX signal (FX) detector.
When a 1300 Hz signal is input to the FXDIM, this pin is "1".
When a call progress tone (CPT) is received (CPD0="1"), this pin is forced to be "0".
When the DOEN register is "0", this pin is fixed at "0".

FXDIM

Inverting input pin for input amplifier used for detecting the FAX signal (FX).
See the figure 9 for adjusting the receive signal level.
When the FX detector is not used, the FXDIM pin should be shorted to the FXDIO pin.

FXDIO

Output pin for input amplifier used for detecting the FAX signal (FX).

CPDIP

Non-inverting input pin for input amplifier used for detecting the CPT.
See the figure 8 for adjusting the receive signal level.
When the CPT detector is not used, see the figure 10.

CPDIM

Inverting input pin for input amplifier used for detecting the CPT.

CPDIO

Output pin for input amplifier used for detecting the CPT.

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ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Rating

Unit

Power Supply Voltage

0.3 to +7.0

Ta = 25°C

With respect to GND

Input Voltage

0.3 to V

+ 0.3

Storage Temperature

stg

55 to +150

°C

Output Short Current

SHT

Short to V

or GND

Power Dissipation

100

Parameter

Symbol

Condition

Typ.

Unit

Power supply voltage

3.6

Operating Temperature Range

°C

Input Clock Frequency Deviation

CLK

Input Clock duty

DUTY

X1, X2 Load Capacitance

C1, C2

SG Bypass Capacitance

Bypass Capacitance

Digital Input Fall Time

Digital Ouput Load Capacitance

DL1

DL2

Frequency Deviation

ppm

An external clock is applied to

SG - GND

- GND

FCDO, CPDO, D3 to D0

CLKO

+25°C ±5°C

Min.

Max.

2.7

5.5

+85

+0.1

100

+100

0.1

Digital Input Rise Time

PD, READ, CS,

ALE, WR, D3 to D0

Temperature Characteristics

30°C to +85°C

100

+100

Equivalent Series Resistance

Load Capacitance

Crystal

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ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

AC CHARACTERISTICS

AC Characteristics 1 DTMF Signal Generator

*1 DTRIM, DTRIP, CPAI, DTAI, FXDIM, CPDIP, CPDIM
*2 DTRIO, CPAO, CPTGO, DTGO, DTAO, FXDIO, CPDIO
*3 DTRIO, CPAO, CPTGO, DTGO, DTAO, FXDIO, CPDIO, SG

Parameter

Symbol Condition or Applicable pin

Typ.

Unit

Power Supply Current

DD1

DD2

Digital Input Voltage

Digital Input Current

Digital Output Voltage

OLCK

0.06

Analog Input Resistance

Power Down Mode

= 0 V

Other than

CLK0

Min.

Max.

9.0

0.3V

+10

0.0

0.2

0.7 V

0.0

OHCK

CLKO, CL £ 20pF

0.06

0.2

Analog Output DC Potential

/20.1

Analog Output Load Resistance

OUT

4.0

5.0

= 100 mA

= 3 V

= 5 V

Operating Mode

0.5

0.0

= V

= 2.7 to 5.5 V

= 2.7 to 5.5 V, Ta = 30 to +85°C)

Parameter

Symbol

Condition

Typ.

Unit

DTMF Tone Transmit Amplitude

DTTL

dBm

DTTH

DDT

7.0

Out-of-Band Spurious

P51

Measured at

DTGO

With respect to

output signal

level measured

at DTGO

Min.

Max.

8.5

5.5

P20

DTDF

9.0

7.5

10.5

P60

P40

P75

P60

High Group Tone

Low Group Tone

2.0

3.0

+1.5

1.0

1.5

DTTH

DTTL

To Nominal

Frequency

THD

Harmonics -

Fundamental

4kHz to 8kHz

8kHz to 12kHz

12 kHz to each

4 kHz band

Tone Transmit Amplitude Ratio

Tone Frequency Accuracy

Total Harmonic Distortion

= 2.7 to 5.5 V, Ta = 30 to +85°C)

*1 0dBm = 0.775 Vrms (For all AC characteristics)

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AC Characteristics 2 Call Progress Tone (CPT) Generator

AC Characteristics 3 Call Progress Tone (CPT) Detector

Figure 1 CPT Detect Timing

Parameter

Symbol

Condition

Typ.

Unit

Tone Transmit Amplitude

CPT

2.5

dBm

Output Frequency

CPT

400

Min.

Max.

420

380

Total Harmonic Distortion

THD

CPT

Harmonics - Fundamental

= 2.7 to 5.5 V, Ta = 30 to +85°C)

Parameter

Symbol

Condition

Typ.

Unit

CPT Detect Amplitude

DETCP

Min.

Max.

dBm

= 350 to 450 Hz at CPDIO

2.7 V £ V

£ 5.5 V

= 2.7 to 5.5 V, Ta = 30 to +85°C)

4.5 V £ V

£ 5.5 V

CPT Non-detect Amplitude

REJCP

Time to Detect

DETCP

Time to Reject

REJCP

CPT Detect Delay Time

DELCP

CPT Detect Hold Time

HOLCP

CPT Detect Frequency

DETCP

CPT Non-detect Frequency

RETCP

Non-detect

Detect

290

530

450

350

See Figure 1.

CPDI

CPDO

(CPDR)

REJCP

DETCP

DELCP

HOLCP

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AC Characteristics 4 FAX Signal (FX) Detector

Figure 2 FX Detect Timing

Parameter

Symbol

Condition

Typ.

Unit

FX Detect Amplitude

DETFX

Min.

Max.

dBm

= 1280 to 1320 Hz at FXDIO

2.7 V £ V

£ 5.5 V

= 2.7 to 5.5 V, Ta = 30 to +85°C)

4.5 V £ V

£ 5.5 V

FX Non-detect Amplitude

REJFX

Time to Detect

DETFX

Time to Reject

REJFX

FX Detect Delay Time

DELFX

FX Detect Hold Time

HOLFX

FX Detect Frequency

DETFX

FX Non-detect Frequency

REJFX

Non-detect

Detect

1200

1380

1320

1280

See Figure 2.

FXDI

FXDO

(FXDR)

REJFX

DETFX

DELFX

HOLFX

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AC Characteristics 5 DTMF Receiver

*1 See the figure 3 for timing.

The input level includes the entire range indicated in V

DETDT1

and V

DETDT2

The input frequency includes the entire range indicated in f

DETDT

Parameter

Symbol

Condition

Typ.

Unit

DTMF Detect Amplitude

DETDT1

Min.

Max.

dBm

Per Frequency at DTRIO

2.7 V £ V

£ 5.5 V

= 2.7 to 5.5 V, Ta = 30 to +85°C)

4.5 V £ V

£ 5.5 V

DTMF Non-detect Amplitude

REJDT

Signal Repetition Time

CYCDT0

CYCDT1

Time to Detect

DETDT0

DETDT1

DTTIM = "0"

DTTIM = "1"

Detect Frequency

DETDT

+1.8

1.8

Non-detect Frequency

REJDT

3.8

+6.0

6.0

High

Group - V

Low

Group

Level Twist

TWIST

N/S (N : 0.3 to 3.4 kHz)

Noise to Signal Ratio

N/S

360 to 440 Hz

Dial Tone Rejection Ratio

REJDT

Time to Reject

REJDT0

REJDT1

Acceptable Drop Out Time

BRKDT10

BRKDT11

BRKDT20

BRKDT21

Interdigit Pause Time

POSDT0

POSDT1

Detect Delay Time

DELDT0

DELDT1

Detect Hold Time

HOLDT0

HOLDT1

SP Delay Time

0.4

To Nominal Frequency

DTTIM = "0"

DTTIM = "1"

DTTIM = "0"

DTTIM = "1"

DTTIM = "0"

DTTIM = "1"

DTTIM = "0"

DTTIM = "1"

DTTIM = "0"

DTTIM = "1"

DTTIM = "0"

DTTIM = "1"

DTTIM = "0"

DTTIM = "1"

Detect

Non-detect

SP = "1"

(Before output)

SP = "0"

(During output)

0.6

0.2

1.0

DTTIM = "1", "0"

DETDT2

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Timing When DTMF is received

DTMF Receive Data

AIN Signal

CYCDT

DETDT

POSDT

REJDT

BRKDT1

DELDT

HOLDT

BRKDT2

Figure 3 Timing When DTMF is Received

DETDT

: Time to Detect

When Time to Detect is the specified value of t

DETDT

or more, the DTMF signal is

normally received.

REJDT

: Time to Reject

When Time to Reject is the specified value of t

REJDT

or less, the input signal is ignored

and the SP and DTMF receive data are not output.

POSDT

: Interdigit Pause

When there is no input signal for the period of t

POSDT

or more, the DTMF receive data

and SP are reset. Even if the receive data is changed, when Interdigit Pause Time is the
value of t

POSDT

or less (including the change without Drop Out), SP remains at "0" and

the DTMF receive data may maintain its initial value.

BRKDT1

: Acceptable Drop Out Time 1

Acceptable Drop Out Time 1 is applied between when the input signal comes and when
SP becomes "0". Even if there is no input signal for the period of t

BRKDT1

or less, the SP

and DTMF receive data are normally output.

BRKDT2

: Acceptable Drop Out Time 2

Acceptable Drop Out Time 2 is applied when SP is "0" (when receive data is output).
Even if there is no input signal during signal reception for the period of t

BRKDT2

or less,

SP and DTMF receive data are not reset.

CYCDT

: Signal Repetition Time

Signal Repetition Time should be the specified value of t

CYCDT

or more so that a signal

is normally received.

DELDT

: Detect Delay Time

The DTMF receive data is output with a delay of the specified value of t

DELDT

after the

input signal appears.

HOLDT

: Detect Hold Time The SP and DTMF receive data outputs stop with a delay of the

specified value of t

HOLDT

after the input signal disappears.

SP Delay Time
The SP data is output with a delay of the specified value of t

after the DTMF receive

data is output. The DTMF receive data should be latched after detecting the fall of SP.

¡ Semiconductor

ML7005

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Processor Interface Charactceristics (Intel Processor Mode)

Figure 4 Processor Interface Timing (Intel Processor Mode : PTYPE="1")

Parameter

Symbol

Condition

Typ.

Unit

Address Data Setup Time

Address Data Hold Time

Min.

Max.

ALE Signal Time

= 2.7 to 5.5 V, Ta = 30 to +85°C)

Chip Select Setup Time before Read

CRS

Chip Select Hold Time after Read

CRH

READ Data Output Delay Time

£ 0.4 V, V

0.4 V

180

Data Float Time after Read

RDF

READ Signal Time

200

Chip Select Setup Time before Write

CWS

Chip Select Hold Time after Write

CWH

WR Signal Time

140

Data Setup Time before Write

Data Hold Time

ALE

READ

D0 to D3

RDF

CRS

CRH

CWH

CWS

ADDRESS

READ DATA

ADDRESS

WRITE DATA

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Processor Interface Characteristics (Motorola Processor Mode)

Figure 5 Processor Interface Timing (Motorola Processor Mode)

Parameter

Symbol

Condition

Typ.

Unit

READ Signal Period

CYC

READ Signal Pulse Width

"H" period

Min.

Max.

200

"L" period

200

= 2.7 to 5.5 V, Ta = 30 to +85°C)

ALE

ALE Æ READ

READ Æ ALE

CS Æ READ

READ Æ CS

WRS

WR Æ READ

WRH

READ Æ WR

D3 to D0

(Write)

DWS

D3 to D0 Æ READ

DWH

READ Æ D3 to D0

D3 to D0

(Read)

DRD

READ Æ D3 to D0

£ 0.4 V,

0.4 V

180

DRH

D3 to D0 Æ READ

See

Figure 5

SETUP Time

HOLD Time

SETUP Time

HOLD Time

SETUP Time

HOLD Time

SETUP Time

HOLD Time

Delay Time

Hold Time

READ

(Clock)

ALE

(Address)

(Read /

Write)

D3 to D0

DATA

"Write"

CYC

DWS

DWH

WRH

WRS

DATA

"Read"

CYC

DRH

WRH

WRS

DRD

¡ Semiconductor

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REGISTER DESCRIPTION

Register Interface Description

The ML7005 contains a 4-bit DTMF transmit data register (DTMFT), a 4-bit DTMF receive data
register (DTMFR), a 4-bit control register (CR), and a 4-bit status register (STR). The DTMFT and
CR registers are for Write-only and the DTMFR and STR registers are for Read-only.
When the PTYPE pin is "1", accessing the registers is possible in the Intel processor mode. When
the PTYPE pin is "0", accessing the registers is possible in the Motorola processor mode.
In the Intel processor mode (PTYPE="1"), when CS is "0", data can be written to the DTMFT and
CR registers by fetching data from D3 to D0 at the rising edge of the WR signal. When CS is "0",
the contents of DTMFR and STR can be transferred to D3 to D0 by setting READ to "0".
In the Motorola processor mode (PTYPE="0"), when CS and WR are "0", data can be written to
the DTMFT and CR registers by fetching D3 to D0 data and ALE at the falling edge of READ.
When CS is "0" and WR is "1", the contents of DTMFR and STR are transferred to D3 to D0 by
latching ALE at the rising edge of READ.
When the PD pin is set to "1" the DTMFT and CR registers are reset.

Table 1 Outline of Registers

Note:

The contents of the DTMFT and CR registers cannot be read.

Table 2 Register Names

Register

name

Accessing

(address) in Intel

processor mode

Description

Accessing in

Motorola

processor mode

Writing to DTMFT

ALE

Reading from DTMFR

DTMFT

DTMFR

Writing to CR

Reading from STR

STR

Register name

DTT0

DTR0

DTT1

DTR1

DTT2

DTR2

DTT3

DTR3

DTMFT

DTMFR

MFC

DOEN

DTTIM

CPGC

DETF

CPDR

FXDR

STR

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DTMFT and DTMFR Registers

16 kinds of DTMF transmit signals can be determined by setting the DTMFT register.
16 kinds of DTMF receive signals can be monitored from the DTMFR register.
The table 3 shows the DTMF signal codes.
Even if the DTMF transmit code is changed while the DTMF signal is being transmitted
(MFC="1"), the output frequency is not changed.

Table 3 DTMF Signal Code List

High group

signal (Hz)

Low group

signal (Hz)

1209

1336

697

1477

697

1209

770

DIGIT

DTT0

DTR0

DTT1

DTR1

DTT2

DTR2

DTT3

DTR3

1336

770

1477

770

1209

852

1336

852

1477

852

1336

941

1209

941

1477

941

1633

697

1633

770

1633

852

1633

941

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Control Register CR

Bit No.

Name

Description

CPGC

This bit is used to control the ON/OFF of call progress tone transmitting.
"0" : The GPTGO output is OFF and the SG level is output.
"1" : The GPTGO output is ON and CPT is output.

DTTIM

This bit is used to control the detect time of DTMF receiver.
"0" : Normal detect "1" : High-speed detect
When there is enough time, set to the normal detect mode (DTTIM = "0") because the
high-speed detect mode sometimes causes erroneous detection by noise or voice signal.

DOEN

This bit is used to control the call progress tone detector and FX detector.
"0" : The CPDO and FXDO output pins and CPDR and FXDR registers are fixed to "0".
"1" : The CPDO and FXDO output pins and CPDR and FXDR registers become valid.

MFC

This bit is used to control the ON/OFF of DTMF transmit output.
"0" : The DTGO output is OFF and the SG level is output.
"1" : The DTGO output is ON and the DTMF signal is output.

CPGC

DTTIM

DOEN

MFC

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Status Register STR

Bit No.

Name

Description

This bit is used to indicate whether the DTMF receive signal is being received.
"0" : Indicates that the valid DTMF signal is being received.
"1" : Indicates that the DTMF signal is not being received.

FXDR

This bit is used to indicate whether the FAX signal (FX) is being received.
"0" : Indicates that the FAX signal (FX) is not being received.
"1" : Indicates that the valid FAX signal (FX: 1300 Hz) is being received.
When a call progress tone is received (CPDO="1"), this bit is forced to be "0".
When the DOEN register is "0", this bit also is fixed at "0". This bit has the same
function as that of the FXDO.

CPDR

This bit is used to indicate whether the call progress tone is being received.
"0" : Indicates that the call progress tone is not being received.
"1" : Indicates that the valid call progress tone (400 Hz) is being received.
When the DOEN register is "0", this bit is fixed at "0". This bit has the same function
as that of the CPDO pin.

DETF

This is a flag to indicate that a detector has changed its status from a non-detect state to
a detect state.
This bit is "1" when:
(1) SP is changed from "1" to "0",
(2) FXDR is changed from "0" to "1", or
(3) CPDR is changed from "0" to "1".
This bit remains "0" even if a 1300 Hz or 400 Hz signal is input, because the FXDR
and CPDR are fixed at "0" when the DOEN regsiter is "0".
When the processor has read the status register, this bit is reset to "0".
When the processor does not read the status register after a signal is detected, this bit is
"0" after the detected signal disappears.

FXDR

CPDR

DETF

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FUNCTIONAL DESCRIPTION

Oscillation Circuit

The X1 and X2 should be connected by a 3.579545 MHz crystal.
When the load capacitance of the crystal is 16pF, X1 and GND should be connected by a 20 pF
capacitor, and X2 and GND also should be connected by a 20 pF capacitor.
If necessary, an external clock should be input to X1 via a 1000 pF capacitor, and X2 should be
left open.

Figure 6 Crystal Connection

Figure 7 External Clock Connection

DTMF Receiver, CPT Detector Input Level Adjustment

Adjust the input level according to the method shown in the figure 8.
Determine the value of a usable resistor so that the levels of the outputs (DTIO, CPDIO) of each
amplifier at a maximum input level are less than the maximum detect level described in the AC
Characteristics.

3.579545MHz

Figure 8 DTMF, CPT Input Level Adjustment

DTRIO

DTRIM

DTRIP

(CPDIM)

(CPDIP)

(CPDIO)

100 kW

, R

50 kW

CA 0.1 mF

Gain = 1 +

£ 10

DTRIP

DTRIM

(CPDIP)

(CPDIM)

Gain =

£ 10

DTRIO

(CPDIO)

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Figure 9 FX Input Level Adjustment

Processing the Input Pin when the DTMF Receiver and CPT Detector are not Used

Process the Input pin according to the method shown in the figure 10.

FXDIM

Gain =

£ 10

FXDIO

FX Detector Input Level Adjustment

Adjust the input level according to the method shown in the figure 9.
Determine the value of a usable resistor so that the output level of FXDIO is less than the
maximum detect level described in the AC Characteristics.

Figure 10 Processing the Unused Input Pin

DTRIP

(CPDIP)

DTRIM

(CPDIM)

DTRIO

(CPDIO)

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Figure 11 Analog Output Level Adjustment

Concurrent Operation of 4 Functions

The DTMF signal generator, DTMF signal detector, call progress tone generator, and call
progress tone detector can operate concurrently.
When both the DTMF signal generator and call progress tone generator operate concurrently, the
DTMF signal sometimes cannot be detected if the receive level of the DTMF signal is less than
-36 dBm.

Adjusting the Analog Output Level

Adjust the analog output level according to the method shown in the figure 11.
R

1.6 is always required when V

4.5 V.

In the case of R

> 1, if R

= A, the maximum analog output load resistance is 20*A (kW).

If V

is less than 4.5 V, R

1 is required.

DTAI (CPAI)

OUT

Gain =

DTGO (CPDGO)

DTAO (CPAO)

Generator

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Register Settings for Each Mode

An example of register settings for each mode is shown below.

Table 4 Register Setting

Mode

Power ON

DTMF Detect

(High Speed)

CPT Detect

Description

(1) Wait until power supply is

stabilized

(2) PD pin = "1"

(internal circuit is reset)

(3) Wait 200 ms or more

(4) PD pin = "0"

(5) CR setting

(1) Detect timing setting

(2) STR monitoring

(when not detected)

(3) STR monitoring

(when detected)

(4) DTMF receive data reading

(5)

STR monitoring (when

detected and after reading STR)

(6) STR monitoring (after

making the input signal OFF)

(1) CPT detect enable setting

(2) STR monitoring

(when not detected)

(3) STR monitoring

(when detected)

Address in

Intel

processor

mode

D1, D0

ALE

Motorola

processor

mode

Active

register

STR

DTMFR

STR

(4) STR monitoring (when

detected and after reading STR)

STR

DTMF

Transmit

(1) DTMF transmit data setting

DTMFT

(2) DTMF transmit ON

(3) Wait transmit ON time

(4) DTMF transmit OFF

(5) Wait transmit OFF time

(6) To transmit next data,

return to (1)

CPT Transmit (1) CPT transmit ON

(2) Wait transmit ON time

(3) CPT transmit OFF

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(Unit : mm)

PACKAGE DIMENSIONS

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

SSOP32-P-430-1.00-K

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more
0.60 TYP.

Mirror finish

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

E2Y0002-29-62

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