OKI Semiconductor

FEDL7021-03

Issue Date: Jun. 1, 2005

ML7021

Echo Canceler

GENERAL DESCRIPTION

The ML7021 is an improved version of the MSM7602 with the reduced cancelable echo delay
time and additional 2100Hz tone detection function.
The ML7021 is a low-power CMOS device for canceling echo (in an acoustic system or telephone
line) generated in a speech path.
Echo is canceled, in digital signal processing, by estimating the echo path and generating a
pseudo echo signal.
The ML7021 makes possible a quality conversation by controlling the noise level and preventing
howling with howling detector, double talk detector, attenuation function, and a gain control
function. The devise also controls the low level noise with a center clipping function.
Further, the ML7021 I/O interface supports m-law PCM . The use of a single chip CODEC, such
as the MSM7566/7704 (3 V) or MSM7543/7533 (5 V), allows a simplified and efficient echo
canceler configuration.

FEATURES

· Tone disable function
· Cancelable echo delay time:

For a single chip: 8 ms (max.)

· Echo attenuation

: 30 dB (typ.)

· Clock frequency

: 19.2 MHz

External input and internal oscillator circuit are provided.

· Power supply voltage : 2.7 V to 5.5 V
· Package:

28-pin plastic SSOP

(SSOP28-P-485-0.65-K)

(Product name : ML7021MB)

¡ Semiconductor

ML7021

PIN DESCRIPTIONS

(1/4)

Pin

Symbol

Type

Description

NLP

HCL

ADP

Control pin for the center clipping function.
This pin forces the SOUT output to a minimum value when the SOUT
signal is below 54 dBm0. Effective for reducing low-level noise.
· Single Chip or Master Chip in a Cascade Connection

"H": Center clip ON
"L": Center clip OFF

· Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.
Through mode control.
When this pin is in the through mode,
RIN and SIN data is output to ROUT and SOUT. At the same time, the
coefficient of the adaptive FIR filter is cleared.
· Single Chip or Master Chip in a Cascade Connection

"H": Through mode
"L": Normal mode (echo canceler operates)

· Slave Chip in a Cascade Connection

Same as the master chip

This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.

AFF coefficient control.
This pin stops updating of the adaptive FIR filter (AFF) coefficient and sets
the coefficient to a fixed value, when this pin is configured to be the
coefficient fix mode.
This pin is used when holding the AFF coefficient which has been once
converged.
· Single Chip or Master Chip in a Cascade Connection

"H": Coefficient fix mode
"L": Normal mode (coefficient update)

· Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.

¡ Semiconductor

ML7021

(2/4)

Pin

Symbol

Type

Description

ATT

INT

IRLD

SIN

RIN

SCK

Control for the ATT function.
This pin prevents howling by attenuators (ATT) for the RIN input and SOUT
output.
If there is input only to RIN, the ATT for the SOUT output is activated.
If there is no input to SIN, or if there is input to both SIN and RIN, the ATT
for the RIN input is activated.
Either the ATT for the RIN output or the ATT for the SOUT is always
activated in all cases, and the attenuation of ATT is 6 dB.
· Single Chip or Master Chip in a Cascade Connection

"H": ATT OFF
"L": ATT ON
"L" is recommended if performing echo cancellation.

· Slave Chip in a Cascade Connection

Fixed at "L"

This input signal is loaded in synchronization with the falling edge of the
INT signal or the rising edge of the RST signal.

Interrupt signal which starts 1 cycle (8 kHz) of the signal processing.
Signal processing starts when "H"-to-"L" transition is detected.
· Single Chip or Master Chip in a Cascade Connection

Connect the IRLD pin.

· Slave Chip in a Cascade Connection

Connect the IRLD pin of the master chip.

INT input is invalid for 100 ms after reset due to initialization.
Refer to the control pin connection example.

Load detection signal output when the SIN and RIN serial input data is
loaded in the internal registers.
· Single Chip

Connect to the INT pin.

· Master Chip in a Cascade Connection

Connect to the INT pin of the master chip and all the slave chips.

· Slave Chip in a Cascade Connection

Leave open.

Refer to the control pin connection example.

Transmit serial data.
Input the PCM signal synchronized to SYNC and SCK. Data is read in at
the falling edge of SCK.

Receive serial data.
Input the PCM signal synchronized to SYNC and SCK. Data is read in at
the falling edge of SCK.

Clock input for transmit/receive serial data.
This pin uses the external SCK or the SCKO.
Input the PCM CODEC transmit/receive clock (64 to 2048 kHz).

¡ Semiconductor

ML7021

(3/4)

Pin

Symbol

Type

Description

SYNC

SOUT

ROUT

X1/CLKIN

Sync signal for transmit/receive serial data.
This pin uses the external SYNC or SYNCO.
Input the PCM CODEC transmit/receive sync signal (8 kHz).

Transmit serial data.
Outputs the PCM signal synchronized to SYNC and SCK.
This pin is in a high impedance state during no data output.

Receive serial data.
Outputs the PCM signal synchronized to SYNC and SCK.
This pin is in a high impedance state during no data output.

Controls the howling detect function. This pin detets and cancels a howling
generated during hand-free talking for acoustic system.
This function is used to cancel acoustic echoes.
· Single Chip or Master Chip in a Cascade Connection

"L": Howling detector ON
"H": Howling detector OFF

· Slave Chip in a Cascade Connection
Fixed at "L"
External input for the basic clock (17.5 to 20 MHz) or for the crystal
oscillator.
When the internal sync signal (SYNCO, SCKO) is used, input the basic
clock of 19.2 MHz.

Crystal oscillator output.
Used to configure the oscilation circuit.
Refer to the internal clock generator circuit example.
When inputting the basic clock externally, insert a 5 pF capacitor with
excellent high frequency characteristics between X2 and GND.

PWDWN

Power-down mode control when powered down.

"L": Power-down mode
"H": Normal operation mode

During power-down mode, all input pins are disabled and output pins are
in the following states :

High impedance : SOUT, ROUT
"L": SYNCO, SCKO, MCKO
"H": OF1, OF2, X2
Holds the last state : WDT, IRLD

Reset after the power-down mode is released.

¡ Semiconductor

ML7021

(4/4)

Pin

Symbol

Type

Description

SYNCO

SCKO

RST

WDT

Input signal by which the gain controller for the RIN input is
controlled and the RIN input level is controlled and howling is prevented.
The gain controller adjusts the RIN input level when it is 10 dBm0 or
above. RIN input levels from 10 to 1.5 dBm0 will be suppressed to
10 dBm0 in the attenuation range from 0 to 8.5 dB.
RIN input levels above 1.5 dBm0 will always be attenuated by 8.5 dB.
· Single Chip or Master Chip in a Cascade Connection

"H": Gain control ON
"L": Gain control OFF
"H" is recommended for echo cancellation.

· Slave Chip in a Cascade Connection

Fixed at "L"

This pin is loaded in synchronization with the falling edge of the INT signal
or the rising edge of RST.

Test program end signal.
This signal is output when one cycle (8kHz) of processing is completed.
Leave it open.

Reset signal.

"L": Reset mode
"H": Normal operation mode

Due to initialization, input signals are disabled for 100 ms after reset
(after RST is returned from L to H).
Input the basic clock during the reset.
Output pins during the reset are in the following states :

High impedance: SOUT, ROUT
"L": WDT
"H": OF1, OF2

Not affected: X2, SYNCO, SCKO, IRLD, MCKO

After the power is turned on, initialize the LSI's internal registers by your

execution of HÆL sequence 1ms later than the master clock starts

normal oscilation.

This LSI starts a normal operation by releasing this pin to H after the

HÆL sequence above.

Here, this pin must stay L for 1ms or longer.

Transmit clock signal (256 kHz) for the PCM CODEC.
Connect to the SCK pin and the PCM CODEC transmit/receive clock pin.
Leave it open if using an external SCK.

8 kHz sync signal for the PCM CODEC.
Connect to the SYNC pin and the PCM CODEC transmit/receive sync pin.
Leave it open if using an external SYNC.

MCKO

Basic clock (19.2 MHz).

¡ Semiconductor

ML7021

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Input Voltage

Power Dissipation

Storage Temperature

Symbol

STG

Condition

Ta = 25°C

Rating

0.3 to +7

0.3 to V

+ 0.3

55 to +150

Unit

°C

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

DC Characteristics

= 2.7 V to 3.6 V, Ta = 40°C to +85°C)

Parameter

Output Load Capacitance

Input Capacitance

Power Supply Current (Stand-by)

Power Supply Current (Operating)

LOAD

DDS

DDO

PWDWN = "L"

0.1

Low Level Output Leakage Current

OZL

= V

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

High Level Output Leakage Current

Symbol

Condition

Min.

Typ.

Max.

Unit

0.1

0.4

2.2

OZH

= 40 mA

= 1.6 mA

= V

Parameter

Power Supply Voltage

High Level Input Voltage

Low Level Input Voltage

Operating Temperature

Symbol

Condition

Pins other than X1

Min.

2.7

2.0

Unit

°C

Typ.

3.3

+25

Max.

3.6

0.5

+85

= 2.7 V to 3.6 V)

X1 pin

2.2

Parameter

Power Supply Voltage

High Level Input Voltage

Low Level Input Voltage

Operating Temperature

Symbol

Condition

Pins other than X1, SCK

Min.

4.5

2.4

Unit

°C

Typ.

+25

Max.

5.5

0.8

+85

= 4.5 V to 5.5 V)

X1, SCK pins

3.5

¡ Semiconductor

ML7021

Condition

Min.

Typ.

Max.

Unit

Parameter

Symbol

Output Load Capacitance

Input Capacitance

Power Supply Current (Stand-by)

Power Supply Current (Operating)

DDO

DDS

LOAD

PWDWN = "L"

= 4.5 V to 5.5 V, Ta = 40°C to +85°C)

High Level Output Voltage

Low Level Output Voltage

High Level Input Current

Low Level Input Current

High Level Output Leakage Current

OZL

Low Level Output Leakage Current

= V

0.1

OZH

= V

= 1.6 mA

= 40 mA

4.2

0.4

0.1

Echo Canceler Characteristics (Refer to Characteristic Diagram)

Cancelable Echo Delay Time

Echo Attenuation

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

RES

= 10 dBm0

(5 kHz band white noise)

E. R. L. (echo return loss)

= 6 dB

= 8 ms

ATT, GC, NLP: OFF

= 10 dBm0

(5 kHz band white noise)

E. R. L. = 6 dB

ATT, GC, NLP: OFF

Tone Disable Characteristics

Tone Detection

Parameter

Min.

Typ.

Max.

Unit

Detection Frequency

2075

2100

2125

Detection Level

dBm0

Detection Time

380

Detection Level

dBm0

Release

1Semiconductor

ML7021

AC Characteristics

Parameter

Clock Frequency

When Internal Sync Signal is not used

Clock Cycle Time

When Internal Sync Signal is not used

Clock Duty Ratio

Clock High Level Pulse Width

fc = 19.2 MHz

Clock Low Level Pulse Width

fc = 19.2 MHz

Clock Rise Time

Clock Fall Time

Sync Clock Output Time

Internal Sync Clock Frequency

Internal Sync Clock Output Cycle Time

Internal Sync Clock Duty Ratio

Internal Sync Signal Output Delay Time

Internal Sync Signal Period

Internal Sync Signal Output Width

Transmit/receive Operation Clock Frequency

Transmit/receive Sync Clock Cycle Time

Transmit/receive Sync Clock Duty Ratio

Transmit/receive Sync Signal Period

Sync Timing

Sync Signal Width

Receive Signal Setup Time

Receive Data Input Time
IRLD Signal Output Delay Time

Serial Output Delay Time

Symbol

MCK

DMC

MCH

MCL

DCM

DCO

DCC

CYO

WSO

SCK

DSC

CYC

WSY

DIC

WIR

Min.

17.5

20.8

0.488

123

SCK

Typ.

19.2

52.08

256

3.9

125

SCK

Max.

57.14

31.3

2048

15.6

Min.

17.5

20.8

0.488

123

SCK

Typ.

19.2

52.08

256

3.9

125

SCK

Max.

57.14

31.3

2048

15.6

138

Unit

MHz

kHz

ms
ms

kHz

= 2.7 V to 3.6 V

= 4.5 V to 5.5 V

(Ta = 40°C to +85°C)

Reset Start Time

DRS

Reset End Time

DRE

Processing Operation Start Time

DIT

100

IRLD Signal Output Width

Reset Signal Input Width

138

Receive Signal Hold Time

CYC

-t

SCK

CYC

-t

SCK

¡ Semiconductor

ML7021

AC Characteristics (Continued)

Parameter

Power Down Start Time

Power Down End Time

Control Pin Setup Time (INT)

Control Pin Hold Time (INT)

Symbol

DPS

DTS

DTH

Min.

Typ.

Max.

Min.

120

Typ.

Max.

111

Unit

= 2.7 V to 3.6 V

= 4.5 V to 5.5 V

(Ta = 40°C to +85°C)

DPE

Control Pin Hold Time (RST)

DHR

Control Pin Setup Time (RST)

DSR

120

111

¡ Semiconductor

ML7021

HOW TO USE THE ML7021

The ML7021 cancels (based on the RIN signal) the echo which returns to SIN.
Connect the base signal to the R side and the echo generated signal to the S side.

Connection Methods According to Echos

Example 1:

Canceling acoustic echo (to handle acoustic echo from line input)

AFF

ROUT

SIN

RIN

SOUT

ML7021

CODEC

Line input

Acoustic echo

Example 2:

Canceling line echo (to handle line echo from microphone input)

AFF

RIN

SOUT

ROUT

SIN

ML7021

Line echo

Microphone input

CODEC

¡ Semiconductor

ML7021

ECHO CANCELER CHARACTERISTIC DIAGRAM

ERL vs. echo attenuation

Echo attenuation [dB]

ERL [dB]

Measurement Conditions
RIN input = 10 dBm 5 kHz band white noise
(0 dBm = 2.2 dBm0)
Echo delay time T

= 8 ms

ATT, GC, NLP = OFF
Power supply voltage 5 V

50 40 30 20 10

RIN input level vs. echo attenuation

Echo attenuation [dB]

RIN input level [dBm]

0 dBm = 2.2 dBm0

Measurement Conditions
RIN input: 5 kHz band white noise
Echo delay time T

= 8 ms

ERL = 6 dB
ATT, GC, NLP = OFF
Power supply voltage 5 V

Echo delay time vs. echo attenuation

Echo attenuation [dB]

Echo delay time [ms]

Measurement Conditions
RIN input = 10 dBm
5 kHz band white noise
(0 dBm = 2.2 dBm0)

ERL = 6 dB
ATT, GC, NLP = OFF
Power supply voltage 5 V

Note:

The characteristics above are for the MSM7543 (V

5 V, m-law interface). The

MSM7566 (V

3 V, m-law interface) provides the same characleristics without input

and output levels. Refer to the PCM CODEC data sheet.

MSM7543

(for both transmit and receive)

0 dBm0 = 0.6007 Vrms = 2.2 dBm (600 W)

MSM7566

(for transmit side)

0 dBm0 = 0.35 Vrms = 6.9 dBm (600 W)

(for receive side)

0 dBm0 = 0.5 Vrms = 3.8 dBm (600 W)

¡ Semiconductor

ML7021

APPLICATION CIRCUIT

Bidirectional Connection Example

Microphone input

Speaker output

21
22

13
12
15
10
16
19

5
6

AIN1
GSX1
AOUT1

DOUT1
DIN1
XSYNC
RSYNC
BCLK
A / m
PDN
CHP

AIN2

GSX2

AOUT2

DOUT2

DIN2

SGC

24
23
2

14
11

8
1

C10 C11

Line input

Line output

(AG)

For cancellation

of acoustic echo

ML7021MB

22
23

19
27

PWDWN

RST

14
15
21

SIN
ROUT

SYNC

SCK
SYNCO
SCKO

RST

PWDWN

MCKO

SOUT

RIN

NLP
HCL

ATT

ADP

WDT

SOUT
RIN

NLP
HCL

ATT
GC

WDT

X2
V

ADP

SIN

ROUT

SYNC

SCK

SYNCO

SCKO

RST

PWDWN

12
9

5
26

14
15
21

8
13

23
6

4
19
27

R1 = 20 kW
R2 = 20 kW
R3 = 2.2 kW
R4 = 10 kW
R10 = 10 kW

C1 = 1 mF
C2 = 10 mF
C3 = 0.1 mF
C4 = 0.1 mF

R5 = 20 kW
R6 = 20 kW
R7 = 2.2 kW
R8 = 10 kW
R11 = 10 kW

C5 = 1 mF
C6 = 10 mF
C7 = 0.1 mF
C8 = 0.1 mF

2ch CODEC

MSM7533VGS-K

For cancellation

of line echo
ML7021MB

R10

R11

INT

IRLD

C13

C12

IRLD

INT

R9 = 1 MW
C12 = 27 pF
C13 = 27 pF
X1 = 19.2 MHz
C14 = 5 pF

C14

C9 = 0.1 mF
C10 = 10 mF
C11 = 0.1 mF

Use the MSM7704-01GS-VK for PCM CODEC when V

= 3V.

The MSM7533 and MSM7704 are pin compatible.

¡ Semiconductor

ML7021

NOTES ON USE

1. Set echo return loss (ERL) to be attenuated. If the echo return loss is set to be

amplified, the echo can not be eliminated.
Refer to the characteristic diagram for ERL vs. echo attenuation quantity.

2. Set the level of the analog input so that the PCM CODEC does not overflow.

3. The recommended input level is 10 to 20 dBm0. Refer to the characteristic

diagram for the RIN input level vs. echo attenuation quantity.

4. Applying the tone signal to this echo canceler for long duration may decrease echo

attenuation.
When used with the HD pin "L" (howling detector ON), this echo canceler may
operate faultily if, while a signal is input to the RIN pin, a tone signal with a higher
level than the signal being input to RIN is input to the SIN pin.
A signal should therefore be input either to the RIN pin or to the SIN pin. If,
however, the tone signal is input to the SIN pin while a signal is input to the RIN
pin, the ADP, HD, or HCL pin must be set to "H".

5. For changes in the echo path (retransmit, circuit switching during transmission,

and so on), convergence may be difficult.
Perform a reset, to make it converge.
If the state of the echo path changes after a reset, convergence may again be
difficult.
In cases such as a change in the echo path, perform a reset each time.

6. When turning the power ON, set the PWDWN pin to "1" and input the basic clock

simultaneously with power ON.
If powering down immediately after power ON, be sure fast input 10 or more
clocks of the basic clock.

7. After powering ON, be sure to reset.

8. After the power down mode is released (when the PWDWN pin is changed from

"L" to "H"), be sure to reset the device.

9. If this canceler is used to cancel acoustic echoes, an echo attenuation may be less

than 30 dB.

¡ Semiconductor

ML7021

EXPLANATION OF TERMS

Attenuating Function :

This function prevents howling and controls the noise level with
the attenuator for the RIN input and SOUT output. Refer to the
explanation of pins (ATT pin).

Echo Attenuation :

If there is talking (input only to RIN) in the path of a rising echo
arises, the echo attenuation refers to the difference in the echo
return loss (canceled amount) when the echo canceler is not used
and when it is used.
Echo attenuation = (SOUT level during through mode operation)
(SOUT level during echo canceler operation) [dB]

Echo Delay Time :

This is the time from when the signal is output from ROUT until
it returns to SIN as an echo.

Acoustic Echo :

When using a hands free phone, and so on, the signal output from
the speaker echoes and is input again to the microphone. The
return signal is referred to as acoustic echo.

Telephone Line Echo :

This is a signal which is delayed midway in a telephone line and
returns as an echo, due to reasons such as a hybrid impedance
mismatch.

Gain Control Function :

This function prevents howling and controls the sound level with
a gain controller for the RIN input. Refer to the explanation of pins
(GC pin).

Center Clipping Function : This function forces the SOUT output to a minimum value when

the signal is below 54 dBm0. Refer to the explanation of pins
(NLP pin).

Double Talk Detection :

Double talk refers to a state in which the SIN and RIN signals are
input simultaneously. In a double talk state, a signal outside the
echo signal which is to be canceled can be input to the SIN input,
resulting in misoperation.
The double talk detector prevents such misoperation of the canceler.

Howling Detection :

This is the oscillating state caused by the acoustic coupling between

the loud speaker and the microphone during hands free talking.
Howling not only interferes with talking, but can also cause in
misoperation of the echo canceler.
The howling detector prevents such misoperation and prevents
howling.

Echo Return Loss (ERL) :

When the signal output from ROUT returns to SIN as an echo, ERL
refers to how much loss there is in the signal level during ROUT.
ERL = (ROUT level) (SIN level of the ROUT signal which returns
as an echo) [dB]
If ERL is positive (ROUT > SIN), the system is an attenuator
system.
If ERL is negative (ROUT < SIN), the system is an amplifier system.

1Semiconductor

ML7021

PACKAGE DIMENSIONS

(Unit : mm)

SSOP28-P-485-0.65-K

Mirror finish

Package material

Lead frame material

Pin treatment

Package weight (g)

Oki Electric Industry Co., Ltd.

Rev. No./Last Revised

Epoxy resin

42 alloy

Solder plating (

5 mm)

0.39 TYP.

3/Dec. 5, 1996

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method, temperature
and times).

1Semiconductor

ML7021

NOTICE

1. The information contained herein can change without notice owing to product and/or technical

improvements. Before using the product, please make sure that the information being referred to is
up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an

explanation for the standard action and performance of the product. When planning to use the product,
please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the
specified maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is

granted by us in connection with the use of the product and/or the information and drawings contained
herein. No responsibility is assumed by us for any infringement of a third party's right which may result
from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any
system or application where the failure of such system or application may result in the loss or damage of
property, or death or injury to humans.

Such applications include, but are not limited to, traffic and automotive equipment, safety devices,
aerospace equipment, nuclear power control, medical equipment, and life-support systems.

Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

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