Document Outline
- GENERAL DESCRIPTION
- FEATURES
- BLOCK DIAGRAM
- PIN ASSIGNMENT (TOP VIEW)
- PIN DESCRIPTIONS
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- PIN FUNCTION DESCRIPTIONS
- AIN0N, AIN0P, GSX0, AIN1N, GSX1
- VFRO0, VFRO1
- AVREF
- XI, XO
- PDNB
- DVDD0, DVDD1, DVDD2, AVDD
- DGND0, DGND1, DGND2, AGND
- TST0, TST1, TST2, TST3
- INTB
- A0 to A7
- D0 to D15
- CSB
- RDB
- WRB
- FR0B (DMARQ0B)
- FR1B (DMARQ1B)
- ACK0B
- ACK1B
- GPI0, GPI1
- GPO0, GPO1
- CLKSEL
- SYNC
- BCLK
- PCMO
- PCMI
- EXAMPLE OF CONFIGURATION
- EXAMPLE OF APPLICATION CIRCUIT
- PACKAGE DIMENSIONS
- REVISION HISTORY
OKI Semiconductor
FEDL7074-004DIGEST-01
Issue Date: Nov. 12, 2003
ML7074-004GA
VoIP CODEC
1/29
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or
representative.
GENERAL DESCRIPTION
The ML7074-004GA is a speech CODEC for VoIP. This LSI allows selection of G.729.A, or G.711 standard as a
speech CODEC. The LSI is optimum for adding VoIP functions to TAs, routers, etc., since it has the functions of
an echo canceller for 32 ms delay, DTMF detection, tone detection, tone generation, etc.
FEATURES
Single 3.3 V power supply operation (DV
DD
0, 1, 2, AV
DD
: 3.0 to 3.6 V)
Speech CODEC:
Selectable among G.729.A (8 kbps), G.711 (64 kbps)
-law, and A-law
Supports PLC (Packet Loss Concealment) function conforming to ITU-T G.711 Appendix I
Echo canceller for 32 ms delay
DTMF detect function
Tone detect function: 2 systems (1650 Hz, 2100 Hz: Detect frequency can be changed.)
Tone generate function: 2 systems
FSK generation function
Dial pulse detect function
Dial pulse transmit function
Internal 1-channel 16-bit timer
Built-in FIFO buffers (640 bytes) for transferring transmit and receive data
Frame/DMA (slave) interface selectable.
Master clock frequency: 4.096 MHz (crystal oscillation or external input)
Hardware or software power down operation possible.
Analog input/output type:
Two built-in input amplifiers
Two built-in output amplifiers, 10 k
driving
Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
2/29
BLOCK DIAGRAM
E
c
h
o
C
anc
e
l
l
e
r
DT
MF
_RE
C
+
-
AFF
D/
A
LP
F
G.
72
9.
A
TO
NE
_
G
E
N
0
(TONE
A
/B)
TX
Buf
f
e
r
0
RX
Buf
f
e
r
0
F
r
ame/D
M
A
C
ontr
o
l
l
er
IN
T
B
A0
-
A
7
C
ont
r
o
l
Re
gis
t
er
8b
D0
-D
15
16
b
VRE
F
CSB
RD
B
WR
B
FR0B
FR1B
AC
K
0
B
AC
K
1
B
AI
N
1
N
G
SX1
VF
RO
0
AVR
EF
OS
C
Po
w
e
r
PL
L
Sp
ee
c
h
Co
de
c
10
k
10k
DVD
D2
DGND
2
AVDD
AGND
PDNB
TST1
XI
XO
G.
71
1
TXGAIN
RX
GA
I
N
DVD
D1
DGND
1
DVD
D0
DGND
0
TST2
TST3
CK
G
N
MC
K
SY
NC(
8k
H
z
)
LPAD
G
PAD
ATTs
ATTr
B
u
s
Co
nt
ro
l Un
it
Ce
n
t
e
r
Cl
ip
E
n
c
o
der
G.
72
9.
A
G.
71
1
De
co
de
r
DTM
F
_
D
ET
INT
DT
M
F
_
D
E
T
TX
Buf
f
e
r
1
RX
Buf
f
e
r
1
AI
N
0
N
GSX0
10k
AI
N
0
P
L
i
ne
ar
P
C
M
Co
de
c
VFR
O
1
10
k
STG
A
IN
SYN
C
BCLK
PC
MI
PC
M
O
TO
N
E
_
D
ET1
TO
N
E
1_D
E
T
S/P
P/S
Se
r
i
a
l
I
/
F
T
O
NE0_D
E
T
T
O
NE1_D
E
T
GPI0
GPI1
GPO
0
GPO
1
TONE_D
ET0
TO
NE
0
_
D
E
T
FSK_
G
E
N
TST0
C
L
KS
EL
AM
P
0
AM
P
1
AM
P
2
AM
P
3
Sin
R
out
So
ut
Ri
n
A/
D
BP
F
Co
de
c
DPG
E
N
DP
DE
T
C
R
16-
B
0
(
G
P
I
0)
C
R
17-B0(G
PO
0)
DP
_
D
E
T
DP
_
D
ET
TIMER
D
T
MF
_CO
D
E[3:0]
D
T
MF_C
O
D
E
[
3:
0]
TO
NE_G
E
N
1
(TONE
C
/D)
G
.
711
Encod
e
r
G
.
711
Dec
o
d
e
r
FG
E
N
_FL
A
G
F
G
E
N
_FLAG
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
3/29
PIN ASSIGNMENT (TOP VIEW)
64-pin plastic QFP
49
AVREF
VFRO0
VFRO1
AVDD
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DGND0
DG
N
D
1
TST3
TST2
TS
T1
TS
T0
PC
M
O
PC
M
I
BCL
K
SY
N
C
D
V
DD1
RDB
WR
B
CS
B
FR0
B
FR1
B
DVDD0
A0
A1
A2
A3
A4
A5
A6
A7
DGND2
XI
XO
DVDD2
GP
I0
GP
I1
GP
O0
GP
O1
PDNB
IN
T
B
AC
K
0
B
AC
K
1
B
C
L
KS
EL
AIN1N
GSX1
AIN0P
AIN0N
GSX0
AGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
L7074-004
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
4/29
PIN DESCRIPTIONS
Pin
No.
Symbol
I/O PDNB = "0"
Description
1
TST1
I
"0"
Test control input 1: Normally input "0".
2
TST0
I
"0"
Test control input 0: Normally input "0".
3
PCMO
O
"Hi-z"
PCM data output
4
PCMI
I
I
PCM data input
I
CLKSEL = "0"
PCM shift clock input
5 BCLK I/O
"L"
CLKSEL = "1"
PCM shift clock output
I
CLKSEL = "0"
PCM sync signal 8 kHz input
6 SYNC I/O
"L"
CLKSEL = "1"
PCM sync signal 8 kHz output
7 DV
DD
0
Digital power supply
8
ACK0B
I
I
Transmit buffer DMA access acknowledge signal input
9
ACK1B
I
I
Receive buffer DMA access acknowledge signal input
10
FR0B
(DMARQ0B)
O "H"
FR0B: (CR11-B7 = "0")
Transmit buffer frame signal output
DMARQ0B: (CR11-B7 = "1")
Transmit buffer DMA access request signal output
11
FR1B
(DMARQ1B)
O "H"
FR1B: (CR11-B7 = "0")
Receive buffer frame signal output
DMARQ1B: (CR11-B7 = "1")
Receive buffer DMA access request signal output
12 INTB O
"H"
Interrupt request output
"L" level is output for about 1.0
s when an interrupt is generated.
13
CSB
I
I
Chip select control input
14
RDB
I
I
Read control input
15
WRB
I
I
Write control input
16
DGND0
I
Digital ground (0.0 V)
17 D0 I/O
I
Data
input/output
18 D1 I/O
I
Data
input/output
19 D2 I/O
I
Data
input/output
20 D3 I/O
I
Data
input/output
21 D4 I/O
I
Data
input/output
22 D5 I/O
I
Data
input/output
23 D6 I/O
I
Data
input/output
24 D7 I/O
I
Data
input/output
25 D8 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
26 D9 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
27 D10 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
28 D11 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
29 D12 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
30 D13 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
31 D14 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
32 D15 I/O
I
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = "1").
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
5/29
Pin
No.
Symbol
I/O PDNB = "0"
Description
33 DV
DD
1
Digital power supply
34 A0 I I
Address
input
35 A1 I I
Address
input
36 A2 I I
Address
input
37 A3 I I
Address
input
38 A4 I I
Address
input
39 A5 I I
Address
input
40 A6 I I
Address
input
41 A7 I I
Address
input
42 PDNB I "0"
Power down input
"0": Power down reset
"1": Normal operation
43 CLKSEL I I
SYNC and BCLK I/O control input
"0": SYNC and BCLK become inputs
"1": SYNC and BCLK become outputs
44 DGND1
Digital ground (0.0 V)
45 GPI0 I I
General-purpose input pin 0 (5 V tolerant input)
/Secondary function: Dial pulse detect input pin
46 GPI1 I I
General-purpose
input pin 1 (5 V tolerant input)
47 GPO0 O "L"
General-purpose output pin 0 (5 V tolerant output, can be pulled up
externally)
/Secondary function: Dial pulse transmit pin
48 GPO1 O "L"
General-purpose output pin 1 (5 V tolerant output, can be pulled up
externally)
49 AV
DD
Analog power supply
50
AIN0P
I
I
AMP0 non-inverted input
51
AIN0N
I
I
AMP0 inverted input
52 GSX0 O
"Hi-z"
AMP0 output (10 k
driving)
53 GSX1 O
"Hi-z"
AMP1 output (10 k
driving)
54
AIN1N
I
I
AMP1 inverted input
55
AVREF
O
"L"
Analog signal ground (1.4 V)
56 VFRO0 O
"Hi-z"
AMP2 Output (10 k
driving)
57 VFRO1 O
"Hi-z"
AMP3 Output (10 k
driving)
58 AGND
Analog ground (0.0 V)
59 DGND2
Digital ground (0.0 V)
60
XI
I
I
4.096 MHz crystal oscillator I/F, 4.096 MHz clock input
61
XO
O
"H"
4.096 MHz crystal oscillator I/F
62 DV
DD
2
Digital power supply
63
TST3
I
"0"
Test control input 3: Normally input "0".
64
TST2
I
"0"
Test control input 2: Normally input "0".
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
6/29
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Conditions
Rating
Unit
Analog power supply
voltage
VDA
-
0.3 to 5.0
V
Digital power supply voltage
V
DD
-
0.3 to 5.0
V
Analog input voltage
VAIN
Analog pins
-
0.3 to V
DD
+ 0.3
V
VDIN1
Normal digital pins
-
0.3 to V
DD
+ 0.3
V
Digital input voltage
VDIN2
5 V tolerant pins
-
0.3 to 6.0
V
Storage temperature range
Tstg
-
55 to +150
C
RECOMMENDED OPERATING CONDITIONS
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Analog power supply voltage
VDA
3.0 3.3 3.6 V
Digital power supply voltage
V
DD
3.0 3.3 3.6 V
Operating temperature range
Ta
-
20
60
C
VIH1
Digital input pins
2.0
V
DD
+
0.3
V
Digital high level input voltage
VIH2
GPI0 and GPI1 pins
2.0
5.5 V
Digital low level input voltage
VIL
Digital pins
-
0.3
0.8 V
Digital input rise time
tIR
Digital pins
2 20 ns
Digital input fall time
tIF
Digital pins
2 20 ns
Digital output load capacitance CDL
Digital
pins
50 pF
Capacitance of bypass capacitor
for AVREF
Cvref
Between AVREF and AGND 2.2+0.1
4.7+0.1
F
Master clock frequency
Fmck
MCK
-
0.01%
4.096 +0.01% MHz
PCM shift clock frequency
Fbclk
BCLK (at input)
64
2048 kHz
PCM sync signal frequency
Fsync
SYNC (at input)
8.0
kHz
Clock duty ratio
DRCLK
MCK, BCLK (at input)
40
50
60
%
tBS
BCLK to SYNC
(at input)
100
ns
PCM sync timing
tSB
SYNC to BCLK
(at input)
100
ns
PCM sync signal width
tWS
SYNC (at input)
1BCLK
100
s
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
7/29
ELECTRICAL CHARACTERISTICS
DC Characteristics
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
ISS
Standby state
(PDNB = "0", V
DD
= 3.3 V, Ta = 25
C)
5.0 20.0
A
I
DD
1
Operating state 1
In the PCM/IF mode
(SC_EN = "1", PCMIF_EN = "1",
AFE_EN = "1")
Connect a 4.096 MHz crystal oscillator
between XI and XO.
45.0 55.0 mA
Power supply current
I
DD
2
Operating state 2
When operating the whole system
(SC_EN = "1", PCMIF_EN = "0",
AFE_EN = "0")
Connect a 4.096 MHz crystal oscillator
between XI and XO.
50.0 65.0 mA
IIH
Vin = DV
DD
0.01 1.0
A
Digital input pin
input leakage current
IIL
Vin = DGND
-
1.0
-
0.01
A
IOZH
Vout = DV
DD
0.01 1.0
A
Digital I/O pin
output leakage current
IOZL
Vout = DGND
-
1.0
-
0.01
A
High level output
voltage
VOH
Digital output pins, I/O pins
IOH = 4.0 mA
IOH = 1.0 mA (XO pin)
2.2
V
Low level output
voltage
VOL
Digital output pins, I/O pins
IOL =
-
4.0 mA
IOL =
-
1.0 mA (XO pin)
0.4 V
Input capacitance *1 CIN
Input
pins
8 12
pF
Note: *1 Guaranteed design value
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
8/29
Analog Interface
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol Conditions
Min.
Typ.
Max.
Unit
Input resistance *1
RIN
AIN0N, AIN0P, AIN1N
10
M
Output load resistance
RL
GSX0, GSX1, VFRO0, VFRO1
10
k
Output load capacitance
CL
Analog output pins
50 pF
Offset voltage
VOF
VFRO0, VFRO1
-
40
40 mV
Output voltage level *2
VO
GSX0, GSX1, VFRO0, VFRO1
RL = 10 k
1.3 Vpp
Notes:
*1 Guaranteed design value
*2
-
7.7 dBm (600
) = 0 dBm0, +3.17 dBm0 = 1.3 Vpp
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
9/29
AC Characteristics
CODEC (Speech CODEC in G.711 (
-law) Mode)
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Conditions
Parameter Symbol
Frequency (Hz)
Level (dBm0)
Min. Typ. Max. Unit
LT1
0 to 60
25
dB
LT2
300 to 3000
-
0.15
0.20 dB
LT3
1020 Reference
value
LT4
3300
-
0.15
0.80 dB
LT5
3400 0
0.80 dB
Transmit frequency
characteristics
LT6
3968.75
0
13
dB
LR2
0 to 3000
-
0.15
0.20 dB
LR3
1020 Reference
value
LR4
3300
-
0.15
0.80 dB
LR5
3400 0
0.80 dB
Receive frequency
characteristics
LR6
3968.75
0
13
dB
SDT1
3 35
dBp
SDT2
0 35
dBp
SDT3
-
30
35
dBp
SDT4
-
40
28
dBp
Transmit signal to noise
ratio [*1]
SDT5
1020
-
45
23
dBp
SDR1
3 35
dBp
SDR2
0 35
dBp
SDR3
-
30
35
dBp
SDR4
-
40
28
dBp
Receive signal to noise
ratio [*1]
SDR5
1020
-
45
23
dBp
GTT1
3
-
0.2
0.2 dB
GTT2
-
10
Reference value
GTT3
-
40
-
0.2
0.2 dB
GTT4
-
50
-
0.6
0.6 dB
Transmit inter-level
loss error
GTT5
1020
-
55
-
1.2
1.2 dB
GTR1
3
-
0.2
0.2 dB
GTR2
-
10
Reference value
GTR3
-
40
-
0.2
0.2 dB
GTR4
-
50
-
0.6
0.6 dB
Receive inter-level loss
error
GTR5
1020
-
55
-
1.2
1.2 dB
NIDLT
Analog input =
AVREF
-
68
dBm0p
Idle channel noise
[*1]
NIDLR
PCMI = "1"
-
72
dBm0p
Transmit absolute level
[*2]
AVT 1020
0
0.285
0.320
0.359
Vrms
Receive absolute level
[*2]
AVR 1020
0
0.285
0.320
0.359
Vrms
PSRRT
30
dB
Power supply noise
reject ratio
PSRRR
Noise frequency
range: 0 to 50 kHz
Noise level: 50mVpp
30
dB
Notes: *1 Using P-message filter
*2 0.320 Vrms = 0 dBm0 =
-
7.7 dBm (600
)
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
10/29
Gain Setting (Speech CODEC in G.711 (
-law) Mode)
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Transmit and receive
gain setting accuracy
GAC
-
1.0
1.0 dB
Tone Output (Speech CODEC in G.711 (
-law) Mode)
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Frequency deviation
fDFT
Relative to set frequency
-
1.5
1.5 %
Output level
oLEV
Relative to set gain
-
2.0
2.0 dB
DTMF Detector, Other Detectors (Speech CODEC in G.711 (
-law) Mode)
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Detect level accuracy
dLAC
Relative to set detect level
-
2.5
2.5 dB
Echo Canceller
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
In the analog I/F mode
In the PCM I/F (16-bit linear) mode
35
Echo attenuation
eRES
In the PCM I/F (G.711) mode
30
dB
Erasable echo delay time
tECT
32 ms
Measurement method
Sin
Sout
Delay
White noise generator
Rout
Rin
ATT
E.R.L
(echo return loss)
Echo delay time
Echo Canceller
LPF
5 kHz
Level Meter
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OKI Semiconductor
ML7074-004GA
11/29
PDNB, XO, AVREF Timings
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol Conditions Min.
Typ.
Max.
Unit
Power down signal pulse
width
tPDNB PDNB
pin 1
s
Oscillation start-up time
txtal
2+
100 ms
AVREF rise time
tAVREF
AVREF = 1.4 (90%)
C5 = 4.7
F, C6 = 0.1
F
(See Fig. 9.)
600 ms
Initialization mode start-up
time
tINIT
1
s
*
is a value that depends on the oscillation stabilizing time when using a crystal oscillator.
Fig. 1 PDNB, XO, and AVREF timings
PDNB
AVREF
About
1.4 V
0 V
VDD
XO
0 V
VDD
txtal
0 V
t
AVREF
DVDD,
AVDD
0 V
VDD
t
PDNB
"1"
"0"
CR5-B7
(READY)
Initialization mode
t
INIT
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OKI Semiconductor
ML7074-004GA
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PCM I/F Mode
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Bit clock frequency
fBCLK
CDL = 20pF(at output)
-
0.1%
64 +0.1% kHz
Bit clock duty ratio
dBCLK
CDL = 20pF(at output)
45
50
55
%
Sync signal frequency
fSYNC
CDL = 20pF(at output)
-
0.1%
8 +0.1% kHz
dSYNC1
CDL = 20pF(at output)
At 64 kHz output
12.4 12.5 12.6
%
Sync signal duty ratio
dSYNC2
CDL = 20pF(at output)
At 128 kHz output
6.24 6.25 6.26
%
tBS
BCLK to SYNC
(at output)
100
ns
Transmit/receive signal sync
timing
tSB
SYNC to BCLK
(at output)
100
ns
Input setup time
tDS
100
-- ns
Input hold time
tDH
100
-- ns
tSDX
100 ns
Digital output delay time
tXD1
100 ns
tXD2
100 ns
Digital output hold time
tXD3
PCMO pin
Pull-up, pull-down resistors
RDL = 1 k
, CDL = 50 pF
100 ns
0
1
MSB
LSB
tWS
tDS
tDH
BCLK
SYNC
PCMI
tBS
tSB
2
3
4
5
6
7
8
-
16
G.711
LSB
16bit
linear
Fig. 2 PCM I/F mode input timing (long frame)
0
1
tWS
tDS
tDH
BCLK
SYNC
PCMI
tBS
tSB
2
3
4
5
6
7
8
9
-
MSB
LSB
G.711
17
LSB
16bit
linear
Fig. 3 PCM I/F mode input timing (short frame)
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OKI Semiconductor
ML7074-004GA
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0
1
LSB
tWS
BCLK
SYNC
PCMO
tBS
tSB
2
3
4
5
6
7
8
9
-
MSB
Hi-z
tSDX
tXD1
tXD2
tXD3
G.711
17
LSB
tXD3
16bit
linear
Fig. 4 PCM I/F mode output timing (long frame)
0
1
LSB
tWS
BCLK
SYNC
PCMO
tBS
tSB
2
3
4
5
6
7
8
9
10
MSB
Hi-z
tXD1
tXD2
tXD3
G.711
-
18
LSB
16bit
linear
tXD3
Fig. 5 PCM I/F mode output timing (short frame)
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Control Register Interface
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions Min.
Typ.
Max.
Unit
Address setup time
tAS
10
ns
Address hold time
tAH
10
ns
Write data setup time
tWDS
10
ns
Write data hold time
tWDH
10
ns
CSB setup time
tCS
10
ns
CSB hold time
tCH
10
ns
WRB pulse width
tWW
10
ns
Read data output delay time
tRDD
20 ns
Read data output hold time
tRDH
3
ns
RDB pulse width
tRW
25
ns
CSB disable time
tCD
CL = 50 pF
10
ns
Fig. 6 Control register interface
A7-A0
Input
D7-D0
I/O
CSB
Input
WRB
Input
RDB
Input
Write timing
Read timing
tAS
tAH
tWDS
tWDH
tCH
tRDD
tCS
tRDH
tWW
tRW
A1
D1
Input
A2
D2
Output
tCS
tCH
tAS
tAH
tCD
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ML7074-004GA
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Transmit and Receive Buffer Interface (in Frame Mode)
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol Conditions Min.
Typ.
Max.
Unit
FR1B setup time
tF1S
3
ns
FR1B output delay time
tF1D
20 ns
Address setup time
tAS
10
ns
Address hold time
tAH
10
ns
Write data setup time
tWDS
10
ns
Write data hold time
tWDH
10
ns
CSB setup time
tCS
10
ns
CSB hold time
tCH
10
ns
WRB pulse width
tWW
10
ns
FR0B setup time
tF0S
3
ns
FR0B output delay time
tF0D
20 ns
Read data output delay time
tRDD
30 ns
Read data output hold time
tRDH
3
ns
RDB pulse width
tRW
35
ns
CSB disable time
tCD
CL = 50 pF
10
ns
Fig. 7 Transmit and receive buffer interface (in frame mode)
A7-A0
Input
D15-D0
I/O
CSB
Input
WRB
Input
RDB
Input
Write timing
Read timing
tAS
tAH
tWDS
tWDH
tCH
tRDD
tCS
tRDH
tWW
tRW
A1
D1
Input
A2
D2
Output
tCS
tCH
tAS
tAH
FR1B
Output
FR0B
Output
tF1S
tF1D
tF0S
tF0D
tCD
A7-A0
Input
D15-D0
I/O
CSB
Input
WRB
Input
RDB
Input
Write timing
Read timing
tAS
tAH
tWDS
tWDH
tCH
tRDD
tCS
tRDH
tWW
tRW
A1
D1
Input
A2
D2
Output
tCS
tCH
tAS
tAH
FR1B
Output
FR0B
Output
tF1S
tF1D
tF0S
tF0D
tCD
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ML7074-004GA
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Transmit and Receive Buffer Interface (in DMA Mode)
(Unless otherwise specified, AV
DD
= 3.0 to 3.6 V, DV
DD
0, 1, 2 = 3.0 to 3.6 V, AGND = DGND0, 1, 2 = 0.0 V,
Ta =
-
20 to +60
C)
Parameter Symbol
Conditions Min.
Typ.
Max.
Unit
DMARQ1B setup time
tDR1S
3
ns
tDR1RD
25 ns
DMARQ1B output delay time
tDR1FD
25 ns
Address setup time
tAS
10
ns
Address hold time
tAH
10
ns
Write data setup time
tWDS
10
ns
Write data hold time
tWDH
10
ns
ACK setup time
tAKS
10
ns
ACK hold time
tAKH
10
ns
WRB pulse width
tWW
10
ns
DMARQ0B setup time
tDR0S
3
ns
tDR0RD
20 ns
DMARQ0B output delay time
tDR0FD
25 ns
Read data output delay time
tRDD
30 ns
Read data output hold time
tRDH
3
ns
RDB pulse width
tRW
35
ns
ACKB disable time
tAD
CL = 50 pF
10
ns
Fig. 8 Transmit and receive buffer interface (in DMA mode)
A7-A0
Input
D15-D0
I/O
ACK0B
Input
WRB
Input
RDB
Input
Write timing
Read timing
tAS
tAH
tWDS
tWDH
tRDD
tAKS
tRDH
tWW
tRW
A1
D1
Input
A2
D2
Output
tAKH
tAS
tAH
DMARQ1B
Output
DMARQ0B
Output
tDR1S
tDR1RD
tDR0S
tDR0RD
ACK1B
Input
tAKH
tAKS
tAD
tDR1FD
tDR0FD
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PIN FUNCTION DESCRIPTIONS
AIN0N, AIN0P, GSX0, AIN1N, GSX1
These are the analog transmit input and transmit level adjust pins. Each of AIN0N and AIN1N is connected to each
of the inverting input pins of the built-in transmit amplifiers AMP0 and AMP1, and AIN0P is connected to the
non-inverting input pin of AMP0. In addition, GSX0 and GSX1 are connected to the output pins of AMP0 and
AMP1, respectively. The selection between AMP0 and AMP1 is made by CR10-B0. See Fig. 9 for the method of
making level adjustment. During the power down mode (when PDNB = "0" or CR0-B7 = "1"), the outputs of
GSX0 and GSX1 go to the high impedance state. If AMP0 is not used in the specific application of this LSI, short
GSX0 with AIN0N and connect AIN0P with AVREF. When AMP1 is not used, short GSX1 with AIN1N.
Notice:
It is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise
will be generated if the amplifier selection is changed while conversation is in progress.
VFRO0, VFRO1
These are analog receive output pins and are connected to the output pins of the built-in receive amplifiers AMP2
and AMP3, respectively. The output signals of VFRO0 and VFRO1 can be selected using CR10-B1 and CR10-B2,
respectively. When selected ("1"), the received signal will be output, and when deselected ("0"), the AVREF
signal (about 1.4 V) will be output. In the power down mode, these pins will be in the high impedance state. It is
recommended to use these output signals via DC coupling capacitors.
Notice:
It is recommended to select the amplifier to be used before the conversation starts, since a small amount of noise is
generated if the output selection is changed while the conversation is in progress.
At the time of resetting or releasing from the reset state, it is recommended to select the AVREF as outputs of
VFRO0 and VFRO1.
Fig. 9 Analog interface
R1
R2
A/D
D/A
VREF
AIN1N
GSX1
AVREF
1 0
AIN0N
GSX0
10k
AIN0P
R3
R4
C6 0.1
F
C1
C2
C3
C4
VFRO0
10k
VFRO1
10k
C5
2.2 to 4.7
F
CR10-B0
CR10-B1
CR10-B2
Gain = R2/R1 <= 63(+36dB)
R1 : Variable
R2 : Max 500k
+
Gain = R4/R3 <=63(+36dB)
R3 : Variable
R4 : Max 500k
Out : Max 1.3Vp-p
Out : Max 1.3Vp-p
AMP0
AMP1
AMP3
AMP2
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ML7074-004GA
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AVREF
This is the output pin for the analog signal ground potential. The output potential at this pin will be about 1.4 V.
Connect a 2.2 to 4.7
F (aluminum electrolytic type) capacitor and a 0.1 F (ceramic type) capacitor in parallel
between this pin and the GND pin as bypass capacitors. The output at the AVREF pin goes to 0.0 V in the power
down mode. The voltage starts rising after the power down mode is released (PDNB = "1" and also CR0-B7 = "0").
The rise time is about 0.6 seconds.
XI, XO
These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master
clock signal.
The oscillations of the master clock oscillator will be stopped during a power down due to the PDNB signal or
during a software power down due to CR0-B7 (SPDN). The oscillations start when the power down condition is
released, and the internal clock supply of the LSI will be started after counting up the oscillation stabilization
period (of about 16 ms). Examples of crystal oscillator connection and external master clock input are shown in
Fig. 10.
Fig. 10 Examples of oscillator circuit and clock input
PDNB
This is the power down control input pin. The power down mode is entered when this pin goes to "0". In addition,
this pin also has the function of resetting the LSI. In order to prevent wrong operation of the LSI, carry out the
initial power-down reset after switching on the power using this PDNB pin. Also, keep the PDNB pin at "0" level
for 1
s or more to initiate the power down state.
Further, it is possible to carry out a power down reset of the LSI when the power is being supplied by performing
control of CR0-B7 (SPDN) in the sequence "0"
"1" "0".
The READY signal (CR5-B7) goes to "1" about 1.0 second after the power down mode is released thereby entering
the mode of setting various functions (initialization mode). See Fig. 1 for the timings of PDNB and AVREF, XO,
and the initialization mode.
Notice: At the time of switching on the power, start from the power down mode using PDNB.
DV
DD
0, DV
DD
1, DV
DD
2, AV
DD
These are power supply pins. DV
DD
0, 1, 2 are the power supply pins for the digital circuits while AV
DD
is the
power supply pin for the analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI and
connect as bypass capacitors a 10
F electrolytic capacitor and a 0.1 F ceramic capacitor in parallel between the
DGND and AGND pins.
DGND0, DGND1, DGND2, AGND
These are ground pins. GDND0, 1, 2 are the ground pins for the digital circuits and AGND is the ground pin for the
analog circuits of the LSI. Connect these pins together in the neighborhood of the LSI.
XI
XO
R
X'tal
C1
C2
4.096 MHz
X'tal(4.096 MHz)
Daishinku Co., Ltd.
AT-49
C2
R
10pF
1M
PDNB
To internal
circuits
CR0-B7
(SPDN)
XI
XO
Open
PDNB
To internal
circuits
CR0-B7
(SPDN)
C1
5pF
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ML7074-004GA
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TST0, TST1, TST2, TST3
These are input pins for testing purposes only. Keep the inputs to these pins at the "0" level during normal use
conditions.
INTB
This is the interrupt request output pin. An "L" level is output for a duration of about 1.0
s at this pin when there
is a change in state of an interrupt cause.
This output will be maintained at the "H" level when there is no change in state of any of the interrupt causes. The
actual interrupt cause generating the interrupt can be verified by reading CR3, CR4, and CR5. The different
interrupt causes are described below.
Underflow error (CR3-B0)
An interrupt is generated when an internal read from the receive buffer occurs before the writing into the receive
buffer from the MCU has been completed.
An interrupt is generated when a normal writing is made in the receive buffer by the MCU and the underflow
error is released.
Overrun error (CR3-B1)
An interrupt is generated when an internal write of the next data into the transmit buffer occurs before the
transmit buffer data read out from the MCU has been completed.
An interrupt is generated when a normal read out is made from the transmit buffer by the MCU and the overrun
error is released.
When a dial pulse is detected (CR4-B6).
When a DTMF signal is detected (CR4-B4).
When DTMF_CODEC0, 1, 2, 3 are detected (CR4-B0, B1, B2, B3).
An interrupt is generated when a DTMF signal is detected.
An interrupt is generated when there is a change from the DTMF signal detected state to the no-detected state.
An interrupt is generated when there is a change in the detected code (CR4-B0, B1, B2, B3) in the condition in
which a DTMF signal is being detected.
When TONE0 is detected (CR3-B3).
An interrupt is generated when a 1650 Hz tone signal is detected.
An interrupt is generated when there is a change to the non-detection condition in the tone signal detection
condition.
When TONE1 is detected (CR3-B4).
An interrupt is generated when a 2100 Hz tone signal is detected.
An interrupt is generated when there is a change to the non-detection condition in the tone signal detection
condition.
When DSP_ERR is detected (CR3-B7).
An interrupt is generated when any error occurs in the DSP inside the LSI.
When FGEN_FLAG is cleared (CR5-B0).
FGEN_FLAG is cleared to "0" and an interrupt is generated when data settings are enabled to output data setting
register FGEN_D[7:0] (CR18) in the FSK generator.
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A0 to A7
These are the address input pins for use during an access of the frame, DMA, or control registers. The different
addresses will be the following.
Transmit buffer (TX Buffer)
A7 to A0 = 10xxxxxxb (the lower 6 bits are not valid)
Receive buffer (RX Buffer)
A7 to A0 = 01xxxxxxb (the lower 6 bits are not valid)
Control register (CR)
A7 to A0 = 00xxxxxxb
D0 to D15
These are the data input/output pins for use during an access of the frame, DMA, or control registers. Connect
pull-up resistors to these pins since they are I/O pins. When the 8-bit bus access method is selected by CR11-B5,
only D0 to D7 become valid. Since the higher 8 bits D8 to D15 will always be in the input state when the 8-bit bus
access method is selected (CR11-B5 = "1"), tie them to "0" or "1" inputs.
CSB
This is the chip select input pin for use during a frame or control register access.
RDB
This is the read enable input pin for use during a frame, DMA, or control register access.
WRB
This is the write enable input pin for use during a frame, DMA, or control register access.
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FR0B (DMARQ0B)
FR0B (In frame mode, CR11-B7 = "0")
This is the transmit frame output pin which outputs the signal when the transmit buffer is full during frame
access. This pin outputs an "L" level when the transmit buffer becomes full, and maintains that "L" level output
until a specific number of words are read out from the MCU.
DMARQ0B (In DMA mode, CR11-B7 = "1")
This is the DMA request output pin which outputs the signal when the transmit buffer is full during DMA access.
This output becomes "L" when the transmit buffer becomes full, and returns to the "H" level automatically on
the falling edge of the read enable signal (RDB = "1"
"0") when there is an acknowledgement signal (ACK0B
= "0") from the MCU. This relationship is repeated until a specific number of words are read out from the MCU.
FR1B (DMARQ1B)
FR1B (In frame mode, CR11-B7 = "0")
This is the receive frame output pin which outputs the signal when the receive buffer is empty during frame
access. This pin outputs an "L" level when the receive buffer becomes empty, and maintains that "L" level
output until a specific number of words are written from the MCU.
DMARQ1B (In DMA mode, CR11-B7 = "1")
This is the DMA request output pin which outputs the signal when the receive buffer is empty during DMA
access. This output becomes "L" when the receive buffer becomes empty, and returns to the "H" level
automatically on the falling edge of the write enable signal (WRB = "1"
"0") when there is an
acknowledgement signal (ACK1B = "0") from the MCU. This relationship is repeated until a specific number of
words are written from the MCU.
ACK0B
This is the DMA acknowledgement input pin for the DMARQ0B signal during DMA access of the transmit buffer
and becomes valid in the DMA mode (CR11-B7 = "1").
Tie this pin to "1" when using this LSI in the frame access mode (CR11-B7 = "0").
ACK1B
This is the DMA acknowledgement input pin for the DMARQ1B signal during DMA access of the receive buffer
and becomes valid in the DMA mode (CR11-B7 = "1").
Tie this pin to "1" when using this LSI in the frame access mode (CR11-B7 = "0").
GPI0, GPI1
These are general-purpose input pins. The state ("1" or "0") of each of these GPI0 and GPI1 pins can be read out
respectively from CR16-B0 and CR16-B1. Further, GPI0 becomes the input pin for the dial pulse detector
(DPDET) in the secondary functions.
GPO0, GPO1
These are general-purpose output pins. The values set in CR17-B0 and CR17-B1 are output at these pins GPO0
and GPO1, respectively. Further, GPO0 becomes the output pin for the dial pulse generator (DPGEN) in the
secondary functions.
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CLKSEL
This is the input/output control input pin of SYNC and BCLK. The pin becomes input at "0" level and output at
"1" level.
SYNC
This is the 8 kHz sync signal input/output pin of PCM signals. When CLKSEL is "0", input continuously an 8 kHz
clock synchronous with BCLK. Further, when CLKSEL is "1", this pin outputs an 8 kHz clock synchronous with
BCLK. Long frame synchronization is used when CR0-B1 (LONG/SHORT) is "0" and short frame
synchronization is used when it is "1".
BCLK
This is the shift clock input/output pin for the PCM signal. When CLKSEL is "0", it is necessary to input to this pin
a clock signal that is synchronous with SYNC. Input a 64 to 2048 kHz clock when the G.711 mode has been
selected, and input a 128 to 2048 kHz clock when the 16-bit linear mode has been selected. When CLKSEL is "1",
this pin outputs a clock that is synchronous with SYNC. This pin outputs a 64 kHz clock when the G.711 mode has
been selected, and outputs an 128 kHz clock when the 16-bit linear mode or G.729.A mode has been selected.
Note: The input/output control and frequencies of the above SYNC and BLCK signals will be as shown in Table 1
below.
Table 1 Input/output control of SYNC and BCLK
CLKSEL SYNC
BCLK
Remarks
"0"
Input
(8 kHz)
Input
(64 kHz to 2048 kHz)
Input a continuous clock after starting the power
supply.
Input a 64 to 2048 kHz clock when G.711 is selected.
Input a 128 to 2048 kHz clock when 16-bit linear
mode is selected.
"1"
Output
(8 kHz)
Output
(64 kHz or 128 kHz)
An "L" level is output during the power down mode.
A 64 kHz clock is output when G.711 is selected.
A 128 kHz clock is output when G.729.A or 16-bit
linear mode is selected.
PCMO
This is the PCM signal output pin for the transmitting section. The PCM signal is output in synchronization with
the rising edges of SYNC and BCLK. The PCMO outputs the data only during the valid data segment in the
selected coding format and goes to the high impedance state during all other segments. The basic timing chart of
the PCM I/F mode is shown in Fig. 11. The PCMO output will be in the high impedance state when the PCM I/F
mode is not used (CR12-B0 = "0").
PCMI
This is the PCM signal input pin for the receiving section. The data is entered starting from the MSB by shift on the
falling edge of BCLK.
The basic timing chart of the PCM I/F mode is shown in Fig. 11.
Fix input to "0" or "1" when the PCM I/F mode (CR12-B0 = "0") is not used.
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Fig. 11 PCM I/F mode timing diagram
BCLK
(IN/OUT))
PCMI
SYNC
(IN/OUT)
- 16-Bit linear
- Long frame synchronization mode (CR0-B1="0")
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
BCLK
(IN/OUT)
PCMO
SYNC
(IN/OUT))
- G.711(
-law,A-law)
- Short frame synchronization mode(CR0-B1="1")
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Hi-z
Hi-z
Hi-z
PCMO
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Hi-z
Hi-z
Hi-z
PCMI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
BCLK
(IN/OUT))
PCMI
SYNC
(IN/OUT)
D15
D14
D13
D12
D11
D10
D9
D8
BCLK
(IN/OUT)
PCMO
SYNC
(IN/OUT))
- 16-Bit linear
- Short frame synchronization mode (CR0-B1="1")
Hi-z
PCMO
Hi-z
Hi-z
PCMI
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D7
D6
D5
D15
D14
D13
D12
D11
D10
D9
D8
:
:
D15
D14
D13
D12
D11
D10
D9
D8
Hi-z
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D7
D6
D15
D14
D13
D12
D11
D10
D9
D8
:
:
- G.711(
-law,A-law)
- Long frame synchronization mode (CR0-B1="0")
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
24/29
EXAMPLE OF CONFIGURATION
Analog I/F mode
Echo Canceller
DTMF_REC
+
-
AFF
D/A
LPF
G.729.A
TONE_GEN0
(TONEA/B)
TX
Buffer0
RX
Buffer0
Frame/DMA
Controller
INTB
A0-A7
Control
Register
8b
D0-D15
16b
VREF
CSB
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
AIN1N
GSX1
VFRO0
AVREF
OSC
Power
PLL
Speech Codec
10k
10k
DV
DD2
DG
ND2
AV
D
D
AG
N
D
PD
N
B
TS
T1
XI
XO
G.711
TXGAIN
RXGAIN
DV
DD1
DG
ND1
DV
DD0
DG
ND0
TS
T2
TS
T3
CKGN
MCK
SYNC(8kHz)
LPAD
GPAD
ATTs
ATTr
Bus Control Unit
Center
Clip
Encoder
G.729.A
G.711
Decoder
DTMF_DET
INT
DTMF_DET
TX
Buffer1
RX
Buffer1
AIN0N
GSX0
10k
AIN0P
Linear PCM Codec
VFRO1
10k
STGAIN
SYNC
BCLK
PCMI
PCMO
TONE_DET1
TONE1_DET
S/P
P/S
Serial I/F
TONE0_DET
TONE1_DET
GP
I
0
GP
I
1
GPO
0
GPO
1
TONE_DET0
TONE0_DET
FSK_GEN
TS
T0
CLKSEL
AMP0
AMP1
AMP2
AMP3
Sin
Rout
Sout
Rin
A/D
BPF
Codec
DPGEN
DPDET
CR16-B0(GPI0)
CR17-B0(GPO0)
DP_DET
DP_DET
TIMER
DTMF_CODE[3:0]
DTMF_CODE[3:0]
TONE_GEN1
(TONEC/D)
G.711
Encoder
G.711
Decoder
FGEN_FLAG
FGEN_FLAG
Function stopped
Cannot be used
Example of settings in the initialization mode
CR15 = 40h * This is mandatory.
CR6=0Fh,CR7=FFh,CR8=00h,CR9=01h,CR1=80h (Address : 0FFFh, Data : 0001h)
* This is mandatory. As for how to set them, refer to Method of Accessing and Controlling Internal Data Memory.
CR11 = 00h (Frame/10 ms/16B/Speech CODEC = G.729.A)
Various settings
CR0 = 09h (OPE_STAT = "1")
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
25/29
PCM I/F Mode
Echo Canceller
DTMF_REC
+
-
AFF
D/A
LPF
G.729.A
TONE_GEN0
(TONEA/B)
TX
Buffer0
RX
Buffer0
Frame/DMA
Controller
INTB
A0-A7
Control
Register
8b
D0-D15
16b
VREF
CSB
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
AIN1N
GSX1
VFRO0
AVREF
OSC
Power
PLL
Speech Codec
10k
10k
DV
DD2
DG
ND2
AV
D
D
AG
N
D
P
DNB
TS
T1
XI
XO
G.711
TXGAIN
RXGAIN
DV
DD1
DG
ND1
DV
DD0
DG
ND0
TS
T2
TS
T3
CKGN
MCK
SYNC(8kHz)
LPAD
GPAD
ATTs
ATTr
Bus Control Unit
Center
Clip
Encoder
G.729.A
G.711
Decoder
DTMF_DET
INT
DTMF_DET
TX
Buffer1
RX
Buffer1
AIN0N
GSX0
10k
AIN0P
Linear PCM Codec
VFRO1
10k
STGAIN
SYNC
BCLK
PCMI
PCMO
TONE_DET1
TONE1_DET
S/P
P/S
Serial I/F
TONE0_DET
TONE1_DET
GP
I0
GP
I1
GPO
0
GPO
1
TONE_DET0
TONE0_DET
FSK_GEN
TS
T0
CLKSEL
AMP0
AMP1
AMP2
AMP3
Sin
Rout
Sout
Rin
A/D
BPF
Codec
DPGEN
DPDET
CR16-B0(GPI0)
CR17-B0(GPO0)
DP_DET
DP_DET
TIMER
DTMF_CODE[3:
0]
DTMF_CODE[3:0]
TONE_GEN1
(TONEC/D)
G.711
Encoder
G.711
Decoder
Function stopped
Cannot be used
FGEN_FLAG
FGEN_FLAG
Examples of settings in the initialization mode
CR15 = 40h * This is mandatory.
CR6=0Fh,CR7=FFh,CR8=00h,CR9=01h,CR1=80h (Address : 0FFFh, Data : 0001h)
* This is mandatory. As for how to set them, refer to Method of Accessing and Controlling Internal Data Memory.
CR10 = 00h (VFRO1 = AVREF/VFRO0 = AVREF)
CR11 = 00h (Frame/10 ms/16B/PCMIF = 16-bit linear)
CR12 = 01h (Speech CODEC = G.729.A/PCMIF_EN = "1")
Various settings
CR0 = 29h (AFE_EN = Power down/LONG/OPE_STAT = "1")
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
26/29
EXAMPLE OF APPLICATION CIRCUIT
49
AVREF
VFRO0
VFRO1
AVDD
50
51
52
53
54
55
56
57
58
59
60
61
62
63
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TST3
TST2
DGND2
XI
XO
DVDD2
AIN1N
GSX1
AIN0P
AIN0N
GSX0
AGND
ML7074
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DGND0
TST1
TST0
PCMO
PCMI
BCLK
SYNC
RDB
WRB
CSB
FR0B
FR1B
DVDD0
INTB
ACK0B
ACK1B
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DGND1
DVDD1
A0
A1
A2
A3
A4
A5
A6
A7
GPI0
GPI1
GPO0
GPO1
PDNB
CLKSEL
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
64
+3.3V
+3.3V
+3.3V
open
open
open
Power down control
MCU
I/F
General-
purpose
input pins
4.096 MHz
crystal
oscillator
Analog
input
PCM
I/F
Analog
output
Conditions:
- When using analog
interface
- Frame mode
- SYNC and BCLK are
output (CLKSEL="1")
General-
purpose
output pins
16
1.4V
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
27/29
PACKAGE DIMENSIONS
QFP64-P-1414-0.80-BK
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating (
J
5m)
Package weight (g)
0.87 TYP.
5
Rev. No./Last Revised
6/Feb. 23, 2001
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity
absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product
name, package name, pin number, package code and desired mounting conditions (reflow method,
temperature and times).
(Unit: mm)
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
28/29
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
Description
FEDL7074-004DIGEST-
01
Nov. 12, 2003
Final edition 1
FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
29/29
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted
by us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any
system or application that requires special or enhanced quality and reliability characteristics nor in any system
or application where the failure of such system or application may result in the loss or damage of property, or
death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
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