OKI Semiconductor
FEDL70Q5110LA-01
Issue Date:Sep.2, 2002
ML70Q5110LA
Bluetooth Baseband Controller IC
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GENERAL DESCRIPTION
The ML70Q5110LA is a CMOS digital IC for use in 2.4 GHz band BluetoothTM systems. This IC incorporates the
ARM7TDMI
as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety
of applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth
Protocol Stack Software, data/voice communications are possible while maintaining interconnectivity with other
Bluetooth systems. Also this IC is equiped with 2 Mbit Flash ROM to reduce the external parts.
FEATURES
Compliant to Bluetooth Specification (Ver. 1.1)
The
ARM7TDMI
is installed as the CPU (operation at a maximum of 32 MHz in this LSI)
1-Ch, 16-bit auto-reload timer
3-Ch, 18-bit auto-reload timer
Interrupt controller (17 causes)
Built-in 8 kbyte, 4-Way Unified Cache
Built-in 32 kbyte
Up to a total of 2 Mbyte of SRAM, ROM, and Flash ROM can be connected to the external memory bus.
Built-in 2Mbit Flash ROM
- Endurance 10
4
cycles
Selectable master clock (12/13/16 MHz).
PCM-CVSD transcoder is installed.
Installed
interfaces:
- UART
(*)
interface (Up to 921.6 Kbps)
- USB
(*)
interface (conforms to USB1.1)
- UART/synchronous serial port interface
- General-purpose I/O interface (programmable interrupts)
- PCM interface (PCMLinear/A-law/
-law can be selected)
- JTAG interface
(*)
This mark indicates interfaces that support the HCI command.
Built-in Regulator and Power-on-Reset
Single power supply voltage: 3.0 to 3.6 V
Package: 144-pin BGA (P-LFBGA144-1111-0.80-MC)
(Dimensions: 11 mm
11 mm
1.5 mm; pin pitch: 0.8 mm)
ARM and ARM7TDMI are registered trademarks of ARM Ltd., UK.
Thumb is trademark of ARM Ltd., UK.
BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry.
The information contained herein can change without notice owing to the product being under development.
FEDL70Q5110LA-01
OKI Semiconductor
ML70Q5110LA
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ABSOLUTE MAXIMUM RATINGS
Parameter Symbol
Conditions Rating Unit
Power supply voltage
V
DD
--
0.3 to +4.5
V
Input voltage
V
I
--
0.3 to +4.5
V
Allowable power dissipation
P
d
--
1.35 W
Storage temperature
T
stg
--
55 to 150
C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Power supply voltage
V
DD
-- 3.0
3.3
3.6
V
"H" level input voltage
Vih
--
2.2
--
3.6
V
"L" level input voltage
Vil
--
0
--
0.8
V
Operating temperature
Ta
--
40
--
85
C
INTERNAL FLASH ROM PROGRAMMING CONDITIONS
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply voltage
V
DD
--
3.0 3.3 3.6
V
During Read
40
--
85
C
Operating temperature
Ta
During Programming
0
--
85
C
ELECTRICAL CHARACTERISTICS
DC Characteristics(1) (Except USB port)
(V
DD
= 3.3 V 0.3 V, Ta = 40 to 85C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
"H" level output voltage
Voh
Ioh = 2 mA
2.4
--
--
V
"L" level output voltage
Vol
Iol = 2mA
--
--
0.4
V
Input leak current
Ii
Vi = GND to 3.6 V
10
--
10
A
Output leak current
Io
Vo = GND to V
DD
10 -- 10
A
Power supply current (during
operation)
Iddo
During 32 MHz
operation
0 70 90 mA
Power supply current (during
stand-by)
Idds CLK
Stopped --
200
800
A
DC Characteristics(2) USB port (D+, D)
(V
DD
= 3.3 V 0.3 V, Ta = 40 to 85C)
Parameter Symbol
Conditions
Min.
Typ.
Max.
Unit
Differential input sensitivity
V
DI
{(D+) (D)}
0.2
--
--
V
Differential common mode
range
V
CM
Includes
VDI
0.8
-- 2.5
V
Single ended receiver threshold
V
SE
--
0.8
--
2.0
V
"H" output voltage
V
OH
15
K
to GND
2.8
--
3.6
V
"L" output voltage
V
OL
1.5
K
to 3.6 V
--
--
0.3
V
Output leakage current
I
LO
0 V < V
IN
< V
DD
10
--
+10
A
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ML70Q5110LA
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PIN PLACEMENT
TOP VIEW
NC PLL_PS
PLL
LOCK
GND
MRE
GND D
-
TEST_L
SCLK
FSEL0 TXCSEL AGND1 TEST_L
NC
PLL_LE RXC TEST_L
MWE
TEST_L
TEST_L
BBWSEL
RESET
_OUT
SCLK
SEL
GND TMS TCK
RX_
POW
TXD
PLL_
POW
MCS0 MCS1
VDD GND
TEST_L
VTM
TEST_L
AVDD1
GND
TRST
PLL_
OFF
PLL_
DATA
TX_
POW
TEST_H
RESET
D+
TEST_L TEST_L SCLK
FSEL1
REMAP0
XCLK VDD SCLK
PLL_
CLK
GND
RSSI_
CLK
LVDD
REGVBG AGND0 REGVDD AVDD0
RXD TXC_IN GND RSSI
GND REMAP1REGOUT
REG
GND
VDD
PCM
OUT
PCMCLK PCMIN
MBS0 MOE1
GND
MOE0
CIO15 TDO
PCM
SYNC
TDI
MBS1
VDD
MD0
GND
CIO12 GND CIO11 CIO14
MD1
MD4
VDD
MD2
CIO9 CIO13 CIO10
CIO7 MA15 MA11
VDD
MA6
MA3 MD13 MD7
MD3 MD5
CIO6 CIO8 CIO2 CIO0 MA17 GND MA9
MA7
MA0
VDD MD9
MD6 MD8
CIO4 CIO5 MA19 MA16 MA14 MA12 MA10
GND
MA5 MA2 MD14
MD11
MD10
NC CIO3 CIO1 MA18 GND MA13 MA8
MA4
MA1 MD15 MD12
GND
NC
1 2 3 4 5 6 7 8 9 10 11 12 13
A
B
C
D
E
F
G
H
J
K
L
M
N
TEST
PU
FEDL70Q5110LA-01
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ML70Q5110LA
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PIN DESCRIPTIONS
RF I/F
Pin Name
Direction
[*0]
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
TXD O -- L C2
Transmit data output
(To ML7050LA Pin# A8)
RXD I -- --
F1
Receive data input
(To ML7050LA Pin# H5)
PLL_DATA O
--
L D2
PLL setting data output
(To ML7050LA Pin# H3)
PLL_CLK O
--
L E1
PLL setting clock output
(To ML7050LA Pin# G3)
PLL_LE O
-- L B1
PLL setting load enable output
(To ML7050LA Pin# H4)
PLL_OFF O
--
L D1
PLL Open-loop/Closed-loop control signal
output (To ML7050LA Pin# G8)
PLL_POW O
--
H C3
Local transmit circuit power control signal
output (To ML7050LA Pin# A7)
TX_POW O
--
H D3
Transmit power control signal output
(To ML7050LA Pin# B6)
RX_POW O
--
H C1
Receive power control signal output
(To ML7050LA Pin# B3)
RSSI I
Pull
down
--
F4
Receive field strength data input
RSSI_CLK
O
--
H
E3
RSSI transfer clock
PLL_PS
O
--
L
A2
PLL power control signal output
PLLLOCK
I
Pull down
--
A3
PLL lock signal input
RXC
O
--
L
B2
Bluetooth receive clock output (1 MHz)
TXC_IN I Pull
down
-- F2
Bluetooth transmit clock input (1 MHz)
When the transmit clock is used by a clock
(RXC) that is generated from the receive data,
set TXCSEL(Pin# A10) to H and connect to
RXC(Pin# B2).
TXCSEL I Pull
down
-- A10
Bluetooth transmit clock setting pin
L: Select 1 MHz divided by internal PLL.
H: Select TXC_IN input signal.
[*0] "I" = Input, "O" = Output, "I/O" = Input/Output, "Oc" = Open Collector
FEDL70Q5110LA-01
OKI Semiconductor
ML70Q5110LA
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CLK and Configuration
Pin Name
Direction
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
SCLK I
-- -- D13
Master clock (12, 13 or 16 MHz) input pin
(Power level: CMOS level)
XCLK
I
--
--
D11
User clock input pin
SCLKSEL I Pull
down -- B10
System clock select pin
L: Select CLK divided by internal PLL
H: Select XCLK input signal
SCLKFSEL0 I Pull
down --
A9
SCLKFSEL1 I Pull
down -- D9
Master clock select pin
SCLKFSEL[1:0] = "00" : 12 MHz
"01" : 13 MHz
"10" : 16 MHz
"11" : Forbidden
RESET
I
--
--
D5
Hardware reset pin (Reset = L)
RESET_OUT
O
--
--
B9
Hardware reset pin (Reset = L), Output
BBWSEL I Pull
down
-- B8
BANK0 region bit width select pin
L: 8-bit
H: 16-bit
REMAP0 I
-- -- D10
REMAP1 I
-- -- F11
REMAP select pin during boot up
REMAP[1:0] = "00" Forbidden
"01" Stacked Flash ROM
"10"
External
MCS1
device
"11"
External
MCS0
device
Memory I/F
Pin Name
Direction
Internal
Pull Up/Down
Initial
Value
Pin
Placement
Description
MA[19:0]
O
--
L
[*1]
External address bus
MD[15:0]
I/O
Pull up
--
[*2]
External data bus
MWE
O
--
H
B4
External write enable signal output
MRE
O
--
H
A5
External read enable signal output
MCS0
O
--
H
C4
External space 0 chip select
MCS1
O
--
H
C5
External space 1 chip select
MBS0
O
--
H
G10
External lower byte select
MBS1
O
--
H
H10
External upper byte select
MOE0
O -- H
G13
External
MCS0
device output enable
(
MCS0
and
MRE
OR output)
MOE1
O -- H
G11
External
MCS1
device output enable
(
MCS1
and
MRE
OR output)
[*1] MA19: M3; MA18: N4; MA17: L5; MA16: M4; MA15: K5; MA14: M5
MA13: N6; MA12: M6; MA11: K6; MA10: M7; MA9: L7;
MA8: N7;
MA7: L8
MA6: K8;
MA5: M9; MA4: N8;
MA3: K9;
MA2: M10; MA1: N9;
MA0: L9
[*2] MD15: N10; MD14: M11; MD13: K10; MD12: N11; MD11: M12; MD10: M13
MD9: L11; MD8: L13; MD7: K11; MD6: L12; MD5: K13; MD4: J11; MD3: K12;
MD2: J13; MD1: J10; MD0: H12
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