OKI Semiconductor
PEDL87V2103DIGEST-01
Issue Date: Jan. 20, 2003
ML87V2103
Preliminary
Video Signal Noise Reduction and Rate Conversion IC with a Built-in 3.9 Mbit Field Memory
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GENERAL DESCRIPTION
The ML87V2103 comprises a 3.9 Mbit field memory and logic circuits for signal processing and memory control.
The device can reduce field-recursive noise and double the conversion speed.
There is an automatic noise reduction mode that detects the noise level in the input video data to set the optimum
noise reduction.
There are two ways to double the conversion speed: progressive conversion that doubles the number of lines by
doubling the horizontal direction frequency and flicker-free conversion that doubles both the vertical and
horizontal direction frequencies.
FEATURES
Built-in memory:
3.9 Mbit filed memory
1 unit
Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656):
14.75/29.5
MHz
Maximum output operating frequency:
29.5 MHz (double-speed conversion)
Power supply voltage :
3.3 V 0.3 V
Input pin:
TTL-5V tolerant (5 V withstand voltage)
Input/output pins:
Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage)
Output pin:
LVCMOS (3.3 V)
Input data format:
YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2)
YCbCr (8 bits (YCbCr)) (4:2:2)
ITU-R BT.656 (8 bits (YCbCr))
Output data format:
YCbCr (8 bits (Y) + 8 bits (CbCr)) (4:2:2)
Serial bus:
I
2
C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps)
Internal memory controller:
Input:
Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1
Output: Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1,
625/50 Hz 1:1, 525/60 Hz 1:1,
625/100 Hz 2:1, 525/120 Hz 2:1
Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768
Sync generator (for output):
Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1,
625/50 Hz 1:1, 525/60 Hz 1:1,
625/100 Hz 2:1, 525/120 Hz 2:1.
Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768
Field-recursive noise reduction:
Noise detection and subtraction (with horizontal motion compensation)
Automatic noise reduction mode
PEDL87V2103DIGEST-01
OKI Semiconductor
ML87V2103
5/14
PIN DESCRIPTIONS
No.
Symbol
I/O
Pad Remarks
Pin Description
1 V
DD
--
IO&CORE
Power supply 3.3 V
2 N.C. --
Unused
pin
3 N.C. --
Unused
pin
4 V
SS
-- IO&CORE
Ground
5 SDA I/O
Schmitt(IN)/
OpenDrain(OUT)
I
2
C-bus data pin
6 SCL I Schmitt I
2
C-bus clock pin
7
SLA1
I
pull-down 50k
Slave address setting pin
8
SLA2
I
pull-down 50k
Slave address setting pin
9
YI7
I
Luminance signal input pin bit 7 (MSB)
10
YI6
I
Luminance signal input pin bit 6
11
YI5
I
Luminance signal input pin bit 5
12
YI4
I
Luminance signal input pin bit 4
13
YI3
I
Luminance signal input pin bit 3
14
YI2
I
Luminance signal input pin bit 2
15
YI1
I
Luminance signal input pin bit 1
16
YI0
I
Luminance signal input pin bit 0 (LSB)
17 V
DD
--
IO&CORE
Power supply 3.3 V
18
ICLK
I
Input system clock pin
19 V
SS
-- IO&CORE
Ground
20
CI7
I
pull-down 50k
Color difference signal input pin bit 7 (MSB)
21
CI6
I
pull-down 50k
Color difference signal input pin bit 6
22
CI5
I
pull-down 50k
Color difference signal input pin bit 5
23
CI4
I
pull-down 50k
Color difference signal input pin bit 4
24
CI3
I
pull-down 50k
Color difference signal input pin bit 3
25
CI2
I
pull-down 50k
Color difference signal input pin bit 2
26
CI1
I
pull-down 50k
Color difference signal input pin bit 1
27
CI0
I
pull-down 50k
Color difference signal input pin bit 0 (LSB)
28 N.C. --
Unused
pin
29 N.C. --
Unused
pin
30 V
DD
--
IO&CORE
Power supply 3.3 V
31 V
SS
-- IO&CORE
Ground
32 IVS I
Schmitt
pull-down 50k
Input system vertical sync signal input pin
33 IHS I
Schmitt
pull-down 50k
Input system horizontal sync signal input pin
34
MODE0
I
pull-down 50k
Mode setting pin bit 0
35
MODE1
I
pull-down 50k
Mode setting pin bit 1
36
MODE2
I
pull-down 50k
Mode setting pin bit 2
37
MODE3
I
pull-down 50k
Mode setting pin bit 3
38
CLKO
O
Clock output (I
2
C-bus control possible)
39 V
DD
--
IO&CORE
Power supply 3.3 V
40 V
SS
-- IO&CORE
Ground
41 N.C. --
Unused
pin
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