OKI Semiconductor
PEDL87V2105DIGEST-02
Issue Date: Dec. 20, 2003
ML87V2105
Preliminary
Video Signal Noise Reduction IC with a Built-in 5.6 Mbit Frame Memory
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or
representative.
GENERAL DESCRIPTION
The ML87V2105 comprises a 5.6 Mbit frame memory, a noise reduction filter, and a memory controller to reduce
frame-recursive 3D noise in video signals.
The motion adaptive noise reduction is performed between frames, between fields, or between lines, to reduce the
afterimage particular to 3D noise reduction as far as possible, while achieving effective noise reduction.
The ML87V2105 also features an automatic noise reduction mode that automatically detects the noise level in the
input video data to set the optimum noise reduction.
Because it is possible to select the same format for output as for input, the ML87V2105 can be introduced into an
existing system, making it easy to achieve noise reduction.
FEATURES
Built-in memory:
Frame memory (4:1:1 data equivalent)
1 unit
Maximum input and output operating frequencies (16 bits/8 bits, ITU-R BT.656):
14.75/29.5
MHz
Power supply voltage:
3.3 V 0.3 V
Input pin:
LVTTL
(3.3
V)
Output pin:
LVCMOS (3.3 V)
Input data format:
YCbCr (8 bits (Y) + 8 bits (CbCr) (4:2:2) + Sync.):
16-bit mode
YCbCr (8 bits (YCbCr) (4:2:2) + Sync.):
8-bit mode
ITU-R BT.656 (8 bits (YCbCr)):
ITU-R BT.656 mode
Output data format:
YCbCr (8 bits (Y) + 8 bits (CbCr) (4:2:2) + Sync.):
16-bit mode
YCbCr (8 bits (YCbCr) (4:2:2) + Sync.):
8-bit mode (Selectable in 8-bit input mode)
ITU-R BT.656 (8 bits (YCbCr)):
ITU-R BT.656 mode (Selectable in input ITU-R
BT.656)
Serial bus:
I
2
C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps)
Internal memory controller:
Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1
Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768
Frame-recursive noise reduction:
Frame-recursive noise detection and subtraction
Auto mode noise reduction
Package:
100 pin TQFP (TQFP100-P-1414-0.50-K)(ML87V2105TB)
1/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
BLOCK DIAGRAM
Frame Memory
5.6Mbits
Memory
Controller
I
2
C-bus
I/F
Register
OHS
ICLK
IVS
OVS
SCL
SDA
SLA1
SLA2
Control
Signal
YO0-7
IHS
RESET
x16
HREF
MODE0-2
TEST1-7
CO0-7
YI0-7
CI0-7
x16
Input/Output
Process
Block
+
3D NR
CLKO
2/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
PIN CONFIGURATION (TOP VIEW)
TEST1
TEST2
TEST3
TEST4
TEST5
96
95
94
93
92
91
89
88
87
86
85
84
83
82
81
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
90
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
ML87V2105TB
(TQFP100-P-1414-0.50-K)
V
SS
V
DD
V
DD
CO
7
CO
6
CO
5
CO
4
N.
C.
V
SS
YO
4
YO
3
YO
2
YO
1
YO
0
YO
6
YO
5
YO
7
N.C.
CI
3
CI
2
IC
L
K
V
SS
OVS
OHS
V
DD
N.C.
V
SS
HREF
N.C.
IHS
IVS
CO
3
CO
2
CO
1
CO
0
N.C.
CI
7
CI
6
CI
5
CI
4
YI
3
YI
2
YI
1
YI
0
YI
7
YI
6
YI
5
YI
4
V
DD
V
SS
N.C.
N.C.
MODE1
SLA1
SLA2
MODE0
N.C.
MODE2
V
DD
V
SS
SDA
SCL
25
47
48
49
50
75
100
99
98
97
V
SS
N.
C.
V
SS
V
DD
CLKO
V
SS
V
SS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SELF
TESTM
N.C.
TEST6
TEST7
V
DD
CI
1
CI
0
N.C.
V
DD
29
28
27
26
30
V
DD
RESET
76
77
78
79
80
N.C.
N.C.
N.C.
N.C.
V
DD
3/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
PIN DESCRIPTIONS
No. Symbol I/O Pad
Remarks Pin
Description
1 N.C. --
Unused
pin
2 V
SS
--
Ground
3 SDA I/O
Schmitt(IN)/
OpenDrain(OUT)
I
2
C-bus data pin
4 SCL I
Schmitt I
2
C-bus clock pin
5
SLA1
I
Internal pull-down 50k Slave address setting pin
6
SLA2
I
Internal pull-down 50k Slave address setting pin
7
YI7
I
Luminance signal input pin bit 7 (MSB)
8
YI6
I
Luminance signal input pin bit 6
9
YI5
I
Luminance signal input pin bit 5
10
YI4
I
Luminance signal input pin bit 4
11
YI3
I
Luminance signal input pin bit 3
12
YI2
I
Luminance signal input pin bit 2
13
YI1
I
Luminance signal input pin bit 1
14
YI0
I
Luminance signal input pin bit 0 (LSB)
15 V
DD
--
Power supply 3.3 V
16
ICLK
I
Input system clock pin
17 V
SS
--
Ground
18
CI7
I
Internal pull-down 50k Color difference signal input pin bit 7 (MSB)
19
CI6
I
Internal pull-down 50k Color difference signal input pin bit 6
20
CI5
I
Internal pull-down 50k Color difference signal input pin bit 5
21
CI4
I
Internal pull-down 50k Color difference signal input pin bit 4
22
CI3
I
Internal pull-down 50k Color difference signal input pin bit 3
23
CI2
I
Internal pull-down 50k Color difference signal input pin bit 2
24
CI1
I
Internal pull-down 50k Color difference signal input pin bit 1
25
CI0
I
Internal pull-down 50k Color difference signal input pin bit 0 (LSB)
26 V
DD
--
Power supply 3.3 V
27 N.C. --
Unused
pin
28 V
SS
--
Ground
29 IVS I
Schmitt
Internal pull-down 50k
Input system vertical sync signal input pin
30 IHS I
Schmitt
Internal pull-down 50k
Input system horizontal sync signal input pin
31
MODE0
I
Internal pull-down 50k Mode setting pin bit 0
32
MODE1
I
Internal pull-down 50k Mode setting pin bit 1
33 N.C. --
Unused
pin
34
MODE2
I
Internal pull-down 50k Mode setting pin bit 2
35
CLKO
O/(I)
Clock output (I
2
C-bus control possible)
36 V
DD
--
Power supply 3.3 V
37 V
SS
--
Ground
38 N.C. --
Unused
pin
39 N.C. --
Unused
pin
4/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
No. Symbol I/O Pad
Remarks Pin
Description
40 V
DD
--
Power supply 3.3 V
41 N.C. --
Unused
pin
42 N.C. --
Unused
pin
43 N.C. --
Unused
pin
44 N.C. --
Unused
pin
45
OHS
O
Horizontal sync signal output pin
46
OVS
O
Vertical sync signal output pin
47
HREF
O
Data output horizontal reference signal output pin
48 V
SS
--
Ground
49 N.C. --
Unused
pin
50 V
DD
--
Power supply 3.3 V
51
CO0
O/(I)
Color difference signal output pin bit 0 (LSB)
52
CO1
O/(I)
Color difference signal output pin bit 1
53
CO2
O/(I)
Color difference signal output pin bit 2
54
CO3
O/(I)
Color difference signal output pin bit 3
55 V
SS
--
Ground
56
CO4
O/(I)
Color difference signal output pin bit 4
57
CO5
O/(I)
Color difference signal output pin bit 5
58
CO6
O/(I)
Color difference signal output pin bit 6
59
CO7
O/(I)
Color difference signal output pin bit 7(MSB)
60 V
DD
--
Power supply 3.3 V
61 N.C. --
Unused
pin
62 V
SS
--
Ground
63
YO0
O
Luminance signal output pin bit 0 (LSB)
64
YO1
O
Luminance signal output pin bit 1
65
YO2
O
Luminance signal output pin bit 2
66
YO3
O
Luminance signal output pin bit 3
67 V
DD
--
Power supply 3.3 V
68
YO4
O
Luminance signal output pin bit 4
69
YO5
O
Luminance signal output pin bit 5
70
YO6
O
Luminance signal output pin bit 6
71
YO7
O
Luminance signal output pin bit 7 (MSB)
72 V
SS
--
Ground
73
TEST7
I
Test input pin bit 7 (1: test mode)
74
TEST6
I
Test input pin bit 6 (1: test mode)
75
RESET
I Schmitt
System reset/input pin
0: System reset
1: Operation
5/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
No. Symbol I/O Pad
Remarks Pin
Description
76 V
DD
--
Power supply 3.3 V
77 N.C. --
Unused
pin
78 V
SS
--
Ground
79 N.C. --
Unused
pin
80 N.C. --
Unused
pin
81 N.C. --
Unused
pin
82 N.C. --
Unused
pin
83 N.C. --
Unused
pin
84 N.C. --
Unused
pin
85 N.C. --
Unused
pin
86 N.C. --
Unused
pin
87
TEST5
I
Internal pull-down 50k Test input pin bit 5 (1: test mode)
88 V
DD
--
Power supply 3.3 V
89
TEST4
I
Internal pull-down 50k Test input pin bit 4 (1: test mode)
90
TEST3
I
Internal pull-down 50k Test input pin bit 3 (1: test mode)
91
TEST2
I
Internal pull-down 50k Test input pin bit 2 (1: test mode)
92
TEST1
I
Internal pull-down 50k Test input pin bit 1 (1: test mode)
93 N.C. --
Unused
pin
94 N.C. --
Unused
pin
95 N.C. --
Unused
pin
96
TESTM
I
Internal pull-down 50k Memory test input pin (1: test mode)
97 SELF I
Internal
pull-down
50k
Self refresh setting pin (0: Self refresh stopped, 1: Self refresh
operated)
98 V
SS
--
Ground
Notes: Keep the test mode pins fixed to 0 or leave them open.
CL0 to CL7 and CLK0 are configured as inputs only in the test mode.
6/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Symbol
Condition Rating Unit
Power supply voltage
V
DD
Ta = 25C
0.3 to + 4.6
V
Input pin voltage
V
I
Ta = 25C
0.3 to + 7.0
V
Output pin short-circuit current
I
OS
Ta
=
25C
50
mA
Power dissipation
P
D
Ta
=
25C
1
W
Operating temperature
T
opr
--
0 to 70
C
Storage temperature
T
stg
--
50 to + 150
C
Recommended Operating Conditions
Parameter Symbol
Min.
Typ.
Max.
Unit
Power supply voltage
V
DD
3.0 3.3 3.6
V
Power supply voltage
V
SS
0 0
0
V
Operating temperature
Ta
0
--
70
C
Pin Capacitance
(V
CC
= 3.3 V 0.3 V, f = 1 MHz, Ta = 25C)
Parameter Symbol
Min.
Max. Unit
Input capacitance
C
i
--
5 pF
Input/output capacitance
(CO0 to CO7, CLK0)
C
io1
--
10 pF
Input/output capacitance (SDA)
C
io2
--
10 pF
Output capacitance
(YO0 to YO7, OVS, OHS, HREF)
C
o
--
10 pF
7/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
DC Characteristics
(Ta = 0 to 70C)
Parameter Symbol
Condition Min.
Max.
Unit
H level input voltage
V
IH
-- 2.0
V
DD
+0.3 V
L level input voltage
V
IL
--
0.3
0.8
V
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS,
RESET
)
V
t+
-- --
2.0
V
Schmitt trigger threshold voltage
(SDA, SCL, IVS, IHS,
RESET
)
V
t
-- 0.8
--
V
Hysteresis voltage width
V
h
--
0.1
--
V
H level input current (pull-down)
I
IH
50
k
Pull Down
20
200
A
Input leakage current
I
IL
TTL
10
10
A
H level output voltage (other than SDA)
V
OH
I
OH
= 4 mA
2.4
V
DD
V
L level output voltage (other than SDA)
V
OL
I
OL
= 4 mA
0
0.4
V
L level output voltage (N-Ch.OD)
(SDA)
V
OOL
I
OL
= 4 mA
0
0.4
V
Output leakage current
I
OL
0
V
out
V
DD
Output disabled
10 10
A
Supply current (during operation)
I
DD1
ICLK: 29.5 MHz
Output disabled
-- 80 mA
Supply current (during standby)
I
DD2
Input pin = V
IL
--
5
mA
AC Characteristics
(Ta = 0 to 70C)
Parameter Symbol
Condition Min.
Max.
Unit
ICLK clock cycle time
t
ICLK
16-bit input mode
66
--
ns
ICLK clock cycle time
t
ICLK
8-bit input mode
ITU-R BT.656 mode
33 -- ns
ICLK clock duty ratio
dt
ICLK
-- 40
60
%
ICLK input set-up time
t
IISU
-- 5
--
ns
ICLK input hold time
t
IIH
-- 3
--
ns
ICLK output delay time
t
IOD
C
L
= 30 pF
5
25
ns
C
L
= 30 pF (IICLK output)
2
25
ns
CLKO delay time
t
CKD
C
L
= 30 pF (ICLK output)
2
25
ns
Data through time
t
DIDO
C
L
= 30 pF
5
20
ns
*1: ( ) indicates the input internal system clock cycle.
Note 1: Measurement conditions
Output comparison level: V
OH
= 1.5 V, V
OL
= 1.5 V
Input voltage level: V
IH
= 3.0 V, V
IL
= 0.0 V
Note 2: .When writing input data to the memory, compensation is applied from the second input system
vertical synchronization signal when V
DD
reaches 3.0 V after the power is turned on, and when
RESET
= 1. (Due to memory initialization, the first data for the first field is not compensated.)
Note 3: .When reading output data from the memory, compensation is applied from the second output
system vertical synchronization signal when V
DD
reaches 3.0 V after the power is turned on, and
when
RESET
= 1. (Due to memory initialization, the first data for the first field is not compensated.)
8/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
INPUT/OUTPUT TIMING
1. ICLK input/output timing
t
ICLK
t
IIH
t
IISU
t
IOD
ICLK
DATA &
CONTROL
INPUT(ICLK)
DATA &
CONTROL
OUTPUT(ICLK)
50%
50%
50%
t
CKD
CLKO
(CKINV=0)
50%
50%
t
CKD
CLKO
(CKINV=1)
2. Data through mode input/output timing
t
DIDO
DATA &
CONTROL
INPUT
DATA &
CONTROL
OUTPUT
50%
50%
9/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
CIRCUIT APPLICATION EXAMPLES
Application Example 1
Mode setting: Open
Slave address: 1011100
Input format: 16-bit YCbCr (Register setting: DISEL = 0, R656 = 0)
NR-FIFO
ML87V2105
SCAN
CONVERTER
(ML87V230X)
or
MPEG
ENCODER
DIGITAL
VIDEO
DECODER
(ML86V766X)
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
CO7
CO6
CO5
CO4
CO3
CO2
CO1
CO0
OVS
OHS
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
ICLK
I
2
C-bus
MATER
CONTROLLER
SD
A
SC
L
VD
D
GN
D
VIDEO
IN
3.3V
HREF
CLKO
2,17,28
,
3
7
,
4
8
,
55
,
6
2
,
7
2
,
7
8,98
13
14
11
12
9
10
7
8
3
4
15
,
2
6
,
36
,
4
0,
5
0
,
6
0
,67,76,88,100
29
30
24
25
16
22
23
20
21
18
19
71
70
47
46
52
51
54
53
57
56
59
58
64
63
66
65
69
68
45
35
75
System
Reset
CLK
R
ESE
T
DATA
OUT
RE
S
E
T
IVS
IHS
97
SE
L
F
10/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
Application Example 2
Mode setting: Open
Slave address: 1011100
Input format: ITU-R BT656 (Register setting: DISEL = 0, R656 = 1)
SCAN
CONVERTER
(ML87V230X)
or
MPEG
ENCODER
DIGITAL
VIDEO
DECODER
(ML86V7666)
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
CO7(OPEN)
CO6(OPEN)
CO5(OPEN)
CO4(OPEN)
CO3(OPEN)
CO2(OPEN)
CO1(OPEN)
CO0(OPEN)
OVS(OPEN)
OHS(OPEN)
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
CI7(OPEN)
CI6(OPEN)
CI5(OPEN)
CI4(OPEN)
CI3(OPEN)
CI2(OPEN)
CI1(OPEN)
CI0(OPEN)
ICLK(27MHz)
I
2
C-bus
MATER
CONTROLLER
SD
A
SC
L
VD
D
GN
D
VIDEO
IN
3.3V
HREF(OPEN)
CLKO(OPEN)
System
Reset
CLK
RE
S
E
T
DATA
OUT
IVS(OPEN)
IHS(OPEN)
NR-FIFO
ML87V2105
2,
1
7
,
2
8,
37
,
4
8
,
5
5
,
6
2,
7
2
,78,98
13
14
11
12
9
10
7
8
3
4
15
,
2
6
,
36
,
4
0,
5
0
,
6
0
,67,76,88,100
29
30
24
25
16
22
23
20
21
18
19
71
70
47
46
52
51
54
53
57
56
59
58
64
63
66
65
69
68
45
35
75
RE
S
E
T
97
SE
L
F
11/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Epoxy resin
Lead frame material
42 alloy
Pin treatment
Solder plating (
5m)
Package weight (g)
0.55 TYP.
5
Rev. No./Last Revised
4/Oct. 28, 1996
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
12/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
REVISION HISTORY
Page
Document
No.
Date
Previous
Edition
Current
Edition
Description
PEDL87V2105DIGEST-01
Oct.20,2003
14
Preliminary edition 1
PEDL87V2105DIGEST-02
Dec.20,2003
14
14
Internal pull down, application schematic
13/14
PEDL87V2105DIGEST-02
OKI Semiconductor
ML87V2105
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation
for the standard action and performance of the product. When planning to use the product, please ensure that the
external conditions are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting
from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical
or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.
5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by
us in connection with the use of the product and/or the information and drawings contained herein. No
responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics,
etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application
that requires special or enhanced quality and reliability characteristics nor in any system or application where the
failure of such system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products and
will take appropriate and necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2003 Oki Electric Industry Co., Ltd.
14/14
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