¡ Semiconductor

ML9044

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¡ Semiconductor

ML9044

DOT MATRIX LCD CONTROLLER DRIVER

E2B0055-19-61

This version: Jun. 1999

Preliminary

GENERAL DESCRIPTION

The ML9044 used in combination with an 8bit or 4bit microcontroller controls the operation
of a character type dot matrix LCD.

FEATURES

· Easy interfacing with 8bit or 4bit microcontroller
· Switchable between serial and parallel interfaces
· Dotmatrix LCD controller/driver for a small (5 ¥ 7 dots) or large (5 ¥ 10 dots) font
· Builtin circuit allowing automatic resetting at poweron
· Builtin 17 common signal drivers and 120 segment signal drivers
· Builtin character generation ROM capable of generating 160 small characters (5 ¥ 7 dots) or

32 large characters (5 ¥ 10 dots)

· Creation of character patterns by programming: up to 8 small character patterns (5 ¥ 8 dots) or

up to 4 large character patterns (5 ¥ 11 dots)

· Builtin RC oscillation circuit using external or internal resistors
· Programselectable duties: 1/9 duty (1 line: 5 ¥ 7 dots + cursor + arbitrator), 1/12 duty (1 line:

5 ¥ 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 ¥ 7 dots + cursor + arbitrator)

· Builtin bias dividing resistors to drive the LCD
· Bidirectional transfer of segment outputs
· Bidirectional transfer of common outputs
· Equipped with a 120dot arbitrator
· Display shifting on each line
· Builtin contrast control circuit
· Builtin voltage multiplier circuit
· Chip (Gold Bump) Product name : ML9044CVWA

¡ Semiconductor

ML9044

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BLOCK DIAGRAM

GND

OSC

RS1
RS0

R/W

P/S

SHT

to DB

5IN

Timing

generator

I/O

buffer

Instruction

(IR)

Instruction

decoder

(ID)

Data

(DR)

COM

SEG

COM

Test

circuit

LCD

bias

voltage

dividing

circuit

Busy flag

(BF)

Expansion

Instruction

Voltage

multiplier

circuit

Address

counter

(ADC)

Expansion

Instruction

decoder (ED)

Character

generator

ROM

(CGROM)

Display

data RAM

(DDRAM)

Arbitrator

RAM

(ABRAM)

Character

generator

RAM

(CGRAM)

Cursor

blink

controller

CSR

17-bit

shift

Common

signal

driver

Rarallel-

serial

converter

120-bit shift register

120-bit latch

Segment Signa - driver

SEG

120

SSR

BEB

¡ Semiconductor

ML9044

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PIN DESCRIPTIONS

Symbol

Description

R/W

The input pin with a pullup resistor to select Read ("H") or Write ("L") in the Parallel

I/F Mode.

This pin should be open in the Serial I/F Mode.

, RS

Name of register

Data register

Instruction register

Expansion Instruction register

The input pins with a pullup resistor to select a register in the Parallel I/F Mode.

This pin should be open in the Serial I/F Mode.

The input pin for data input/output between the CPU and the ML9044 and for activating

instructions in the Parallel I/F Mode.

This pin should be open in the Serial I/F Mode.

to DB

The input/output pins to transfer data of lowerorder 4 bits between the CPU and the

ML9044 in the Parallel I/F Mode. Each pin is equipped with a pullup resistor. These 4

lines are not used for the 4bit interface.

This pin should be open in the Serial I/F Mode.

to DB

The input/output pins to transfer data of upper 4 bits between the CPU and the ML9044

in the Parallel I/F Mode. Each pin is equipped with a pullup resistor.

This pin should be open in the Serial I/F Mode.

OSC

The clock oscillation pins required for LCD drive signals and the operation of the

ML9044 by instructions sent from the CPU.

To input external clock, the OSC

pin should be used. The OSC

and the OSC

pins

should be open.

To start oscillation with an external resistor, the resistor should be connected between

the OSC

and OSC

pins. The OSC

pin should be open.

To start oscillation with an internal resistor, the OSC

and OSC

pins should be

shortcircuited outside the ML9044. The OSC

pin should be open.

COM

to COM

The LCD common signal output pins.

For 1/9 duty, nonselectable voltage waveforms are output via COM

to COM

. For

1/12 duty, nonselectable voltage waveforms are output via COM

to COM

SEG

to SEG

120

The LCD segment signal output pins.

¡ Semiconductor

ML9044

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SSR

The input pin to select the transfer direction of the segment signal output data.

"L": Data transfer from SEG

to SEG

120

"H": Data transfer from SEG

120

to SEG

, V

The pins to output bias voltages to the LCD.

For 1/4 bias : The V

and V

pins are shorted.

For 1/5 bias : The V

and V

pins are shorted.

BEB

The input pin to enable or disable the voltage multiplier circuit.

"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.

The voltage multiplier circuit doubles the input voltage V

and outputs it to the V

5IN

pin.

The voltage multiplier circuit can be used only when generating a level lower than GND.

The pin to input voltage to the voltage multiplier.

, V

5IN

The pins to supply the LCD drive voltage.

The LCD drive voltage is supplied to the V

pin when the voltage multiplier is not used

(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the

5IN

pin should be open.

The LCD drive voltage is supplied to the V

5IN

pin when the voltage multiplier is not used

(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V

should be open.

When the voltage multiplier is used (BEB = 1), the V

5IN

and V

pins should be open (the

multiplied voltage is output to the V

5IN

pin). In this case, the internal contrast adjusting

circuit is used automatically.

The pin to connect the positive pin of the capacitor for the voltage multiplier.

The pin to connect the negative pin of the capacitor used for the voltage multiplier.

CSR

The input pin to select the transfer direction of the common signal output data.

Refer to the Expansion Instruction Codes section about the AS bit.

CSR

duty

AS bit

shift direction

arbitrator's common pin

1/9

COM1 Æ COM9

COM9

1/9

COM2 Æ COM9, COM1

COM1

1/12

COM1 Æ COM12

COM12

1/12

COM2 Æ COM12, COM1

COM1

1/17

COM1 Æ COM17

COM17

1/17

COM2 Æ COM17, COM1

COM1

1/9

COM9 Æ COM1

COM1

1/9

COM8 Æ COM1, COM9

COM9

1/12

COM12 Æ COM1

COM1

1/12

COM11 Æ COM1, COM12

COM12

1/17

COM17 Æ COM1

COM1

1/17

COM16 Æ COM1, COM17

COM17

Symbol

Description

¡ Semiconductor

ML9044

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P/S

The input pin to select the parallel or serial interface.

"L" selects the parallel interface.

"H" selects the serial interface.

The pin to enable this IC in the serial I/F mode.

"L" enables this IC.

"H" disables this IC.

This pin should be open in the parallel I/F mode.

SHT

The pin to input shift clock in the serial I/F mode.

Data inputting to the SI pin is carried out synchronizing with the rising edge of this

clock signal.

Data outputting from the SO pin is carried out synchronizing with the falling edge of this

clock signal.

This pin should be open in the parallel I/F mode.

The pin to input DATA in the serial I/F mode.

Data inputting to this pin is carried out synchronizing with the rising edge of the SHT

signal.

This pin should be open in the parallel I/F mode.

The pin to output DATA in the serial I/F mode.

Data inputting to this pin is carried out synchronizing with the falling edge of the SHT

signal.

This pin should be open in the parallel I/F mode.

Symbol

Description

, T

The input pins for test circuits (normally open). Equipped with a pulldown resistor.

The power supply pin.

GND

The ground level input pin.

¡ Semiconductor

ML9044

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ABSOLUTE MAXIMUM RATINGS

Note:

This voltage should be applied across V

and V

. The following voltages are output

to the V

, V

) and V

pins:

· 1/4 bias
V

= {V

)/4}

0.15V

= V

= {V

)/2}

0.15V

= {V

3 ¥ (V

)/4 }

0.15V

· 1/5 bias
V

= {V

)/5}

0.15V

= {V

2 ¥ (V

)/5}

0.15V

= V

= {V

3 ¥ (V

)/5}

0.15V

= {V

4 ¥ (V

)/5}

0.15V

The voltages at the V

, V

), V

and V

pins should satisfy

)>V

(Higher ¨

Æ Lower)

* Do not apply shortcircuiting across output pins and across an output pin and an
input/output pin or the power supply pin in the output mode.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Rating

Unit

Applicable pins

(GND = 0V)

Supply Voltage

Ta = 25°C

0.3 to +6.5

GND

LCD Driving Voltage

, V

Ta = 25°C

7.5 to V

+0.3

, V

5IN

, V

Input Voltage

Ta = 25°C

0.3 to V

+0.3

R/W, E, SHT, CSR,
P/S, SSR, SI, RS

, BEB, CS,

to T

, DB

to DB

Storage Temperature

STG

55 to +125

°C

Parameter

Symbol

Condition

Range

Unit Applicable pins

(GND = 0V)

Supply Voltage

2.5 to 5.5

GND

Input Voltage

BEB = 1

1.40 to

3.5

LCD Driving Voltage

(See Note)

2.8 to 7.0

5IN

)

Operating Temperature

40 to +85

°C

¡ Semiconductor

ML9044

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ELECTRICAL CHARACTERISTICS

DC Characteristics

(GND = 0V, V

= 2.5V to 5.5V, Ta = 40 to +85°C)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Applicable pin

"H" Input Voltage 1

IH1

0.8V

"L" Input Voltage 1

IL1

0.3

0.2V

"H" Input Voltage 2

IH2

0.8V

"L" Input Voltage 2

IL2

0.3

0.2V

"H" Output Voltage 1 V

OH1

= 0.1mA

0.75V

"L" Output Voltage 1

OL1

= +0.1mA

0.2V

"H" Output Voltage 2 V

OH2

= 13mA

0.9V

"L" Output Voltage 2

OL2

= +13mA

0.1V

COM Voltage

Drop

OCH

= 4mA

0.3

CMH

OCMH

= ±4mA

0.3

+ 0.3

CML

OCML

= ±4mA

0.3

+ 0.3

OCL

= +4mA

+ 0.3

SEG Voltage

Drop

OSH

= 4mA

0.3

SMH

OSMH

= ±4mA

0.3

+ 0.3

SML

OSML

= ±4mA

0.3

+ 0.3

OSL

= +4mA

= 5V

Note 1

+ 0.3

Input Leakage

Current

| IIL |

= 5V, V

= 5V or 0V

1.0

Input Current 1

| II1|

= 5V, V

= GND

= 5V, V

= V

Excluding current flowing

through the pull-up resistor

and the output driving MOS

2.0

Input Current 2

| II2|

= 5V, V

= V

105

= 5V, V

= V

Excluding current flowing

through the pull-down resistor

2.0

Supply Current

= 5V

Note 2

Rf = 120kW±2%

Note 3

OSC

: Open

OSC

and OSC

: Short-circuited

Note 4

OSC

, OSC

: Open

Input from OSC

1.2

LCD Bias Resistor

4.0

Oscillation Frequency of

External Resistor Rf

osc1

175

270

350

kHz

Oscillation Frequency of

Internal Resistor Rf

osc2

140

270

480

kHz

Clock Input

Frequency

Input Clock Rise Time

External Clock

125

480

kHz

Input Clock Duty

duty

Note 5

Note 6

0.2

Note 6

0.2

E, SSR, CSR, BEB,

SHT, P/S, CS, SI

R/W, RS

, RS

to DB

, SO

, T

GND

, V

OSC

, OSC

OSC

, OSC

OSC

R/W, RS

, RS

E, DB

to DB

SHT, P/S, SI, CS

OSC

SSR, CSR, BEB

to DB

, SO

OSC

COM

to COM

SEG

to SEG

120

Input Clock Fall Time

¡ Semiconductor

ML9044

9/54

Control Range of
LCD Driving
Voltage (by internal
variable resistor)

LCD

MAX

= 5V, 1/5 bias

5IN

= 0V

TBD

LCD

MIN

= 5V, 1/5 bias

5IN

= 0V

TBD

Bias Voltage for Driving

LCD by External Input

LCD1

2.8

7.0

LCD2

Note 7

1/5 bias

1/4 bias

2.8

7.0

Voltage Multiplier

Output Voltage

V5OUT V

= 3V, V

= 0V

BEB = H

+1.2V

Voltage Multipler

Input Voltage

, V

5IN

(GND = 0V, V

= 2.5V to 5.5V, Ta = 40 to +85°C)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

Applicable pin

¡ Semiconductor

ML9044

10/54

Note 1:

Applied to the voltage drop occurring between any of the V

, V

and V

pins and

any of the common pins (COM

to COM

) when the current of 4mA flows in or flows

out at one common pin.
Also applied to the voltage drop occurring between any of the V

, V

) and

pins and any of the segment pins (SEG

to SEG

120

) when the current of 4mA flows

in or flows out at one common pin.

The current of 4mA flows out when the output level is V

or flows in when the output

level is V

Note 2:

Applied to the current flowing into the V

pin when the external clock (f

osc2

= f

270 kHz) is fed to the internal R

oscillation or OSC

under the following conditions:

= 5V

GND = V

= 0V,

, V

) and V

: Open

E, SSR, CSR, and BEB: "L" (fixed)
Other input pins: "L" or "H" (fixed)
Other output pins: No load

OSC

The wire between OSC

and OSC

should be as short

as possible. Keep OSC

open.

OSC

The wire between OSC

and R

and the wire between

OSC

and R

should be as short as possible.

Keep OSC

open.

= 120kW±2%

waveform

Applied to the pulses entering from the OSC

duty

= t

/ (t

+ t

) ¥ 100 (%)

Note 3:

Note 4:

Note 5:

¡ Semiconductor

ML9044

12/54

Switching Characteristics (The following ratings are subject to change after ES evaluation.)

· Parallel Interface Mode
The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2)
are as shown below:

1) WRITE MODE (Timing for input from the CPU)

= 2.5 to 5.5V, Ta = 40 to +85°C)

Parameter

Symbol

Unit

Min

Typ

Max

R/W, RS

, RS

Setup time

E Pulse Width

450

R/W, RS

, RS

Hold time

E Rise Time

E Fall Time

E Pulse Width

430

E Cycle Time

1000

to DB

Input Data Hold time

195

to DB

Input Data Setup time

, RS

R/W

to DB

Input

Data

¡ Semiconductor

ML9044

13/54

2) READ MODE (Timing for output to the CPU)

= 2.5 to 5.5V, Ta = 40 to +85°C)

Parameter

Symbol

Unit

Min

Typ

Max

R/W, RS

, RS

Setup Time

E Pulse Width

450

R/W, RS

, RS

Hold Time

E Rise Time

E Fall Time

E Pulse Width

430

E Cycle Time

1000

to DB

Output Data Delay Time

350

to DB

Output Data Hold Time

RS1, 0

R/W

to DB

Output
Data

¡ Semiconductor

ML9044

14/54

· Serial Interface Mode

= 2.5 to 5.5V, Ta = 40 to +85°C)

Parameter

Symbol

Unit

Min

Typ

Max

SHT Cycle Time

500

SCY

CS Setup Time

100

CSU

CS Hold Time

100

SHT Setup Time

SSU

SHT Hold Time

200

SHT "H" Pulse Width

200

SWH

SHT "L" Pulse Width

200

SWL

SHT Rise Time

SHT Fall Time

SI Setup Time

100

DISU

SI Hold Time

100

DIH

Data Output Delay Time

160

DOD

Data Output Hold Time

CDH

SCY

DOD

CDH

SHT

CSU

SSU

SWL

SWH

DISU

DIH

¡ Semiconductor

ML9044

15/54

FUNCTIONAL DESCRIPTION

Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS

and RS

The DR is selected when both RS

and RS

are "H". The IR is selected when RS0 is "L" and RS

is "H". The ER is selected when both RS

and RS

are "L". (When RS

is "H" and RS

is "L", the

ML9044 is not selected.)
The IR stores an instruction code and the address code of the display data RAM (DDRAM) or the
character generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read
from the DDRAM, AMRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or
CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically
transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM
and CGRAM can be checked by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or
CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads
the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the
DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/
W(Read/Write) pin.

Table 1 R/W pin status and register operation

Busy Flag (BF)
The status "1" of the Busy Flag (BF) indicates that the ML9044 is carrying out internal operation.
When the BF is "1", any new instruction is ignored.
When R/W = "H", RS

= "L" and RS

= "H", the data in the BF is output to the DB

New instructions should be input when the BF is "0".
When the BF is "1", the output code of the address counter (ADC) is undefined.

R/W

Operation

Writing in the IR

Reading the Busy flag (BF) and the address counter (ADC)

Writing in the DR

Reading from the DR

Writing in the ER

Reading the contrast code

¡ Semiconductor

ML9044

16/54

Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and
also provides a cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to
the predefined register, the register selects the specified DDRAM, ABRAM or CGRAM and
transfers the address code to the ADC. The address data in the ADC is automatically incremented
(or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or
CGRAM.
The data in the ADC is output to DB

to DB

when R/W = "H", RS

= "L", RS

= "H" and BF =

"0".

Timing Generator
The timing generator generates timing signals for the internal operation of the ML9044 activated
by the instruction sent from the CPU or for the operation of the internal circuits of the ML9041
such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the
internal operation carried out for LCD displaying will not be interfered by the internal operation
initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM,
the display of the LCD not corresponding to the written data is not affected.

¡ Semiconductor

ML9044

17/54

Display Data RAM (DDRAM)
This RAM stores the display data represented in 8bit character coding (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below.
The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.

MSB

LSB

Hexadecimal

ADC

(Example) Representation of DDRAM address = 12

0 0 0 1 0 2 0 3 0 4

1 6 1 7

Digit

23 24

Left
end

Right

end

Display position

DD RAM address (hexadecimal)

4 F 0 0 0 1 0 2

1 5 1 6

Digit

23 24

(Display shifted to the right)

0 1 0 2 0 3 0 4

1 7 1 8

Digit

0 5

23 24

(Display shifted to the left)

1) Relationship between DDRAM addresses and display positions (1line display mode)

In the 1line display mode, the ML9044 can display up to 24 characters from digit 1 to digit 24.
While the DDRAM has addresses "00" to "4F" for up to 80 character codes, the area not used for
display can be used as a RAM area for general data. When the display is shifted by instruction,
the relationship between the LCD display and the DDRAM address changes as shown below:

¡ Semiconductor

ML9044

18/54

2) Relationship between DDRAM addresses and display positions (2line display mode)
In the 2line mode, the ML9044 can display up to 48 characters (24 characters per line) from digit
1 to digit 24.

0 0 0 1 0 2 0 3 0 4

Digit

1 6 1 7

23 24

4 0 4 1 4 2 4 3 4 4

5 6 5 7

Line 1

Line 2

Display position

DD RAM

address (hexadecimal)

2 7 0 0 0 1 0 2

1 5 1 6

23 24

6 7 4 0 4 1 4 2

5 5 5 6

Line 1

Line 2

0 1 0 2 0 3 0 4

1 7 1 8

23 24

4 1 4 2 4 3 4 4

0 3

4 3

0 5

4 5

5 7 5 8

Line 1

Line 2

(Display shifted to the right)

(Display shifted to the left)

Digit

Note:
The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at digit
1 in the second line.

When the display is shifted by instruction, the relationship between the LCD display and the
DDRAM address changes as shown below:

¡ Semiconductor

ML9044

20/54

Character Generator RAM (CGRAM)

The CGRAM is used to generate userspecific character patterns that are not in the CGROM.
CGRAM (64 bytes = 512 bits) can store up to 8 small character patterns (5 ¥ 8 dots) or up to 4 large
character patterns (5 ¥ 11 dots).
When displaying a character pattern stored in the CGRAM, write an 8bit character code (00 to
07 or 08 to 0F; hex.) assigned in Table 2 to the DDRAM. This enables outputting the character
pattern to the LCD display position corresponding to the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC.
Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM
or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM.

1) Small character patterns (5 ¥ 8 dots) (See Table 31.)

(1) A method of writing character patterns to the CGRAM from the CPU

The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB

to DB

The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3.1).
Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since
the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all "1", which means
7 in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bits 5 to 7 is not. Therefore, the CGRAM data bits 5 to 7 can be
used as a RAM area.

(2) A method of displaying CGRAM character patterns on the LCD

The CGRAM is selected when the higherorder 4 bits of a character code are all zeros. Since bit
3 of a character code is not used, the character pattern "0" in Table 31 can be selected using the
character code "00" or "08" in hexadecimal.
When the 8bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5,
respectively.)

¡ Semiconductor

ML9044

21/54

2) Large character patterns (5 ¥ 11 dots) (See Table 32.)

(1) A method of writing character patterns to the CGRAM from the CPU

The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB

to DB

The data lines DB

to DB

correspond to the CGRAM data bits 0 to 7, respectively (see Table 3

2). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status.
Since the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all "1", which means
A in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in
hexadecimal (set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data
given by the CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These
bits can be written and read as a RAM area.

(2) A method of displaying CGRAM character patterns on the LCD

The CGRAM is selected when the higherorder 4 bits of a character code are all zeros. Since bits
0 and 3 of a character code are not used, the character pattern "b" in Table 32 can be selected with
a character code "00", "01", "08" or "09" in hexadecimal.
When the 8bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5,
respectively.)

¡ Semiconductor

ML9044

22/54

Arbitrator RAM (ABRAM)
The arbitrator RAM(ABRAM) stores arbitrator display data.
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address
area is 00 to 23 (00H to 17H).
Although an address exceeding 23 (17H) can be set or the address already set may exceed it due
to automatic increment or decrement processing, any address out of the valid address area is
ignored.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC.
Therefore, the cursor or blink display should be inhibited while the ADC is hoding a CGRAM
or ABRAM address.

MSB

LSB

Hexadecimal

ADC

Don't Care

Display - ON data

5XSn+1

5XSn+5

Configuration of input display data

Input data

Relationship between display-ON

data and segment pins

Sn = ABRAM address (0 to 23)

The arbitrator RAM can store a maximum of 120 dots of the arbitrator DisplayON data in units
of 5 dots.
The arbitrator display is not shifted by any instructions and has the following relationship with
the LCD display positions:.

¡ Semiconductor

ML9044

23/54

Table 2 Relationship between character codes and character patterns of the ML9044

Lower
4 bits

Upper

4 bits

0000

LSB

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

MSB
0000

0010

0011

0100

0101

0110

0111

1010

1011

1100

1101

1110

1111

0001

RAM (1)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

(2)

(3)

(4)

(5)

(9)

(7)

(8)

(2)

(

)

;

[

]

{

}

¡ Semiconductor

ML9044

24/54

Table 31

Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ¥ 7 dot character mode. (Examples)

CG RAM

address

(Character pattern)

(Character code)

data

DD RAM

data

5 4 3 2 1 0

0 0 0 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 1 1 1 0

1 0 0 0 1

0 1 1 1 0

0 0 0 0 0

7 6 5 4 3 2 1 0

MSB

LSB

MSB

LSB

MSB

LSB

0 0 0 0 ¥ 0 0 0

¥ ¥ ¥

0 0 1 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 0 1 0 0

1 0 0 1 0

1 0 0 0 1

0 0 0 0 0

0 0 0 0 ¥ 0 0 1

¥ ¥ ¥

1 1 1 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 1 1 1 0

0 0 1 0 0

0 1 1 1 0

0 0 0 0 0

0 0 0 0 ¥ 1 1 1

¥ ¥ ¥

: Don't Care

¡ Semiconductor

ML9044

25/54

Table 32

Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ¥ 10 dot character mode (Examples)

CG RAM

address

(Character pattern)

(Character code)

data

DD RAM

data

5 4 3 2 1 0

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

LSB

0 0 0 0 ¥ 0 0 ¥

¥ ¥ ¥

0 0 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0 ¥ 0 0 ¥

¥ ¥ ¥

0 0 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0 0

0 1 1 1 1

1 0 0 0 1

0 1 1 1 1

0 0 0 0 1

0 1 1 1 0

0 0 0 0 0

¥ ¥ ¥ ¥ ¥

0 0 0 0 ¥ 1 1 ¥

¥ ¥ ¥

0 0 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0 0

1 1 0 1 1

0 1 0 1 0

1 0 0 0 1

0 1 1 1 0

0 0 0 0 0

¥ ¥ ¥ ¥ ¥

: Don't Care

0 1 0 0 0

0 1 1 1 1

1 0 0 1 0

0 1 1 1 1

0 1

1 1 1 1 1

0 0 0 1 0

0 0 0 0 0

¥ ¥ ¥ ¥ ¥

¡ Semiconductor

ML9044

26/54

Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set
in the ADC (Address Counter).
For example, when the ADC stores a value of "07" (hexadecimal), the cursor or blink is displayed
as follows:

Note:

The cursor or blink is also displayed even when a CGRAM or ABRAM address is set
in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC
is holding a CGRAM or ABRAM address.

DB6

DB0

0 0

0 0 0 1 0 2 0 3 0 4

0 7 0 8

Cursor/blink position

1 6 1 7

23 24

0 5 0 6

0 0 0 1 0 2 0 3 0 4

0 7 0 8

Cursor/blink position

1 6 1 7

23 24

0 5 0 6

4 0 4 1 4 2 4 3 4 4

4 7 4 8

5 6 5 7

4 5 4 6

First line

ADC

In 1-line display mode

In 2-line display mode

Second line

Digit

¡ Semiconductor

ML9044

27/54

LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR)

The ML9044 has 17 common signal outputs and 120 segment signal outputs to display 24
characters (in the 1line display mode) or 48 characters (in the 2line display mode).
The character pattern is converted into serial data and transferred in series through the shift
register.
The transfer direction of serial data is determined by the SSR pin. The shift direction of common
signals is determined by the CSR pin. The following tables show the transfer and shift directions:

* Refer to the Expansion Instruction Codes section about the AS bit.

Signals to be input to the SSR and CSR pins should be determined at poweron and be kept
unchanged.

CSR

duty

AS bit

Shift direction

arbitrator's common pin

1/9

COM1 Æ COM9

COM9

1/9

COM2 Æ COM9, COM1

COM1

1/12

COM1 Æ COM12

COM12

1/12

COM2 Æ COM12, COM1

COM1

1/17

COM1 Æ COM17

COM17

1/17

COM2 Æ COM17, COM1

COM1

1/9

COM9 Æ COM1

COM1

1/9

COM8 Æ COM1, COM9

COM9

1/12

COM12 Æ COM1

COM1

1/12

COM11 Æ COM1, COM12

COM12

1/17

COM17 Æ COM1

COM1

1/17

COM16 Æ COM1, COM17

COM17

SSR

Transfer direction

SEG

120

SEG

120

SEG

¡ Semiconductor

ML9044

28/54

Builtin Reset Circuit

The ML9044 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is "1" and the ML9041 does not accept any instruction
from the CPU (other than the Read BF instruction).
The Busy Flag is "1" for about 15 ms after the V

becomes 2.5 V or higher.

During this initialization, the ML9044 performs the following instructions:

Display clearing

CPU interface data length = 8 bits

(DL = "1")

1line LCD display

(N = "0")

Font size = 5 ¥ 7 dots

(F = "0")

ADC counting = Increment

(I/D = "1")

Display shifting = None

(S = "0")

Display = Off

(D = "0")

Cursor = Off

(C = "0")

Blinking = Off

(B = "0")

10) Arbitrator = Displayed in the lower line

(AS = "0")

11) Setting 1FH (hexadecimal) to the Contrast Data

To use the builtin reset circuit, the power supply conditions shown below should be satisfied.
Otherwise, the builtin reset circuit may not work properly. In such a case, initialize the ML9044
with the instructions from the CPU. The use of a battery always requires such initialization from
the CPU. (See "Initial Setting of Instructions")

Figure 1 Poweron and Poweroff Waveform

2.5V

0.2V

OFF

0.1ms£ t

100ms

1ms£ t

OFF

¡ Semiconductor

ML9044

29/54

I/F with CPU

Parallel interface mode
The ML9044 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any
8bit or 4bit microcontroller (CPU).

1) 8bit interface data length
The ML9044 uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the
CPU.

2) 4bit interface data length
The ML9044 uses only the higherorder 4 data bus lines DB

to DB

twice to transfer 8bit data

to and from the CPU.
The ML9044 first transfers the higherorder 4 bits of 8bit data (DB

to DB

in the case of 8bit

interface data length) and then the lowerorder 4 bits of the data (DB

to DB

in the case of 8bit

interface data length).
The lowerorder 4 bits of data should always be transferred even when only the transfer of the
higherorder 4 bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8bit data. Therefore, when only
one access is made, the following data transfer cannot be completed properly.

¡ Semiconductor

ML9044

30/54

Figure 2 8-Bit Data Transfer

Figure 3 4-Bit Data Transfer

R/W

Busy

(Internal operation)

Busy

ADC

Writing In IR

(Instruction

Reading BF (Busy Flag)

and ADC (Address Counter)

Writing In DR

(Data Register)

R/W

Busy

(Internal operation)

Busy

ADC

Writing In IR

(Instruction

Reading BF (Busy Flag)

and ADC (Address Counter)

Writing In DR

(Data Register)

¡ Semiconductor

ML9044

31/54

Serial Interface Mode

In the Serial I/F Mode, the ML9044 interfaces with the CPU via the CS, SHT, SI and SO pins.
Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If
the CS signal rises up before the completion of 16bit unit access, this access is ignored.
When the BF bit is "1", the ML9044 cannot accept any other instructions. Before inputting a new
instruction, check that the BF bit is "0". Any access when the BF bit is "1" is ignored.
Data format is LSBfirst.

Examples of Access in the Serial I/F Mode

1) WRITE MODE

SHT

R/W

SHT

R/W

2) READ MODE

¡ Semiconductor

ML9044

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Instruction Codes

Table of Instruction Codes

Display Clear

Cursor Home

Entry Mode Setting

Displya ON/OFF Control

Cursor/Display Shift

Function Setting

CGRAM Address Setting

DDRAM Address Setting

Busy Flag/Address Read

RAM Data Write

RAM Data Read

Contrast Control Data Write

Contrast Control Data Read

Instruction

Function

Execution

Time

f = 270kHz

Code

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

R/W

RS0

RS1

Clears all the displayed digits of the LCD and

sets the DDRAM address 0 in the address

counter. The arbitrator data is cleared.

Sets the DDRAM address 0 in the address

counter and shifts the display back to the

original. The content of the DDRAM

remains unchanged.
Determines the direction of movement of

the cursor and whether or not to shift the

display. This instruction is executed when

data is written or read.
Sets LCD display ON/OFF (D), cursor

ON/OFF or cursor-position character

blinking ON/OFF.

Moves the cursor or shifts the display

without changing the content of the DDRAM.

Sets the interface data length (DL), the

number of display lines (N) or the type of

character font (F).

Sets on CGRAM address. After that,

CGRAM data is transferred to and from

the CPU.
Sets a DDRAM address. After that DDRAM

data is transferred to and from the CPU.

Reads the Busy Flag (indicating that the

ML9044 is operating) and the content of

the address counter.
Writes data in DDRAM, ABRAM or CGRAM.

Reads data from DDRAM, ABRAM or CGRAM.

Writes data to control the contrast of the LCD.

Reads data to control the contrast of the LCD.

The
execution
time is
dependent
upon
frequencies

DD RAM
CG RAM
ABRAM
ACG
ADD

AAB
ADC

: Display data RAM
: Character generator RAM
: Arbitrator data RAM
: CGRAM address
: DDRAM address (Corresponds to
the cursor address)
: ABRAM address
: Address counter (Used by DDRAM,
ABRAM and CGRAM)

I/D = "0"

S/C = "0"
R/L = "0"
DL = "0"
N = "0"
F = "0"
BF = "0"

AS = "0"

I/D = "1"
S = "1"
S/C = "1"
R/L = "1"
D/L = "1"
N = "1"
F = "1"
BF = "1"

B = "1"
C = "1"
D = "1"
AS = "1"

(Decrement)

(Moves the cursor.)
(Left shift)
(4-bit data)
(1 line)
(5 ¥ 7 dots)
(Ready to accept
an instruction)

(Arbitrator Displays
arbitrator on the lower line)

(Increment)
(Shifts the display.)
(Shifts display.)
(Right shift)
(8-bit data)
(2 lines)
(5 ¥ 10 dots)
(Busy)

(Enables blinking.)
(Displyas the corsor.)
(Displays a character pattern.)
(Arbitrator Displays arbitrator
on the upper line)

1.52 ms

37 ms

0 ms

37 ms

I/D

R/L

S/C

ACG

ADD

ADC

WRITE DATA

READ DATA

Arbitrator Display Line Set

Sets the arbitrator display line.

37 ms

WRITE (Contrast Data) DATA

READ (Contrast Data) DATA

ABRAM address setting

Sets an ABRAM address. After that

ABRAM data is transferred to and from

the CPU.

37 ms

AAB

¥: Don't Care

¡ Semiconductor

ML9044

33/54

Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9044. The ML9044 starts
operation as instructed by the code received. The busy status of the ML9044 is rather longer than
the cycle time of the CPU, since the internal processing of the ML9044 starts at a timing which
does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9044 executes
the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0"
before sending an instruction code to the ML9044.

1) Display Clear

When this instruction is executed, the LCD display including arbitrator display is cleared and the
I/D entry mode is set to "Increment". The value of "S" (Display shifting) remains unchanged.
The position of the cursor or blink being displayed moves to the left end of the LCD (or the left
end of the line 1 in the 2line display mode).

Note:

All DDRAM and ABRAM data turn to "20" and "00" in hexadecimal, respectively. The
value of the address counter (ADC) turns to the one corresponding to the address "00"
(hexadecimal) of the DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency
of 270 kHz.

2) Cursor Home

When this instruction is executed, the cursor or blink position moves to the left end of the LCD
(or the left end of line 1 in the 2line display mode). If the display has been shifted, the display
returns to the original display position before shifting.
Note:

The value of the address counter (ADC) goes to the one corresponding to the address
"00" (hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency
of 270 kHz.

R/W

Instruction Code :

R/W

Instruction code:

: Don't Care

¡ Semiconductor

ML9044

34/54

3) Entry Mode Setting

(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= "1";
increment) or to the left by 1 character position (I/D= "0"; decrement) after an 8bit character
code is written to or read from the DDRAM. At the same time, the address counter (ADC) is also
incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement).
After a character pattern code is written to or read from the CGRAM, the address counter (ADC)
is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0";
decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented
by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement).

(2) When S = "1", the cursor or blink stops and the entire display shifts to the left (I/D = "1") or
to the right (I/D = "0") by 1 character position after a character code is written to the DDRAM.
In the case of S = "1",when a character code is read from the DDRAM, when a character pattern
data is written to or read from the CGRAM or when data is written to or read from the ABRAM,
normal read/write is carried out without shifting of the entire display. (The entire display does
not shift, but the cursor or blink shifts to the right (I/D = "1") or to the left (I/D = "0") by 1
character position.)
When S = "0", the display does not shift, but normal write/read is performed.
Note:

The execution time of this instruction is 37 ms (maximum) at an oscillation frequency
of 270 kHz.

4) Display Mode Setting

(1) The "D" bit (DB2) of this instruction determines whether or not to display character patterns
on the LCD.
When the "D" bit is "1", character patterns are displayed on the LCD.
When the "D" bit is "0", character patterns are not displayed on the LCD and the cursor/blink
setting is also canceled.

Note:

Unlike the Display Clear instruction, this instruction does not change the character
code in the DDRAM and ABRAM.

(2 ) When the "C" bit (DB1) is "0", the cursor turns off. When both the "C" and "D" bits are "1",
the cursor turns on.

(3) When the "B" bit (DB0) is "0", blinking is canceled. When both the "B" and "D" bits are "1",
blinking is performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor
are alternately displayed.
Note:

The execution time of this instruction is 37 ms (maximum) at an oscillation frequency
of 270kHz.

R/W

I/D

Instruction code:

R/W

Instruction code:

¡ Semiconductor

ML9044

35/54

5) Cursor/Display Shift

S/C = "0", R/L = "0" This instruction shifts left the cursor and blink positions by 1 (decrements

the content of the ADC by 1).

S/C = "0", R/L = "1" This instruction shifts right the cursor and blink positions by 1 (increments

the content of the ADC by 1).

S/C = "1", R/L = "0" This instruction shifts left the entire display by 1 character position. The

cursor and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)

S/C = "1", R/L = "1" This instruction shifts right the entire display by 1 character position. The

cursor and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)

In the 2line mode, the cursor or blink moves from the first line to the second line when the cursor
at digit 40 (27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between
the lines (from line 1 to line 2 or vice versa).
Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

6) Function Setting

(1) When the "DL" bit (DB4) of this instruction is "1", the data transfer to and from the CPU is
performed once by the use of 8 bits DB

to DB

When the "DL" bit (DB4) of this instruction is "0", the data transfer to and from the CPU is
performed twice by the use of 4 bits DB

to DB

(2) The 2line display mode is selected when the "N" bit (DB3) of this instruction is "1". The 1
line display mode is selected when the "N" bit is "0".
(3) The character font represented by 5 ¥ 7 dots is selected when the "F" bit (DB2) of this
instruction is "1". The character font represented by 5 ¥ 10 dots is selected when the "F" bit is "1"
and the "N" bit is "0".
After the ML9044 is powered on, this initial setting should be carried out before execution of any
instruction except the Busy Flag Read. After this initial setting, no instructions other than the DL
Set instruction can be executed. In the Serial I/F Mode, DL setting is ignored.

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

R/W

S/C

R/L

Instruction code:

: FDon't Care

R/W

: Don't Care

Instruction code:

Number of

display lines

Font size

Duty

Number of

biases

Number of

common signals

5¥7

1/9

5¥10

1/12

5¥7

1/17

5¥7

1/17

¡ Semiconductor

ML9044

36/54

7) CGRAM Address Setting

R/W

Instruction code:

R/W

Instruction code:

R/W

Instruction code:

This instruction sets the character data corresponding to the CGRAM address represented by the
bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM
address bits C

to C

set in the instruction code at that time.

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

8) DDRAM Address Setting

This instruction sets the character data corresponding to the DDRAM address represented by the
bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the DDRAM
address bits D6 to D0 set in the instruction code at that time.
In the 1line mode (the "N" bit is "1"), the DDRAM address represented by bits D6 to D0 (binary)
should be in the range "00" to "4F" in hexadecimal.
In the 2line mode (the "N" bit is "2"), the DDRAM address represented by bits D6 to D0 (binary)
should be in the range "00" to "27" or "40" to "67" in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or
read it from the DDRAM.

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

9) DDRAM/ABRAM/CGRAM Data Write

This instruction writes data represented by bits E

to E

(binary) to DDRAM, ABRAM or

CGRAM.
After data is written, the cursor, blink or display shifts according to the Cursor/Display Shift
instruction (see 5)).

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

¡ Semiconductor

ML9044

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10) Busy Flag/Address Counter Read (Execution time: 1 ms)

The "BF" bit (DB7) of this instruction tells whether the ML9044 is busy in internal operation (BF
= "1") or not (BF = "0").
When the "BF" bit is "1", the ML9044 cannot accept any other instructions. Before inputting a
new instruction, check that the "BF" bit is "0".
When the "BF" bit is "0", the ML9044 outputs the correct value of the address counter. The value
of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the
DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding
address setting.
When the "BF" bit is "1", the value of the address counter is not always correct because it may
have been incremented or decremented by 1 during internal operation.

11) DDRAM/ABRAM/CGRAM Data Read

A character code (P

to P

) is read from the DDRAM, DisplayON data (P

to P

) from the

ABRAM or a character pattern (P

to P

) from the CGRAM.

The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the
Transfer Mode Setting instruction (see 3).

Note:

Conditions for reading correct data

(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read
instruction is input.

(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see
5) is input before this Data Read instruction is input.

(3) When two or more consecutive RAM Data Read instructions are executed, the following read
data is correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

R/W

Instruction code:

R/W

Instruction code:

¡ Semiconductor

ML9044

38/54

Expansion Instruction Codes

The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal
processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is "1"), the ML9041 executes the Busy Flag Read instruction only.
Therefore, the CPU should ensure that the Busy Flag is "0" before sending an expansion
instruction code to the ML9044.

1) Arbitrator Display Line Set

This expansion instruction code sets the Arbitrator display line. The relationship between the
status of this bit and the common outputs is as follows:

2) Contrast Adjusting Data Write

R/W

Exparsion Instruction codes:

R/W

Exparsion Instraction codes:

CSR

duty

AS bit

Shift direction

Arbitrator's comon pin

1/9

COM1 Æ COM9

COM9

1/9

COM2 Æ COM9, COM1

COM1

1/12

COM1 Æ COM12

COM12

1/12

COM2 Æ COM12, COM1

COM1

1/17

COM1 Æ COM17

COM17

1/17

COM2 Æ COM17, COM1

COM1

1/9

COM9 Æ COM1

COM1

1/9

COM8 Æ COM1, COM9

COM9

1/12

COM12 Æ COM1

COM1

1/12

COM11 Æ COM1, COM12

COM12

1/17

COM17 Æ COM1

COM1

1/17

COM16 Æ COM1, COM17

COM17

This instruction writes contrast adjusting data (F

to F

) to the contrast register.

After contrast adjusting data is written in the register, the potential (VLCD) output to the V

varies according to the data written.
The VLCD becomes maximum when the content of the contrast register is "1F" (hexadecimal)
and becomes minimum when it is "00" (hexadecimal).
Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

¡ Semiconductor

ML9044

39/54

3) Contrast Adjusting Data Read

This instruction reads contrast adjusting data (G

to G

) from the contrast register.

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

4) ABRAM Address Setting

This instruction sets the character data corresponding to the ABRAM address represented by the
bits H

to H

(binary).

The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the ABRAM
address bits H

to H

set in the instruction code at that time.

The ABRAM address represented by bits H4 to H0 (binary) should be in the range "00" to "13"
in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or
read it from the DDRAM.

Note:

The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.

R/W

Exparsion Instruction code:

R/W

Exparsion Instruction code:

¡ Semiconductor

ML9044

40/54

LCD Drive Waveforms

The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/
9, 1/12 and 1/17 duties). See 1) to 3) below.
The relationship between the duty ratio and the frame frequency is as follows:

Note:

At an oscillation frequency (OSC) of 270 kHz

(1) Driving the LCD of one 24character line (1/9 duty, CSR = L, AS = 0) under the conditions
of the 1line display mode and the character font of 5 ¥ 7 dots

· COM

to COM

output DisplayOFF common signals.

Duty ratio

Frame Frequency

1/9

75.0Hz

1/12

56.3Hz

1/17

79.4Hz

COM

Character

Cursor
Arbitrator

COM

SEG

120

ML9044

¡ Semiconductor

ML9044

43/54

1) COM and SEG Waveforms on 1/9 Duty

1 frame

, V

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(first character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(second character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(cursor line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(arbitrator line)

9 1 2 3 4

7 8 9 1 2 3 4

7 8 9 1 2

, V

COM

, V

SEG

Display

turning-off

waveform

Display

turning-on

waveform

¡ Semiconductor

ML9044

44/54

2) COM and SEG Waveforms on 1/12 Duty

1 frame

, V

Display

turning-off

waveform

Display

turning-on

waveform

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(first character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(second character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(cursor line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(arbitrator line)

12 1 2 3 4 5 6

9 10 11 12 1 2 3 4 5 6

COM

SEG

¡ Semiconductor

ML9044

45/54

3) COM and SEG Waveforms on 1/17 Duty

1 frame

(

)

17 1 2 3 4 5 6 7 8 9 10 11 12 13

16 17 1 2

Display

turning-off

waveform

Display

turning-on

waveform

3 4

(

)

(

)

(

)

SEG

(

)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(first character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(second character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(corsor line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(arbitrator line)

¡ Semiconductor

ML9044

46/54

Initial Setting of Instructions

(a) Data transfer from and to the CPU using 8 bits of DB0 to DB7
1)

Turn on the power.

Wait for 15 ms or more after V

has reached 2.5V or higher.

Set "8 bits" with the Function Setting instruction.

Wait for 4.1 ms or more.

Set "8 bits" with the Function Setting instruction.

Wait for 100 ms or more.

Set "8 bits" with the Function Setting instruction.

Check the Busy Flag for No Busy (or wait for 100 ms or more).

Set "8 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)

10) Check the Busy Flag for No Busy.
11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode

Setting instruction and Arbitrator Display Line Setting Instruction.

12) Check the Busy Flag for No Busy.
13) Initialization is completed.

An example of instruction code for 3), 5) and 7)

(b) Data transfer from and to the CPU using 8 bits of DB4 to DB7
1)

Turn on the power.

Wait for 15 ms or more after V

has reached 2.5V or higher.

Set "8 bits" with the Function Setting instruction.

Wait for 4.1 ms or more.

Set "8 bits" with the Function Setting instruction.

Wait for 100 ms or more.

Set "8 bits" with the Function Setting instruction.

Check the Busy Flag for No Busy (or wait for 100 ms or longer).

Set "4 bits" with the Function Setting instruction.

10) Wait for 100 ms or longer.
11) Set "4 bits", "Number of LCD lines" and "Font size" with the Initial Setting instruction.

(After this, the number of LCD lines and the font size cannot be changed.)

12) Check the Busy Flag for No Busy.
13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode

Setting instruction and Arbitrator Display Line Setting Instruction

14) Check the Busy Flag for No Busy.
15) Initialization is completed.

An example of instruction code for 3), 5) and 7)

R/W

: Don't Care

R/W

¡ Semiconductor

ML9044

47/54

An example of instruction code for 9)

*: In 13), check the Busy Flag for No Busy before executing each instruction.

Turn on the power.

Wait for 15 ms or more after VDD has reached 2.5V or higher.

Set "Number of LCD lines" and "Font size" with the Function Setting Instruction.

Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.

Check the busy flag for No Busy.

Initialization is completed.

*: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.

R/W

¡ Semiconductor

ML9044

52/54

PAD CONFIGURATION

Pad Layout

Chip Size

: 10.62 ¥ 2.55mm

Chip Thickness : 625

20mm

Bump Size (1)

: 72 ¥ 72mm

Bump Size (2)

: 54 ¥ 96mm

Pad Coordinates

182

183

189

Pad

Symbol

X (

mm)

Y (

mm)

1099.8

5IN

BEB

CSR

SSR
P/S
V

5103

4914

4725

4536

4347

4158

3969

3780

3591

3402

3213

3024

2835

2646

2457

2268

2079

1890

1701

1512

Pad

Symbol

X (

mm)

Y (

mm)

R/W

SI
SHT
CS
OSC

OSC

COM

1323

1134

945

756

567

378

189

378

567

756

945

1134

1323

1512

1701

1890

2079

2268

¡ Semiconductor

ML9044

53/54

Pad

Symbol

X (

mm)

Y (

mm)

COM

DUMMY

2457

2646

2835

3024

3213

3402

3591

3780

3969

4158

4347

4536

4725

4914

5103

5184

Pad

Symbol

X (

mm)

Y (

mm)

SEG

102

SEG

101

SEG

100

SEG

3486

3402

3318

3234

3150

3066

2982

2898

2814

2730

2646

2562

2478

2394

2310

2226

2142

2058

1974

1890

100

DUMMY

5184

1806

101

DUMMY

5184

1722

102

SEG

120

4998

1638

103

SEG

119

4914

1554

104

SEG

118

4830

1470

105

SEG

117

4746

1386

106

SEG

116

4662

1302

107

SEG

115

4578

1218

108

SEG

114

4494

1134

109

SEG

113

4410

1050

110

SEG

112

4326

966

111

SEG

111

4242

882

112

SEG

110

4158

798

113

SEG

109

4074

714

114

SEG

108

3990

630

115

SEG

107

3906

546

116

SEG

106

3822

462

117

SEG

105

3738

378

118

SEG

104

3654

294

119

SEG

103

3570

SEG

210

120

1099.8

720

480

240

480

720

1087.8

SEG

1087.8

¡ Semiconductor

ML9044

54/54

Pad

Symbol

X (

mm)

Y (

mm)

SEG

126

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

SEG

141

SEG

142

SEG

143

SEG

144

SEG

145

SEG

146

SEG

147

SEG

148

SEG

149

1087.8

126

210

294

378

462

546

630

714

798

882

966

1050

1134

1218

1302

1386

1470

1554

1638

1722

1806

1890

1974

2058

2142

2226

Pad

Symbol

X (

mm)

Y (

mm)

SEG

2814

2898

2982

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

SEG

176

SEG

177

SEG

178

SEG

179

SEG

180

SEG

181

SEG

182

DUMMY

183

DUMMY

184

1087.8

720

480

3066

3150

3234

3318

3402

3486

3570

3654

3738

3822

3906

3990

4074

4158

4242

4326

4410

4494

4578

4662

4746

4830

4914

4998

5184

SEG

150

2310

DUMMY

185

240

5184

SEG

151

2394

DUMMY

186

5184

SEG

152

2478

DUMMY

187

240

5184

SEG

153

2562

DUMMY

188

480

5184

SEG

154

2646

DUMMY

189

720

5184

SEG

155

2730

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation.

Printed in Japan

E2Y0002-29-62

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9044

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9044