PEDL9044-03

1Semiconductor

This version: Mar. 2001
Previous version: Dec. 1999

ML9044-xxA/xxB

Preliminary

DOT MATRIX LCD CONTROLLER DRIVER

1/60

GENERAL DESCRIPTION

The ML9044 used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type
dot matrix LCD.

FEATURES

Easy interfacing with 8-bit or 4-bit microcontroller

Switchable between serial and parallel interfaces

Dot-matrix LCD controller/driver for a small (5

7 dots) or large (5

10 dots) font

Built-in circuit allowing automatic resetting at power-on

Built-in 17 common signal drivers and 120 segment signal drivers

Built-in character generation ROM capable of generating 160 small characters (5

7 dots) or 32 large

characters (5

10 dots)

Creation of character patterns by programming: up to 8 small character patterns (5

8 dots) or up to 4 large

character patterns (5

11 dots)

Built-in RC oscillation circuit using external or internal resistors

Program-selectable duties: 1/9 duty (1 line: 5

7 dots + cursor + arbitrator), 1/12 duty (1 line: 5

10 dots +

cursor + arbitrator), or 1/17 duty (2 lines: 5

7 dots + cursor + arbitrator)

Built-in bias dividing resistors to drive the LCD

Bi-directional transfer of segment outputs

Bi-directional transfer of common outputs

Equipped with a 120-dot arbitrator

Display shifting on each line

Built-in contrast control circuit

Built-in voltage multiplier circuit

Chip (Gold Bump)
Product name: ML9044-xxA/xxB CVWA (xx: Character generator ROM code number)

ML9044-51A/51B CVWA (General character generator ROM code)

xxA: With dummy bumps on both sides of the chip
xxB: Without dummy bumps on both sides of the chip

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1Semiconductor

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BLOCK DIAGRAM

C
S

3
A

Tim

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Parallel-

serial

converter

Dat

gis

t
e
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(DR)

SEG

rcu

i
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(E

)

Vol

t
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ltip

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(ADC)

s
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Cha

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(DD RA

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r
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(
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Cur

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Com

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120-bit shift register

120-bit latch

Segment Signal - driver

SEG

SSR

BEB

Cha

r
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(CG R

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I/O CIRCUITS

Applied to pins SSR, CSR,

/S, and BEB

Applied to pins T

, T

, and T

Applied to pins R/

, RS

, and RS

At serial I/F
At parallel I/F

At serial I/F

At parallel I/F

Applied to pin SI

Applied to pin E

Applied to pin

SHT

Applied to pin

: 1 (

= 0)

: 0 (

= 1)

: 0

At serial I/F

At parallel I/F

: 1 (

= 1)

: 0 (

= 0)

: 1

: 0
: 1

At serial I/F
At parallel I/F

: 0
: 1

Applied to pins DB

to DB

Output Enable signal

Applied to pin SO

Output Enable signal

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PIN DESCRIPTIONS

Symbol

Description

The input pin with a pull-up resistor to select Read ("H") or Write ("L") in the Parallel I/F
Mode.
This pin should be open in the Serial l/F Mode.

, RS

The input pins with a pull-up resistor to select a register in the Parallel l/F Mode.

This pin should be open in the Serial I/F Mode.

The input pin for data input/output between the CPU and the ML9044 and for
activating instructions in the Parallel l/F Mode.
This pin should be open in the Serial l/F Mode.

to DB

The input/output pins to transfer data of lower-order 4 bits between the CPU and the
ML9044 in the Parallel l/F Mode. The pins are not used for the 4-bit interface and
serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open when not used.

to DB

The input/output pins to transfer data of upper 4 bits between the CPU and the
ML9044 in the Parallel l/F Mode. The pins are not used for the serial interface.
Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F
Mode when not used.

OSC

The clock oscillation pins required for LCD drive signals and the operation of the
ML9044 by instructions sent from the CPU.
To input external clock, the OSC

pin should be used. The OSC

and the OSC

pins

should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC

and OSC

pins. The OSC

pin should be open.

To start oscillation with an internal resistor, the OSC

and OSC

pins should be

short-circuited outside the ML9044. The OSC

pin should be open.

COM

to COM

The LCD common signal output pins.
For 1/9 duty, non-selectable voltage waveforms are output via COM

to COM

. For

1/12 duty, non-selectable voltage waveforms are output via COM

to COM

SEG

to SEG

120

The LCD segment signal output pins.

Name of register

Data register

Instruction register

Expansion Instruction register

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1Semiconductor

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Symbol

Description

CSR

The input pin to select the transfer direction of the common signal output data.
At 1/n duty, data is transferred from COM1 to COMn when "L" is applied to this pin and
transferred from COMn to COM1 when "H" is applied to this pin.

SSR

The input pin to select the transfer direction of the segment signal output data.
"L": Data transfer from SEG

to SEG

120

"H": Data transfer from SEG

120

to SEG

, V

The pins to output bias voltages to the LCD.
For 1/4 bias : The V

and V

pins are shorted.

For 1/5 bias : The V

and V

pins are shorted.

BEB

The input pin to enable or disable the voltage multiplier circuit.
"L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage V

MUL

and the multiplied voltage

referenced to V

is output to the V

5IN

pin. The voltage multiplier circuit can be used

only when generating a level lower than GND.

The pin to input voltage to the voltage multiplier.

, V

5IN

The pins to supply the LCD drive voltage.
The LCD drive voltage is supplied to the V

pin when the voltage multiplier is not used

(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the
V

5IN

pin should be open.

The LCD drive voltage is supplied to the V

5IN

pin when the voltage multiplier is not used

(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V

should be open.
When the voltage multiplier is used (BEB = 1), the V

pin should be open (the

multiplied voltage is output to the V

5IN

pin). In this case, the internal contrast adjusting

circuit must be used. Capacitors for the voltage multiplier should be connected
between the V

pin and the V

5IN

pin.

The pin to connect the positive pin of the capacitor for the voltage multiplier.

The pin to connect the negative pin of the capacitor used for the voltage multiplier.

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Symbol

Description

, T

The input pins for test circuits (normally open). Each of these pins is equipped with a
pull-down resistor, so this pin should be left open.

The power supply pin.

GND

The ground level input pin.

The input pin to select the parallel or serial interface.
"L" selects the parallel interface.
"H" selects the serial interface.

The pin to enable this IC in the serial l/F mode.
"L" enables this IC.
"H" disables this IC.
This pin should be open in the parallel l/F mode.

SHT

The pin to input shift clock in the serial l/F mode.
Data inputting to the SI pin is carried out synchronizing with the rising edge of this
clock signal.
Data outputting from the SO pin is carried out synchronizing with the falling edge of
this clock signal.
This pin should be open in the parallel l/F mode.

The pin to input DATA in the serial l/F mode.
Data inputting to this pin is carried out synchronizing with the rising edge of the

SHT

signal.
This pin should be open in the parallel l/F mode.

The pin to output DATA in the serial l/F mode.
Data inputting to this pin is carried out synchronizing with the falling edge of the

SHT

signal.
This pin should be open in the parallel l/F mode.

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ABSOLUTE MAXIMUM RATINGS

(GND = 0 V)

Parameter

Symbol

Condition

Rating

Unit

Applicable pins

Supply Voltage

Ta = 25°C

0.3 to +6.5

GND

LCD Driving Voltage

, V

Ta = 25°C

7.5 to V

+0.3

, V

5IN

, V

Input Voltage

Ta = 25°C

0.3 to V

+0.3

, E,

SHT

, CSR,

/S,

SSR, Sl, RS

, RS

, BEB,

to T

, DB

to DB

, V

Storage Temperature

STG

55 to +150

°C

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V)

Parameter

Symbol

Condition

Range

Unit

Applicable pins

Supply Voltage

2.5 to 5.5

GND

LCD Driving Voltage

(See Note)

2.8 to 7.0

5IN

)

Voltage Multipler
Operating Voltage

MUL

BEB = 1

1.40 to

3.5

Operating Temperature

40 to +85

°C

Note:

This voltage should be applied across V

and V

. The following voltages are output to the V

, V

) and V

pins:

1/4 bias

= {V

)/4} ±0.15 V

= V

= {V

)/2} ±0.15 V

= {V

)/4 } ±0.15 V

1/5 bias

= {V

)/5} ±0.15 V

= {V

)/5} ±0.15 V

= V

= {V

)/5} ±0.15 V

= {V

)/5} ±0.15 V

The voltages at the V

, V

), V

and V

pins should satisfy

> V

) > V

> V

(Higher

Lower)

* Do not apply short-circuiting across output pins and across an output pin and an input/output

pin or the power supply pin in the output mode.

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1Semiconductor

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ELECTRICAL CHARACTERISTICS

DC Characteristics

(GND

= 0 V, V

= 2.5 to 5.5 V, Ta = 40 to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit Applicable pin

"H" Input Voltage 1

IH1

0.8V

"L" Input Voltage 1

IL1

0.3

0.2V

, RS

E, DB

to DB

SHT

/S, Sl,

"H" Input Voltage 2

IH2

0.8V

"L" Input Voltage 2

IL2

0.3

0.2V

OSC

, SSR,

CSR, BEB

"H" Output Voltage 1

OH1

= 0.1 mA

0.75V

"L" Output Voltage 1

OL1

= +0.1 mA

0.2V

to DB

, SO

"H" Output Voltage 2

OH2

= 13

0.9V

"L" Output Voltage 2

OL2

= +13

0.1V

OSC

OCH

= 4

0.3

CMH

OCMH

= ±4

0.3

+0.3

CML

OCML

= ±4

0.3

+0.3

COM Voltage Drop

OCL

= +4

= 5 V

Note 1

+0.3

COM

OSH

= 4

0.3

SMH

OSMH

= ±4

0.3

+0.3

SML

OSML

= ±4

0.3

+0.3

SEG Voltage Drop

OSL

= +4

= 5 V

Note 1

+0.3

SEG

120

Input Leakage Current

| IIL |

= 5 V, V

= 5 V or 0 V

1.0

E, SSR, CSR,
BEB,

SHT

/S,

CS, Sl

= 5 V, V

= GND

Input Current 1

| II1 |

= 5 V, V

= V

Excluding current flowing
through the pull-up resistor
and the output driving MOS

2.0

, RS

to DB

, SO

= 5 V, V

= V

105

Input Current 2

| II2 |

= 5 V, V

= V

Excluding current flowing
through the pull-down resistor

2.0

, T

Supply Current

= 5 V

Note 2

1.2

mA V

GND

LCD Bias Resistor

4.0

, V

Oscillation Frequency
of External Resistor Rf

osc1

Rf = 180 k

±2%

Note 3

175

270

400

kHz OSC

, OSC

Oscillation Frequency
of Internal Resistor Rf

osc2

OSC

: Open

Note 4

OSC

and OSC

: Short-

circuited

140

270

480

kHz

OSC

, OSC

OSC

Clock Input
Frequency

OSC

, OSC

: Open

Input from OSC

125

480

kHz

Input Clock Duty

duty

Note 5

Input Clock Rise
Time

Note 6

0.2

x
ternal C

l
oc

Input Clock Fall Time

Note 6

0.2

OSC

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1Semiconductor

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(GND

= 0 V, V

= 2.5 to 5.5 V, Ta = 40 to +85°C)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable

pins

LCD

MAX

= 5 V, 1/5 bias

5IN

= 0 V,

Contrast data: 1F

4.6

Maximum and
minimum LCD
drive voltages
when internal
variable resistors
are used.

LCD

MIN

= 5 V, 1/5 bias

5IN

= 0 V,

Contrast data: 00

3.4

LCD1

1/5 bias

2.8

7.0

Bias Voltage for
Driving LCD by
External Input

LCD2

Note 7 1/4 bias

2.8

7.0

Voltage Multiplier
Output Voltage

5OUT

= 3 V, V

= 0 V

f = 270 kHz
A capacitor for the voltage
multiplier = 4.7

No load
BEB = H

)

20.1

)

2+1.2 V

, V

5IN

Voltage Multiplier
Input Voltage

3.5 V

Note 1: Applied to the voltage drop occurring between any of the V

, V

and V

pins and any of the

common pins (COM

to COM

) when the current of 4

A flows in or flows out at one common

pin.
Also applied to the voltage drop occurring between any of the V

, V

) and V

pins and

any of the segment pins (SEG

to SEG

120

) when the current of 4

A flows in or flows out at one

common pin.

The current of 4

A flows out when the output level is V

or flows in when the output level is

Note 2: Applied to the current flowing into the V

pin when the external clock (f

OSC2

= f

= 270 kHz) is

fed to the internal R

oscillation or OSC

under the following conditions:

= 5 V

GND = V

= 0 V,

, V

) and V

: Open

E, SSR, CSR, and BEB: "L" (fixed)
Other input pins: "L" or "H" (fixed)
Other output pins: No load

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Note 3:

Note 4:

OSC

The wire between OSC

and OSC

should be as short

as possible. Keep OSC

open.

OSC

The wire between OSC

and R

and the wire between

OSC

and R

should be as short as possible.

Keep OSC

open.

= 180 k

Note 5:

waveform

Applied to the pulses entering from the OSC

duty

= t

/(t

+ t

) ×100 (%)

Note 6:

0.7V

Applied to the pulses entering from the OSC

0.7V

0.3V

Note 7: For 1/4 bias, V

and V

pins are short-circuited. V

pin is open.

For 1/5 bias, V

and V

pins are short-circuited. V

pin is open.

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Switching Characteristics (The following ratings are subject to change after ES evaluation.)

Parallel Interface Mode

The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below:

1) WRITE MODE (Timing for input from the CPU)

= 2.5 to 5.5 V, Ta = 40 to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

, RS

Setup Time

E Pulse Width

450

, RS

Hold Time

E Rise Time

E Fall Time

E Pulse Width

430

E Cycle Time

1000

to DB

Input Data Hold Time

195

to DB

Input Data Setup Time

, RS

to DB

Input

Data

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2) READ MODE (Timing for output to the CPU)

= 2.5 to 5.5 V, Ta = 40 to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

, RS

Setup Time

E Pulse Width

450

, RS

Hold Time

E Rise Time

E Fall Time

E Pulse Width

430

E Cycle Time

1000

to DB

Output Data Delay Time

350

to DB

Output Data Hold Time

, RS

to DB

Output

Data

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Serial Interface Mode

= 2.5 to 5.5 V, Ta = 40 to +85°C)

Parameter

Symbol

Min.

Typ.

Max.

Unit

SHT

Cycle Time

SCY

500

Setup Time

CSU

100

Hold Time

100

SHT

Setup Time

SSU

SHT

Hold Time

200

SHT

"H" Pulse Width

SWH

200

SHT

"L" Pulse Width

SWL

200

SHT

Rise Time

SHT

Fall Time

Sl Setup Time

DISU

100

Sl Hold Time

DIH

100

Data Output Delay Time

DOD

160

Data Output Hold Time

CDH

SCY

DOD

CDH

SHT

CSU

SSU

SWL

SWH

DISU

DIH

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FUNCTIONAL DESCRIPTION

Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)

These registers are selected by setting the level of the Register Selection input pins RS

and RS

. The DR is

selected when both RS

and RS

are "H". The IR is selected when RS

is "L" and RS

is "H". The ER is selected

when both RS

and RS

are "L". (When RS

is "H" and RS

is "L", the ML9044 is not selected.)

The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character
generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the
DDRAM, AMRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically transferred from
the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked
by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected
to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next
address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/

W (Read/Write) pin.

Table 1 R/

pin status and register operation

Operation

Writing in the IR

Reading the Busy flag (BF) and the address counter (ADC)

Writing in the DR

Reading from the DR

Writing in the ER

Reading the contrast code

Busy Flag (BF)

The status "1" of the Busy Flag (BF) indicates that the ML9044 is carrying out internal operation.
When the BF is "1", any new instruction is ignored.
When R/

W = "H", RS

= "L" and RS

= "H", the data in the BF is output to the DB

New instructions should be input when the BF is "0".
When the BF is "1", the output code of the address counter (ADC) is undefined.

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Address Counter (ADC)

The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a
cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined
register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the
ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is
written in or read from the DDRAM, ABRAM or CGRAM.
The data in the ADC is output to DB

to DB

when R/

W = "H", RS

= "L", RS

= "H" and BF = "0".

Timing Generator

The timing generator generates timing signals for the internal operation of the ML9044 activated by the instruction
sent from the CPU or for the operation of the internal circuits of the ML9041 such as DDRAM, ABRAM,
CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying
will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU
writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.

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Display Data RAM (DDRAM)

This RAM stores the display data represented in 8-bit character coding (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM
addresses (to be set in the ADC) are represented in hexadecimal.

MSB

LSB

Hexadecimal

ADC

(Example) Representation of DDRAM address = 12

1) Relationship between DDRAM addresses and display positions (1-line display mode)

00 01 02 03 04

16 17

Digit

1 2 3 4 5

23 24

Left

end

Right

end

Display position
DD RAM address (hexadecimal)

In the 1-line display mode, the ML9044 can display up to 24 characters from digit 1 to digit 24. While the
DDRAM has addresses "00" to "4F" for up to 80 character codes, the area not used for display can be used as a
RAM area for general data. When the display is shifted by instruction, the relationship between the LCD
display and the DDRAM address changes as shown below:

4F 00 01 02

15 16

Digit

1 2 3 4

23 24

(Display shifted to the right)

01 02 03 04

17 18

Digit

1 2 3 4

23 24

(Display shifted to the left)

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2) Relationship between DDRAM addresses and display positions (2-line display mode)

In the 2-line mode, the ML9044 can display up to 48 characters (24 characters per line) from digit 1 to digit 24.

00 01 02 03 04

Digit

1 2 3 4 5

16 17

23 24

40 41 42 43 44

56 57

Line 1

Line 2

Display position
DD RAM
address (hexadecimal)

Note: The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at

digit 1 in the second line.

When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address
changes as shown below:

27 00 01 02

Digit

1 2 3 4

15 16

23 24

67 40 41 42

55 56

Line 1

Line 2

01 02 03 04

Digit

1 2 3 4

17 18

23 24

41 42 43 44

57 58

Line 1

Line 2

(Display shifted to the right)

(Display shifted to the left)

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Character Generator ROM (CGROM)

The CGROM generates small character patterns (5

7 dots, 160 patterns) or large character patterns (5

10 dots,

32 patterns) from the 8-bit character code signals in the DDRAM.
When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the
character pattern is displayed in the display position specified by the DDRAM address.
Character codes 20 to 7F and A0 to FF are contained in the character code area in the CG ROM.
Character codes 20 to 7F and A0 to DF are contained in the character code area for the 5

7-dot character patterns.

Character codes E0 to FF are contained in the ROM area for 5

10-dot character patterns.

The general character generator ROM codes are 51A/51B.
The relationship between character codes and general purpose character patterns are indicated in Table2.

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Character Generator RAM (CGRAM)

The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes =
512 bits) can store up to 8 small character patterns (5

8 dots) or up to 4 large character patterns (5

11 dots).

When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F;
hex.) assigned in Table 2 to the DDRAM. This enables outputting the character pattern to the LCD display
position corresponding to the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM.

1) Small character patterns (5

8 dots) (See Table 3-1.)

(1) A method of writing character patterns to the CGRAM from the CPU

The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB

to DB

The data lines DB

to DB

correspond to the CGRAM data bits 0 to 7, respectively (see Table 3-1). Input

data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is
automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary
to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all "1", which means 7 in
hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the data given
by the CGRAM data bits 5 to 7 is not. Therefore, the CGRAM data bits 5 to 7 can be used as a RAM area.

(2) A method of displaying CGRAM character patterns on the LCD

The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit 3 of a
character code is not used, the character pattern "0" in Table 3-1 can be selected using the character code
"00" or "08" in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5, respectively.)

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2) Large character patterns (5

11 dots) (See Table 3-2.)

(1) A method of writing character patterns to the CGRAM from the CPU

The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB

to DB

The data lines DB

to DB

correspond to the CGRAM data bits 0 to 7, respectively (see Table 3-2). Input

data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is
automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary
to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all "1", which means A in
hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for
displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display
the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in hexadecimal
(set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data given by the
CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These bits can be written
and read as a RAM area.

(2) A method of displaying CGRAM character patterns on the LCD

The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bits 0 and 3
of a character code are not used, the character pattern "

" in Table 3-2 can be selected with a character

code "00", "01", "08" or "09" in hexadecimal.
When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the
DDRAM, the character pattern is displayed in the display position specified by the DDRAM address.
(The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5, respectively.)

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Arbitrator RAM (ABRAM)

The arbitrator RAM (ABRAM) stores arbitrator display data.
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address area is 00 to 23
(00H to 17H).
Although an address exceeding 23 (17H) can be set or the address already set may exceed it due to automatic
increment or decrement processing, any address out of the valid address area is ignored.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the
cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.

MSB

LSB

Hexadecimal

ADC

The arbitrator RAM can store a maximum of 120 dots of the arbitrator Display-ON data in units of 5 dots.
The arbitrator display is not shifted by any instructions and has the following relationship with the LCD display
positions.

E4 E3 E2 E1 E0

* Don't Care

Display - ON data

5XSn+1

5XSn+5

Configuration of input display data

Input data

Relationship between display-ON

data and segment pins

Sn = AB RAM address (0 to 23)

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Table 2 Relationship between Character Codes and Character Patterns of the ML9044-51A/51B

(General Character Codes)

The character code area in the CG ROM: Character codes 20H to 7FH, A0H to FFH.

7-dot ROM area: 20H to 7FH, A0H to DFH

10-dot ROM area: E0H to FFH

The CG RAM area

: Character codes 00H to FFH

00H:

20H:

28H: (

30H: 0

38H: 8

21H: !

29H: )

31H: 1

39H: 9

22H: "

2AH:

32H: 2

3AH: :

23H: #

2BH: +

33H: 3

3BH: ;

24H: $

2CH: ,

34H: 4

3CH: <

25H: %

2DH: -

35H: 5

3DH: =

26H: &

2EH: .

36H: 6

3EH: >

27H: '

2FH: /

37H: 7

3FH: ?

40H: @

48H: H

50H: P

41H: A

49H: I

51H: Q

42H: B

4AH: J

52H: R

43H: C

4BH: K

53H: S

44H: D

4CH: L

54H: T

45H: E

4DH: M

55H: U

46H: F

4EH: N

56H: V

47H: G

4FH: O

57H: W

01H:

02H:

03H:

04H:

05H:

06H:

07H:

08H:

09H:

0AH:

0BH:

0CH:

0DH:

0EH:

0FH:

CG RAM(1)

CG RAM(2)

CG RAM(3)

CG RAM(4)

CG RAM(5)

CG RAM(6)

CG RAM(7)

CG RAM(8)

CG RAM(1)

CG RAM(2)

CG RAM(3)

CG RAM(4)

CG RAM(5)

CG RAM(6)

CG RAM(7)

CG RAM(8)

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Table 3-1

Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5

×
×
×
×

7 dot character mode. (Examples)

CG RAM data

(Character pattern)

(Character code)

DD RAM data

0 1 1 1 0

1 0 0 0 1

0 1 1 1 0

0 0 0 0 0

7 6 5 4 3 2 1 0

LSB MSB

LSB

0 0 0 0

0 0 0

× × ×

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 0 1 0 0

1 0 0 1 0

1 0 0 0 1

0 0 0 0 0

0 0 0 0

0 0 1

×××

0 1 1 1 0

0 0 1 0 0

0 1 1 1 0

0 0 0 0 0

0 0 0 0

1 1 1

× × ×

CG RAM

address

5 4 3 2 1 0

MSB

0 0 0 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

0 0 1 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

1 1 1 0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

: Don't Care

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Table 3-2

Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5

×
×
×
×

10 dot character mode (Examples)

CG RAM

CG RAM data

address

(Character pattern)

(Character code)

DD RAM data

5 4 3 2 1 0 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

LSB

MSB

LSB

MSB

LSB

0 0 0 0

0 0

× × ×

0 0 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 0 0 0

0 1

× × ×

0 0 0 0 0

0 1 1 1 1

1 0 0 0 1

0 1 1 1 1

0 0 0 0 1

0 1 1 1 0

0 0 0 0 0

× × × × ×

0 0 0 0

1 1

× × ×

0 0 0 0 0

1 1 0 1 1

0 1 0 1 0

1 0 0 0 1

0 1 1 1 0

0 0 0 0 0

× × × × ×

0 1 0 0 0

0 1 1 1 1

1 0 0 1 0

0 1 1 1 1

0 1 0 1 0

1 1 1 1 1

0 0 0 1 0

0 0 0 0 0

× × × × ×

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

0 1 0 0 0 0

1 1 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

: Don't Care

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Cursor/Blink Control Circuit

This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC
(Address Counter).
For example, when the ADC stores a value of "07" (hexadecimal), the cursor or blink is displayed as follows:

0 0 0 1 1 1

00 01 02 03 04

07 08

Digit

1 2 3 4 5

8 9

Cursor/blink position

16 17

23 24

6 7

05 06

00 01 02 03 04

07 08

Digit

1 2 3 4 5

8 9

Cursor/blink position

16 17

23 24

6 7

05 06

40 41 42 43 44

47 48

56 57

45 46

First line

ADC

In 1-line display mode

In 2-line display mode

Second line

Note:

The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in
the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is
holding a CGRAM or ABRAM address.

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LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR)

The ML9044 has 17 common signal outputs and 120 segment signal outputs to display 24 characters (in the 1-line
display mode) or 48 characters (in the 2-line display mode).
The character pattern is converted into serial data and transferred in series through the shift register.
The transfer direction of serial data is determined by the SSR pin. The shift direction of common signals is
determined by the CSR pin. The following tables show the transfer and shift directions:

SSR

Transfer direction

SEG

120

SEG

120

SEG

CSR

duty

AS bit

Shift Direction

Arbitrator's common pin

1/9

COM1

COM9

1/9

COM2

COM9, COM1

COM1

1/12

COM1

COM12

1/12

COM2

COM12, COM1

COM1

1/17

COM1

COM17

1/17

COM2

COM17, COM1

COM1

1/9

COM9

COM1

1/9

COM8

COM1, COM9

COM9

1/12

COM12

COM1

1/12

COM11

COM1, COM12

COM12

1/17

COM17

COM1

1/17

COM16

COM1, COM17

COM17

* Refer to the Expansion Instruction Codes section about the AS bit.

Signals to be input to the SSR and CSR pins should be determined at power-on and be kept unchanged.

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Built-in Reset Circuit

The ML9044 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is "1" and the ML9044 does not accept any instruction from the CPU
(other than the Read BF instruction).
The Busy Flag is "1" for about 15 ms after the V

becomes 2.5 V or higher.

During this initialization, the ML9044 performs the following instructions:

Display clearing

CPU interface data length = 8 bits

(DL = "1")

1-line LCD display

(N = "0")

Font size = 5

7 dots

(F = "0")

ADC counting = Increment

(I/D = "1")

Display shifting = None

(S = "0")

Display = Off

(D = "0")

Cursor = Off

(C = "0")

Blinking = Off

(B = "0")

10) Arbitrator = Displayed in the lower line

(AS = "0")

11) Setting 1FH (hexadecimal) to the Contrast Data

To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the
built-in reset circuit may not work properly. In such a case, initialize the ML9044 with the instructions from the
CPU. The use of a battery always requires such initialization from the CPU. (See "Initial Setting of Instructions")

2.5 V

0.2 V

OFF

0.1 ms

100 ms

1 ms

OFF

Figure 1 Power-on and Power-off Waveform

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I/F with CPU

Parallel interface mode
The ML9044 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit
microcontroller (CPU).

1) 8-bit interface data length

The ML9044 uses all of the 8 data bus lines DB

to DB

at a time to transfer data to and from the CPU.

2) 4-bit interface data length

The ML9044 uses only the higher-order 4 data bus lines DB

to DB

twice to transfer 8-bit data to and from the

CPU.
The ML9044 first transfers the higher-order 4 bits of 8-bit data (DB

to DB

in the case of 8-bit interface data

length) and then the lower-order 4 bits of the data (DB

to DB

in the case of 8-bit interface data length).

The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4
bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is
made, the following data transfer cannot be completed properly.

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Busy

(Internal operation)

Busy

ADC

Writing In IR

(Instruction

Reading BF (Busy Flag)

and ADC (Address Counter)

Writing In DR

(Data Register)

Figure 2 8-Bit Data Transfer

Busy

(Internal operation)

Busy

ADC

Writing In IR

(Instruction

Reading BF (Busy Flag)

and ADC (Address Counter)

Writing In DR

(Data Register)

Figure 3 4-Bit Data Transfer

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Serial Interface Mode

In the Serial I/F Mode, the ML9044 interfaces with the CPU via the

CS, SHT, SI and SO pins.

Writing and reading operations are executed in units of 16 bits after the

CS signal falls down. If the CS signal rises

up before the completion of 16-bit unit access, this access is ignored.
When the BF bit is "1", the ML9044 cannot accept any other instructions. Before inputting a new instruction,
check that the BF bit is "0". Any access when the BF bit is "1" is ignored.
Data format is LSB-first.

Examples of Access in the Serial I/F Mode

1) WRITE MODE

SHT

2) READ MODE

SHT

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Instruction Codes

Table of Instruction Codes

Code

Instruction

Function

Execution

Time

f = 270 kHz

Display Clear

Clears all the displayed digits of the
LCD and sets the DDRAM address 0 in
the address counter. The arbitrator
data is cleared.

1.52 ms

Cursor Home

Sets the DDRAM address 0 in the
address counter and shifts the display
back to the original. The content of the
DDRAM remains unchanged.

1.52 ms

Entry Mode
Setting

I/D

Determines the direction of movement
of the cursor and whether or not to shift
the display. This instruction is
executed when data is written or read.

Display
ON/OFF Control 1

Sets LCD display ON/OFF (D), cursor
ON/OFF or cursor-position character
blinking ON/OFF.

Cursor/Display
Shift

S/C R/L

Moves the cursor or shifts the display
without changing the content of the
DDRAM.

Function Setting 1

Sets the interface data length (DL), the
number of display lines (N) or the type
of character font (F).

CGRAM
Address Setting

ACG

Sets on CGRAM address. After that,
CGRAM data is transferred to and from
the CPU.

DDRAM
Address Setting

ADD

Sets a DDRAM address. After that,
DDRAM data is transferred to and from
the CPU.

Busy Flag/
Address Read

ADC

Reads the Busy Flag (indicating that
the ML9044 is operating) and the
content of the address counter.

RAM Data Write 1

WRITE DATA

Writes data in DDRAM, ABRAM or
CGRAM.

RAM Data Read 1

READ DATA

Reads data from DDRAM, ABRAM or
CGRAM.

Arbitrator
Display Line Set

AS Sets the arbitrator display line.

Contrast Control
Data Write

WRITE (Contrast Data)

DATA

Writes data to control the contrast of
the LCD.

Contrast Control
Data Read

READ (Contrast Data)

DATA

Reads data to control the contrast of
the LCD.

ABRAM
Address Setting

AAB

Sets an ABRAM address. After that,
ABRAM data is transferred to and from
the CPU.

I/D = "1" (Increment)

I/D = "0" (Decrement)

S = "1"

(Shifts the display.)

S/C = "1" (Shifts display.)

S/C = "0" (Moves the cursor.)

R/L = "1" (Right shift)

R/L = "0" (Left shift)

D/L = "1" (8-bit data)

DL = "0" (4-bit data)

N = "1" (2 lines)

N = "0"

(1 line)

F = "1"

(5 x 10 dots)

F = "0"

(5 x 7 dots)

BF = "1" (Busy)

BF = "0" (Ready to accept

an instruction)

B = "1"

(Enables blinking)

C = "1" (Displays the cursor.)
D = "1" (Displays a character pattern.)
AS = "1" (Arbitrator Displays AS = "0" (Arbitrator Displays

arbitrator on the

upper line)

lower line)

DD RAM: Display data RAM
CG RAM: Character generator RAM
ABRAM: Arbitrator data RAM
ACG:

CGRAM address

ADD:

DDRAM address
(Corresponds to the cursor
address)

AAB:

ABRAM address

ADC:

Address counter (Used by
DDRAM, ABRAM and
CGRAM)

The
execution
time is
dependent
upon
frequen-
cies.

: Don't Care

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Instruction Codes

An instruction code is a signal sent from the CPU to access the ML9044. The ML9044 starts operation as
instructed by the code received. The busy status of the ML9044 is rather longer than the cycle time of the CPU,
since the internal processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is "1"), the ML9044 executes the Busy Flag Read instruction only. Therefore, the CPU
should ensure that the Busy Flag is "0" before sending an instruction code to the ML9044.

1) Display Clear

Instruction Code:

When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry
mode is set to "Increment". The value of "S" (Display shifting) remains unchanged. The position of the cursor
or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display
mode).

Note:

All DDRAM and ABRAM data turn to "20" and "00" in hexadecimal, respectively. The value of the
address counter (ADC) turns to the one corresponding to the address "00" (hexadecimal) of the
DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.

2) Cursor Home

Instruction code:

: Don't Care

When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end
of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display
position before shifting.

Note:

The value of the address counter (ADC) goes to the one corresponding to the address "00"
(hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.

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3) Entry Mode Setting

I/D

Instruction code:

(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= "1"; increment) or to

the left by 1 character position (I/D= "0"; decrement) after an 8-bit character code is written to or read
from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D =
"1"; increment) or decremented by 1 (when I/D = "0"; decrement). After a character pattern code is
written to or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = "1";
increment) or decremented by 1 (when I/D = "0"; decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1
(when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement).

(2) When S = "1", the cursor or blink stops and the entire display shifts to the left (I/D = "1") or to the right

(I/D = "0") by 1 character position after a character code is written to the DDRAM.
In the case of S = "1", when a character code is read from the DDRAM, when a character pattern data is
written to or read from the CGRAM or when data is written to or read from the ABRAM, normal
read/write is carried out without shifting of the entire display. (The entire display does not shift, but the
cursor or blink shifts to the right (I/D = "1") or to the left (I/D = "0") by 1 character position.)
When S = "0", the display does not shift, but normal write/read is performed.

Note:

The execution time of this instruction is 37

s (maximum) at an oscillation frequency of

270 kHz.

4) Display Mode Setting

Instruction code:

(1) The "D" bit (DB2) of this instruction determines whether or not to display character patterns on the LCD.

When the "D" bit is "1", character patterns are displayed on the LCD.
When the "D" bit is "0", character patterns are not displayed on the LCD and the cursor/blink setting is
also canceled.

Note:

Unlike the Display Clear instruction, this instruction does not change the character code in the
DDRAM and ABRAM.

(2) When the "C" bit (DB1) is "0", the cursor turns off. When both the "C" and "D" bits are "1", the cursor

turns on.

(3) When the "B" bit (DB0) is "0", blinking is canceled. When both the "B" and "D" bits are "1", blinking is

performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are
alternately displayed.

Note:

The execution time of this instruction is 37

s (maximum) at an oscillation frequency of

270 kHz.

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5) Cursor/Display Shift

S/C

R/L

Instruction code:

: Don't Care

S/C = "0", R/L = "0"

This instruction shifts left the cursor and blink positions by 1 (decrements the
content of the ADC by 1).

S/C = "0", R/L = "1"

This instruction shifts right the cursor and blink positions by 1 (increments the
content of the ADC by 1).

S/C = "1", R/L = "0"

This instruction shifts left the entire display by 1 character position. The cursor
and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)

S/C = "1", R/L = "1"

This instruction shifts right the entire display by 1 character position. The cursor
and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)

In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40
(27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from
line 1 to line 2 or vice versa).

Note:

The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

6) Function Setting

: Don't Care

Instruction code:

(1) When the "DL" bit (DB

) of this instruction is "1", the data transfer to and from the CPU is performed

once by the use of 8 bits DB

to DB

When the "DL" bit (DB

) of this instruction is "0", the data transfer to and from the CPU is performed

twice by the use of 4 bits DB

to DB

(2) The 2-line display mode is selected when the "N" bit (DB

) of this instruction is "1". The 1-line display

mode is selected when the "N" bit is "0".

(3) The character font represented by 5

7 dots is selected when the "F" bit (DB

) of this instruction is "1".

The character font represented by 5

10 dots is selected when the "F" bit is "1" and the "N" bit is "0".

After the ML9044 is powered on, this initial setting should be carried out before execution of any
instruction except the Busy Flag Read. After this initial setting, no instructions other than the DL Set
instruction can be executed. In the Serial I/F Mode, DL setting is ignored.

Number of

display lines

Font size

Duty

Number of

biases

Number of

common signals

1/9

1/12

1/17

Note:

The execution time of this instruction is 37

s at an oscillation frequency (OSC) of

270 kHz.

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7) CGRAM Address Setting

Instruction code:

This instruction sets the character data corresponding to the CGRAM address represented by the bits C

to C

(binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C

set in the instruction code at that time.

Note: The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

8) DDRAM Address Setting

Instruction code:

This instruction sets the character data corresponding to the DDRAM address represented by the bits D

to D

(binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the DDRAM address bits D

set in the instruction code at that time.

In the 1-line mode (the "N" bit is "1"), the DDRAM address represented by bits D

to D

(binary) should be in

the range "00" to "4F" in hexadecimal.
In the 2-line mode (the "N" bit is "2"), the DDRAM address represented by bits D

to D

(binary) should be in

the range "00" to "27" or "40" to "67" in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or read it from the
DDRAM.

Note: The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

9) DDRAM/ABRAM/CGRAM Data Write

Instruction code:

This instruction writes data represented by bits E

to E

(binary) to DDRAM, ABRAM or CGRAM.

After data is written, the cursor, blink or display shifts according to the Cursor/Display Shift instruction (see
5)).

Note: The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

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10) Busy Flag/Address Counter Read (Execution time: 1

Instruction code:

The "BF" bit (DB7) of this instruction tells whether the ML9044 is busy in internal operation (BF = "1") or not
(BF = "0").
When the "BF" bit is "1", the ML9044 cannot accept any other instructions. Before inputting a new instruction,
check that the "BF" bit is "0".
When the "BF" bit is "0", the ML9044 outputs the correct value of the address counter. The value of the
address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and
CGRAM addresses is set in the counter is determined by the preceding address setting.
When the "BF" bit is "1", the value of the address counter is not always correct because it may have been
incremented or decremented by 1 during internal operation.

11) DDRAM/ABRAM/CGRAM Data Read

Instruction code:

A character code (P

to P

) is read from the DDRAM, Display-ON data (P

to P

) from the ABRAM or a

character pattern (P

to P

) from the CGRAM.

The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the Transfer Mode
Setting instruction (see 3).

Note: Conditions for reading correct data

(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input.

(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input

before this Data Read instruction is input.

(3) When two or more consecutive RAM Data Read instructions are executed, the following read data is

correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.

Note:

The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

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Expansion Instruction Codes

The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal processing of the
ML9044 starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the
ML9044 executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is
"0" before sending an expansion instruction code to the ML9044.

1) Arbitrator Display Line Set

Expansion instruction code:

This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit
and the common outputs is as follows:
For display examples, refer to LCD Drive Waveforms section.

CSR

duty

AS bit

Shift direction

Arbitrator's common pin

1/9

COM1

COM9

1/9

COM2

COM9, COM1

COM1

1/12

COM1

COM12

1/12

COM2

COM12, COM1

COM1

1/17

COM1

COM17

1/17

COM2

COM17, COM1

COM1

1/9

COM9

COM1

1/9

COM8

COM1, COM9

COM9

1/12

COM12

COM1

1/12

COM11

COM1, COM12

COM12

1/17

COM17

COM1

1/17

COM16

COM1, COM17

COM17

2) Contrast Adjusting Data Write

Expansion instruction code:

This instruction writes contrast adjusting data (F

to F

) to the contrast register.

After contrast adjusting data is written in the register, the potential (VLCD) output to the V

pin varies

according to the data written.
The VLCD becomes maximum when the content of the contrast register is "1F" (hexadecimal) and becomes
minimum when it is "00" (hexadecimal).

Note: The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

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3) Contrast Adjusting Data Read

Expansion instruction code:

This instruction reads contrast adjusting data (G

to G

) from the contrast register.

Note: The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

4) ABRAM Address Setting

Expansion instruction code:

This instruction sets the character data corresponding to the ABRAM address represented by the bits H

to H

(binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the ABRAM address bits H

set in the instruction code at that time.

The ABRAM address represented by bits H

to H

(binary) should be in the range "00" to "13" in hexadecimal.

If an address other than above is input, the ML9044 cannot properly write a character code in or read it from the
DDRAM.

Note: The execution time of this instruction is 37

s at an oscillation frequency (OSC) of 270 kHz.

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LCD Drive Waveforms

The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9, 1/12 and 1/17
duties). See 1) to 3) below.
The relationship between the duty ratio and the frame frequency is as follows:

Duty ratio

Frame Frequency

1/9

75.0 Hz

1/12

56.3 Hz

1/17

79.4 Hz

Note:

At an oscillation frequency (OSC) of 270 kHz

(1) Driving the LCD of one 24-character line under the conditions of the 1-line display mode and the character

font of 5

7 dots

(1/9 duty, AS = 0, CSR = L, SSR = H)

COM

Character

Cursor
Arbitrator

COM

SEG

120

SEG

ML9044

COM

to COM

output Display-OFF common signals.

(1/9 duty, AS = 1, CSR = L, SSR = H)

COM

Character

Cursor

COM

SEG

120

SEG

ML9044

Arbitrator

COM

to COM

output Display-OFF common signals.

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EXAMPLES OF VLCD GENERATION CIRCUITS

With 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier

ML9044

BEB

5IN

Reference potential for

voltage multiplier

With 1/4 bias, a built-in contrast adjusting circuit

With 1/4 bias, no built-in contrast adjusting circuit

and the V

level input from an external circuit

and the V

level input from an external circuit

ML9044

BEB

5IN

level

ML9044

BEB

5IN

level

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With 1/5 bias, a built-in contrast adjusting circuit and a voltage multiplier

ML9044

BEB

5IN

Reference potential for

voltage multiplier

With 1/5 bias, a built-in contrast adjusting circuit

With 1/5 bias, no built-in contrast adjusting circuit

and the V

level input from an external circuit

and the V

level input from an external circuit

ML9044

BEB

5IN

level

ML9044

BEB

5IN

level

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1) COM and SEG Waveforms on 1/9 Duty

1 frame

, V

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(first character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(second character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(cursor line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(arbitrator line)

9 1 2 3 4 ··· 7 8 9 1 2 3 4 ··· 7 8 9 1 2

, V

COM

, V

SEG

Display

turning-off

waveform

Display

turning-on

waveform

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2) COM and SEG Waveforms on 1/12 Duty

1 frame

, V

Display

turning-off

waveform

Display

turning-on

waveform

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(first character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(second character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(cursor line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(arbitrator line)

12 1 2 3 4 5 6 ··· 9 10 11 12 1 2 3 4 5 6 ···

COM

SEG

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3) COM and SEG Waveforms on 1/17 Duty

1 frame

)

17 1 2 3 4 5 6 7 8 9 10 11 12 13 ··· 16 17 1 2

Display

turning-off

waveform

Display

turning-on

waveform

3 4

)

SEG

)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(first character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(second character line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(cursor line)

COM

(CSR = L, AS = L)

COM

(CSR = L, AS = H)

COM

(CSR = H, AS = L)

COM

(CSR = H, AS = H)

(arbitrator line)

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Initial Setting of Instructions

(a) Data transfer from and to the CPU using 8 bits of DB

to DB

Turn on the power.

Wait for 15 ms or more after V

has reached 2.5 V or higher.

Set "8 bits" with the Function Setting instruction.

Wait for 4.1 ms or more.

Set "8 bits" with the Function Setting instruction.

Wait for 100

s or more.

Set "8 bits" with the Function Setting instruction.

Check the Busy Flag for No Busy (or wait for 100

s or more).

Set "8 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)

10) Check the Busy Flag for No Busy.
11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting

instruction and Arbitrator Display Line Setting Instruction.

12) Check the Busy Flag for No Busy.
13) Initialization is completed.

An example of instruction code for 3), 5) and 7)

: Don't Care

(b) Data transfer from and to the CPU using 8 bits of DB

to DB

Turn on the power.

Wait for 15 ms or more after V

has reached 2.5 V or higher.

Set "8 bits" with the Function Setting instruction.

Wait for 4.1 ms or more.

Set "8 bits" with the Function Setting instruction.

Wait for 100

s or more.

Set "8 bits" with the Function Setting instruction.

Check the Busy Flag for No Busy (or wait for 100

s or longer).

Set "4 bits" with the Function Setting instruction.

10) Wait for 100

s or longer.

11) Set "4 bits", "Number of LCD lines" and "Font size" with the Initial Setting instruction. (After this, the

number of LCD lines and the font size cannot be changed.)

12) Check the Busy Flag for No Busy.
13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode Setting

instruction and Arbitrator Display Line Setting Instruction.

14) Check the Busy Flag for No Busy.
15) Initialization is completed.

An example of instruction code for 3), 5) and 7)

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An example of instruction code for 9)

*: In 13), check the Busy Flag for No Busy before executing each instruction.

Turn on the power.

Wait for 15 ms or more after V

has reached 2.5 V or higher.

Set "Number of LCD lines" and "Font size" with the Function Setting Instruction.

Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.

Check the busy flag for No Busy.

Initialization is completed.

*: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.

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ML9044-xxA CVWA PAD CONFIGURATION

Pad Layout

Chip Size:

10.62

2.55 mm

Chip Thickness: 625±20

Bump Size (1):

(PAD No. 1-62, 183-189)

Bump Size (2):

(PAD No. 63-182)

182

183

189

Pad Coordinates

Pad

Symbol

X (

Y (

Pad

Symbol

X (

Y (

5103

1100

1323

1100

4914

1100

1134

1100

4725

1100

945

1100

4536

1100

756

1100

4347

1100

567

1100

4158

1100

378

1100

5IN

3969

1100

189

1100

3780

1100

3591

1100

189

1100

3402

1100

378

1100

BEB

3213

1100

SHT

567

1100

3024

1100

756

1100

CSR

2835

1100

OSC

945

1100

SSR

2646

1100

OSC

1134

1100

2457

1100

OSC

1323

1100

2268

1100

1512

1100

2079

1100

1701

1100

1890

1100

1890

1100

1701

1100

COM

2079

1100

1512

1100

COM

2268

1100

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Pad

Symbol

X (

Y (

Pad

Symbol

X (

Y (

COM

2457

1100

SEG

102

3486

1088

COM

2646

1100

SEG

101

3402

1088

COM

2835

1100

SEG

100

3318

1088

COM

3024

1100

SEG

3234

1088

COM

3213

1100

SEG

3150

1088

COM

3402

1100

SEG

3066

1088

COM

3591

1100

SEG

2982

1088

COM

3780

1100

SEG

2898

1088

COM

3969

1100

SEG

2814

1088

COM

4158

1100

SEG

2730

1088

COM

4347

1100

SEG

2646

1088

COM

4536

1100

SEG

2562

1088

COM

4725

1100

SEG

2478

1088

COM

4914

1100

SEG

2394

1088

COM

5103

1100

SEG

2310

1088

DUMMY

5184

720

SEG

2226

1088

DUMMY

5184

480

SEG

2142

1088

DUMMY

5184

240

SEG

2058

1088

DUMMY

5184

SEG

1974

1088

DUMMY

5184

240

100

SEG

1890

1088

DUMMY

5184

480

101

SEG

1806

1088

DUMMY

5184

720

102

SEG

1722

1088

SEG

120

4998

1088

103

SEG

1638

1088

SEG

119

4914

1088

104

SEG

1554

1088

SEG

118

4830

1088

105

SEG

1470

1088

SEG

117

4746

1088

106

SEG

1386

1088

SEG

116

4662

1088

107

SEG

1302

1088

SEG

115

4578

1088

108

SEG

1218

1088

SEG

114

4494

1088

109

SEG

1134

1088

SEG

113

4410

1088

110

SEG

1050

1088

SEG

112

4326

1088

111

SEG

966

1088

SEG

111

4242

1088

112

SEG

882

1088

SEG

110

4158

1088

113

SEG

798

1088

SEG

109

4074

1088

114

SEG

714

1088

SEG

108

3990

1088

115

SEG

630

1088

SEG

107

3906

1088

116

SEG

546

1088

SEG

106

3822

1088

117

SEG

462

1088

SEG

105

3738

1088

118

SEG

378

1088

SEG

104

3654

1088

119

SEG

294

1088

SEG

103

3570

1088

120

SEG

210

1088

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Pad

Symbol

X (

Y (

Pad

Symbol

X (

Y (

121

SEG

126

1088

156

SEG

2814

1088

122

SEG

1088

157

SEG

2898

1088

123

SEG

1088

158

SEG

2982

1088

124

SEG

126

1088

159

SEG

3066

1088

125

SEG

210

1088

160

SEG

3150

1088

126

SEG

294

1088

161

SEG

3234

1088

127

SEG

378

1088

162

SEG

3318

1088

128

SEG

462

1088

163

SEG

3402

1088

129

SEG

546

1088

164

SEG

3486

1088

130

SEG

630

1088

165

SEG

3570

1088

131

SEG

714

1088

166

SEG

3654

1088

132

SEG

798

1088

167

SEG

3738

1088

133

SEG

882

1088

168

SEG

3822

1088

134

SEG

966

1088

169

SEG

3906

1088

135

SEG

1050

1088

170

SEG

3990

1088

136

SEG

1134

1088

171

SEG

4074

1088

137

SEG

1218

1088

172

SEG

4158

1088

138

SEG

1302

1088

173

SEG

4242

1088

139

SEG

1386

1088

174

SEG

4326

1088

140

SEG

1470

1088

175

SEG

4410

1088

141

SEG

1554

1088

176

SEG

4494

1088

142

SEG

1638

1088

177

SEG

4578

1088

143

SEG

1722

1088

178

SEG

4662

1088

144

SEG

1806

1088

179

SEG

4746

1088

145

SEG

1890

1088

180

SEG

4830

1088

146

SEG

1974

1088

181

SEG

4914

1088

147

SEG

2058

1088

182

SEG

4998

1088

148

SEG

2142

1088

183

DUMMY

5184

720

149

SEG

2226

1088

184

DUMMY

5184

480

150

SEG

2310

1088

185

DUMMY

5184

240

151

SEG

2394

1088

186

DUMMY

5184

152

SEG

2478

1088

187

DUMMY

5184

240

153

SEG

2562

1088

188

DUMMY

5184

480

154

SEG

2646

1088

189

DUMMY

5184

720

155

SEG

2730

1088

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ML9044-xxB CVWA PAD CONFIGURATION

Pad Layout

175

Pad Coordinates

Note:

The ML9044-xxB does not have the dummy pads corresponding to the pad numbers 56 to 62 and 183 to
189 for the ML9044-xxA.

Pad

Symbol

X (

Y (

Pad

Symbol

X (

Y (

5103

1100

1323

1100

4914

1100

1134

1100

4725

1100

945

1100

4536

1100

756

1100

4347

1100

567

1100

4158

1100

378

1100

5IN

3969

1100

189

1100

3780

1100

3591

1100

189

1100

3402

1100

378

1100

BEB

3213

1100

SHT

567

1100

3024

1100

756

1100

CSR

2835

1100

OSC

945

1100

SSR

2646

1100

OSC

1134

1100

2457

1100

OSC

1323

1100

2268

1100

1512

1100

2079

1100

1701

1100

1890

1100

1890

1100

1701

1100

COM

2079

1100

1512

1100

COM

2268

1100

Chip Size:

10.62

2.55 mm

Chip Thickness: 625±20

Bump Size (1):

(PAD No. 1-55)

Bump Size (2):

(PAD No. 56-175)

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Pad

Symbol

X (

Y (

Pad

Symbol

X (

Y (

COM

2457

1100

SEG

2898

1088

COM

2646

1100

SEG

2814

1088

COM

2835

1100

SEG

2730

1088

COM

3024

1100

SEG

2646

1088

COM

3213

1100

SEG

2562

1088

COM

3402

1100

SEG

2478

1088

COM

3591

1100

SEG

2394

1088

COM

3780

1100

SEG

2310

1088

COM

3969

1100

SEG

2226

1088

COM

4158

1100

SEG

2142

1088

COM

4347

1100

SEG

2058

1088

COM

4536

1100

SEG

1974

1088

COM

4725

1100

SEG

1890

1088

COM

4914

1100

SEG

1806

1088

COM

5103

1100

SEG

1722

1088

SEG

120

4998

1088

SEG

1638

1088

SEG

119

4914

1088

SEG

1554

1088

SEG

118

4830

1088

SEG

1470

1088

SEG

117

4746

1088

SEG

1386

1088

SEG

116

4662

1088

100

SEG

1302

1088

SEG

115

4578

1088

101

SEG

1218

1088

SEG

114

4494

1088

102

SEG

1134

1088

SEG

113

4410

1088

103

SEG

1050

1088

SEG

112

4326

1088

104

SEG

966

1088

SEG

111

4242

1088

105

SEG

882

1088

SEG

110

4158

1088

106

SEG

798

1088

SEG

109

4074

1088

107

SEG

714

1088

SEG

108

3990

1088

108

SEG

630

1088

SEG

107

3906

1088

109

SEG

546

1088

SEG

106

3822

1088

110

SEG

462

1088

SEG

105

3738

1088

111

SEG

378

1088

SEG

104

3654

1088

112

SEG

294

1088

SEG

103

3570

1088

113

SEG

210

1088

SEG

102

3486

1088

114

SEG

126

1088

SEG

101

3402

1088

115

SEG

1088

SEG

100

3318

1088

116

SEG

1088

SEG

3234

1088

117

SEG

126

1088

SEG

3150

1088

118

SEG

210

1088

SEG

3066

1088

119

SEG

294

1088

SEG

2982

1088

120

SEG

378

1088

PEDL9044-03

1Semiconductor

ML9044-xxA/xxB

59/60

Pad

Symbol

X (

Y (

Pad

Symbol

X (

Y (

121

SEG

462

1088

149

SEG

2814

1088

122

SEG

546

1088

150

SEG

2898

1088

123

SEG

630

1088

151

SEG

2982

1088

124

SEG

714

1088

152

SEG

3066

1088

125

SEG

798

1088

153

SEG

3150

1088

126

SEG

882

1088

154

SEG

3234

1088

127

SEG

966

1088

155

SEG

3318

1088

128

SEG

1050

1088

156

SEG

3402

1088

129

SEG

1134

1088

157

SEG

3486

1088

130

SEG

1218

1088

158

SEG

3570

1088

131

SEG

1302

1088

159

SEG

3654

1088

132

SEG

1386

1088

160

SEG

3738

1088

133

SEG

1470

1088

161

SEG

3822

1088

134

SEG

1554

1088

162

SEG

3906

1088

135

SEG

1638

1088

163

SEG

3990

1088

136

SEG

1722

1088

164

SEG

4074

1088

137

SEG

1806

1088

165

SEG

4158

1088

138

SEG

1890

1088

166

SEG

4242

1088

139

SEG

1974

1088

167

SEG

4326

1088

140

SEG

2058

1088

168

SEG

4410

1088

141

SEG

2142

1088

169

SEG

4494

1088

142

SEG

2226

1088

170

SEG

4578

1088

143

SEG

2310

1088

171

SEG

4662

1088

144

SEG

2394

1088

172

SEG

4746

1088

145

SEG

2478

1088

173

SEG

4830

1088

146

SEG

2562

1088

174

SEG

4914

1088

147

SEG

2646

1088

175

SEG

4998

1088

148

SEG

2730

1088

PEDL9044-03

1Semiconductor

ML9044-xxA/xxB

60/60

NOTICE

The information contained herein can change without notice owing to product and/or technical improvements.
Before using the product, please make sure that the information being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been chosen as an
explanation for the standard action and performance of the product. When planning to use the product, please
ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum ratings and within the
specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating
temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation
resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or
unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified
maximum ratings or operation outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is
granted by us in connection with the use of the product and/or the information and drawings contained herein.
No responsibility is assumed by us for any infringement of a third party's right which may result from the use
thereof.

The products listed in this document are intended for use in general electronics equipment for commercial
applications (e.g., office automation, communication equipment, measurement equipment, consumer
electronics, etc.). These products are not authorized for use in any system or application that requires special
or enhanced quality and reliability characteristics nor in any system or application where the failure of such
system or application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace
equipment, nuclear power control, medical equipment, and life-support systems.

Certain products in this document may need government approval before they can be exported to particular
countries. The purchaser assumes the responsibility of determining the legality of export of these products
and will take appropriate and necessary steps at their own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior permission.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9044CVWA

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9044CVWA