Semiconductor
ML9050/9051
1/71
PEDL9050-02
Semiconductor
ML9050/9051
132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays
GENERAL DESCRIPTION
The ML9050/9051 is an LSI for dot matrix graphic LCD devices carrying out bit map display.
This LSI can drive a dot matrix graphic LCD display panel under the control of an 8-bit
microcomputer. Since all the functions necessary for driving a bit map type LCD device are
incorporated in a single chip, using the ML9050/9051 makes it possible to realize a bit map type
dot matrix graphic LCD display system with only a few chips.
Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the
display panel, it is possible to carry out displays with a high degree of freedom such as Chinese
character displays, etc. With one chip, it is possible to construct a graphic display system with
a maximum of 132 65 dots. The display can be expanded further using two chips.
The ML9050/9051 is made using a CMOS process. Because it has a built-in RAM, low power
consumption is one of its features, and is therefore suitable for displays in battery-operated
portable equipment.
The ML9050 has 65 common signal outputs and 132 segment signal outputs and one chip can
drive a display of up to 65 132 dots.
The ML9051 has 49 common signal outputs and 132 segment signal outputs and one chip can
drive a display of up to 49 132 dots.
This device is not resistant to radiation or to light.
FEATURES
Direct display of the RAM data using the bit map method
Display RAM data "1" ... Dot is displayed
Display RAM data "0" ... Dot is not displayed
Display RAM capacity
ML9050/9051: 65 132 = 8580 dots
LCD Drive circuits
ML9050: 65 common outputs, 132 segment outputs
ML9051: 49 common outputs, 132 segment outputs
Microcomputer interface: Can select an 8-Bit parallel or serial interface
Built-in voltage multiplier circuit for the LCD drive power supply
Built-in LCD drive power supply adjustment circuit
Built-in LCD drive bias resistors
Line reversal drive/frame reversal drive (selected by a command)
Built-in oscillator circuit (Internal RC oscillator/external clock input)
A variety of commands
Read/write of display data, display ON/OFF, normal/reverse display, all dots ON/all dots
OFF, set page address, set display start address, etc.
Power supply voltage
Logic power supply: V
DD
-V
SS
= 1.8 V to 5.5 V
Voltage multiplier reference voltage: V
IN
-V
SS
= 1.8 V to V
DD
(5-Times multiplier 1.8 V to 3.6 V, 6-times multiplier 1.8 to 3 V, 7-times multiplier 1.8
to 2.5 V)
LCD Drive voltage: V
BI
-V
SS
= 6.0 to 18 V
Package: Gold bump chip, TCP
PEDL9050-02
This version: Dec. 1999
Previous version: Jun. 1999
Preliminary
Semiconductor
ML9050/9051
2/71
PEDL9050-02
BLOCK DIAGRAM
V
DD
V
IN
FRS
V1
V2
V3
V4
V5
V
SS
VC1+
VS1
VC2+
VS2
VC3+
VC4+
VC5+
VC6+
VOUT
VR
VRS
IRS
HPM
SEG Drivers
COM
Drivers
COM Output state
selection cricuit
Display data latch circuit
Display data RAM
132
65
Column address circuit
Bus holder
C86
CS1
CS2
A0
RD
(E)
WR
(R/
W
)
P/
S
RES
D7(SI)
D6(SCL)
D5
D4
D3
D2
D1
D0
Oscillator circuit
Display timing generator circuit
COMS
COMS
COM63
COM0
SEG131
SEG0
Line address circuit
I/O Buffer
Page address circuit
Power supply circuit
Command decoder
Status
MPU lnterface
FR
CL
DOF
M/S
CLS
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PEDL9050-02
PIN DESCRIPTION
Function
Pin name
Number
of pins
Description
MPU
Interface
8
I/O
I/O
D0 to D7
This is an 8-bit bi-directional data bus that can be connected to an 8-bit
or 16-bit standard MPU data bus. When a serial interface is selected (P/S
= "L"):
D7: Serial data input pin (SI)
D6: Serial clock input pin (SCL)
In this case, D0 to D5 will be in the Hi-Z state. D0 to D7 will all be in the
Hi-Z state when the chip select is in the inactive state.
1
I
A0
Normally, the lowest bit of the MPU address bus is connected and used
for distinguishing between data and commands.
A0 = "H": Indicates that D0 to D7 is display data.
A1 = "L": Indicates that D0 to D7 is control data.
1
I
RES
Initial setting is made by making RES = "L". The reset operation is made
during the active level of the RES signal.
2
I
CS1
CS2
These are the chip select signals. The Chip Select of the LSI becomes
active when CS1 is "L" and also CS2 is "H" and allows the input/output of
data or commands.
1
I
RD
(E)
The active level of this signal is "L" when connected to an 80-series MPU.
This terminal is connected to the RD signal of the 80-series MPU, and the
data bus of the ML9050/9051 goes into the output state when this signal
is "L".
The active level of this signal is "H" when connected to a 68-series MPU.
This pin will be the Enable and clock input pin when connected to a 68-
series MPU.
1
I
WR
(R/W)
The active level of this signal is "L" when connected to an 80-series MPU.
This terminal is connected to the WR signal of the 80-series MPU. The
data on the data bus is latched into the ML9052 at the rising edge of the
WR signal.
When connected to a 68-series MPU, this pin becomes the input pin for
the Read/Write control signal.
R/W = "H": Read, R/W = "L": Write
1
I
C86
This is the pin for selecting the MPU interface type.
C86 = "H": 68-Series MPU interface.
C86 = "L": 80-Series MPU interface.
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ML9050/9051
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PEDL9050-02
Function
Pin name
Number
of pins
Description
MPU
Interface
I/O
1
I
P/S
Data/command
Data
Read/Write
Serial clock
M/S CLS
DOF
FRS
FR
CL
Power
supply circuit
Oscillator
circuit
"H"
"H"
"L"
Output
Output
Output
Output
Output
Output
Output
Input
Enabled
Enabled
Enabled
Disabled
"L"
"H"
"L"
Input
Input
Output
Output
Input
Input
Input
Input
Disabled
Disabled
Disabled
Disabled
"H"
"L"
A0
A0
D0 to D7
SI (D7)
RD, WR
Write only
SCL (D6)
P/S
This is the pin for selecting parallel data input or serial data input.
P/S = "H": Parallel data input.
P/S = "L": Serial data input.
The pins of the LSI have the following functions depending on the state of
P/S input.
When P/S is "L", D0 to D5 will go into the Hi-Z state. In this condition,
the data on the lines D0 to D5 can be "H", "L", or open. The pins RD (E)
and WR (R/W) should be tied to either the "H" level or the "L" level.
During serial data input, it is not possible to read the display data in the
RAM.
Oscillator
circuit
1
I
CLS
This is the pin for selecting whether to enable or disable the internal
oscillator circuit for the display clock.
CLS = "H": The internal oscillator circuit is enabled.
CLS = "L": The internal oscillator circuit is disabled (External input).
When CLS = "L", the display clock is input at the pin CL.
Display
timing
generator
circuit
1
I
M/S
This is the pin for selecting whether master operation or slave operation
is made towards the ML9050/9051. During master operation, the
synchronization with the LCD display system is achieved by inputting the
timing signals necessary for LCD display.
M/S = "H": Master operation
M/S = "L": Slave operation
The functions of the different circuits and pins will be as follows
depending on the states of M/S and CLS signals.
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ML9050/9051
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PEDL9050-02
Function
Pin name
Number
of pins
Description
I/O
M/S CLS
CL
"H"
"H"
"L"
Output
Input
"L"
"H"
"L"
Input
Input
Display
timing
generator
circuit
1
I/O
CL
This is the display clock input/output pin.
The function of this pin will be as follows depending on the states of M/S
and CLS signals.
When the ML9050/9051 is used in the master/slave mode, the
corresponding CL pin has to be connected.
1
I/O
FR
This is the input/output pin for LCD display frame reversal signal.
M/S = "H": Output
M/S = "L": Input
When the ML9050/9051 is used in the master/slave mode, the
corresponding FR pin has to be connected.
1
I/O
DOF
This is the blanking control pin for the LCD display.
M/S = "H": Output
M/S = "L": Input
When the ML9050/9051 is used in the master/slave mode, the
corresponding DOF pin has to be connected.
1
O
FRS
This is the output pin for static drive.
This pin is used in combination with the FR pin.
Power
supply
circuit
1
I
IRS
This is the pin for selecting the resistor for adjusting the voltage V1.
IRS = "H": The internal resistor is used.
IRS = "L": The internal resistor is not used. The voltage V1 is adjusted
using the external potential divider resistors connected to the pins VR.
This pin is effective only in the master operation. This pin is tied to the
"H" or the "L" level during slave operation.
1
I
HPM
This is the power control pin for the LCD drive power supply circuit.
HPM = "H": Normal mode
HPM = "L": High power mode
This pin is effective only during master operation mode. This pin is tied to
the "H" or the "L" level during slave operation.
13
--
V
DD
This pin is tied to the MPU power supply terminal VCC.
9
--
V
SS
This is the 0 V pin connected to the system ground (GND).
4
--
V
IN
This is the reference power supply of the voltage multiplier circuit for
driving the LCD.
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