ML9060

¡ Semiconductor

1/19

FEDL9060-01

This version: Feb. 1999

GENERAL DESCRIPTION

The ML9060 consists of a 320-bit shift register, a 320-bit data latch, 160 sets of LCD drivers, and
a common signal generator circuit.
The LCD display data is input serially to the shift register from the DATA IN pin in
synchronization with the CLOCK IN signal, and is stored in the data latch by the LOAD IN
signal.
The LCD display data stored in the data latch is output via the LCD drivers.
A maximum of 160 segments of LCD can be driven in static display mode and a maximum of
320 segments can be driven directly in the 1/2 duty display mode.
It is possible to select the mode of using the internal oscillator circuit or the mode of using an
external clock for the common signal generator circuit. The ML9060 also outputs the sync signal
during the 1/2 duty display mode.

FEATURES

· Logic power supply

: 2.7 to 5.5V

· LCD Driving voltage

: 4.5 to 16V

· Maximum number of segments that can be driven:

Static display mode

: 160 segments

1/2 Duty display mode : 320 segments

· Serial transfer clock

: 1 MHz max.

· The microcontroller interface consists of the three signals DATA IN, CLOCK IN, and LOAD

IN.

· An RC oscillator circuit is built in which can use either an external resistor or the internal

resistor.

· Cascade connection of several ICs is possible. (Max. 3 chips)
· Built-in common signal generator circuit.
· Built-in common output mid-level voltage generator circuit.
· Input for turning all segments ON is available (SEG-TEST IN).
· Input for turning all segments OFF is available (BLANK IN).
· Gold bump chip

Product name: ML9060DVWA

¡ Semiconductor

ML9060

1/2 DUTY, 160-OUTPUT STATIC LCD DRIVER

FEDL9060-01

This version: Mar. 2001

ML9060

¡ Semiconductor

2/19

FEDL9060-01

BLOCK DIAGRAM

SEG-TEST IN

SEG-TEST OUT

BLANK IN

BLANK OUT

DATA IN

OSC2

OSC1

OSC I/E

M/S

SYNC

GND

Shift Register B

P0160b

P01b

SIb

SOb

Shift Register A

P0160a

P01a

SIa

SOa

LOAD IN

LOAD OUT

SEG160

SEG2

SEG1

CLOCK IN

CLOCK OUT

DATA OUT

Timing Generator

LCD

1/2VLCD Generator
& Common Drivers

COM B

COM A

COM OUT

D/S

OSCR

1/64 or 1/128

OSC

1/2

SYNC

Data Latch B

L0160b

L01b

LI160b

LI1b

Data Latch A

L0160a

L01a

LI160a

LI1a

Segment Drivers

Data Selector

DSI160b

DSI1b

DSI160a

DSI1a

DS0160

DS02

DS01

ML9060

¡ Semiconductor

3/19

FEDL9060-01

*: Use with V

LCD

Note: Never place a short between an output pin and another output pin or between an output

pin and other pins (input pins, I/O pins, or power supply pins).

: In order to prevent mdlfunctioning of the device, turn on the logic power supply first and

then turn on the LCD driving power supply, and also turn off the LCD driving power
supply and then turn off the logic power supply.

ABSOLUTE MAXIMUM RATINGS

Parameter

Symbol

Condition

Rating

Unit

Logic power supply voltage

0.3 to +6.5

LCD Driving voltage

LCD

0 to 18

Input voltage

GND0.3 to V

+0.3

Storage temperature

STG

55 to +150

Ta = 25

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Condition

Range

Unit

Logic power supply voltage

2.7 to 5.5

LCD Driving voltage

LCD

4.5 to 16

Junction operating
temperature

jop

40 to +85

ML9060

¡ Semiconductor

4/19

FEDL9060-01

ELECTRICAL CHARACTERISTICS

DC Characteristics

"H" Input voltage

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable pin

IH1

0.7V

DATA IN

CLOCK IN

LOAD IN

SEG-TEST IN

BLANK IN

M/S, D/S

OSC1, OSC I/E

IH2

0.8V

"L" Input voltage

IL1

GND

0.3V

IL2

GND

0.2V

Input leakage current 1

= V

or 0V

1.0

Input leakage current 2

= V

or 0V

D/S = "H"

M/S = "L"

SYNC

"H" Output

voltage

OHS

= 30mA

LCD

0.2

SEG1 to SEG160

OHC

= 150mA

LCD

0.2

COM A, COM B

OHL1

= 100mA

0.9V

DATA OUT

CLOCK OUT

LOAD OUT

SEG-TEST OUT

BLANK OUT

COM OUT

SYNC

OHL2

= 200mA

0.9V

OSC2

"M" Output

voltage

OMC

*3 I

150mA

1/2V

LCD

0.15

1/2V

LCD

1/2V

LCD

+0.15

COM A, COM B

OLS

= 30mA

0.2

OLC

= 150mA

0.2

DATA OUT

CLOCK OUT

LOAD OUT

SEG-TEST OUT

BLANK OUT

COM OUT

SYNC

OLL1

= 100mA

0.1V

OLL2

= 200mA

0.1V

OSC2

Output

resistance

SEG

SEG1 to SEG160

COM

1.5

COM A, COM B

Segment

Common

Logic

Common

Segment

Common

Logic

Segment

Common

SEG1 to SEG160

COM A, COM B

(VDD = 2.7 to 5.5V, VLCD = 4.5 to 16V, Tj = 40 to +85

"L" Output

voltage

"M": Middle level

ML9060

¡ Semiconductor

5/19

FEDL9060-01

*1: Applicable to the DATA IN, LOAD IN, SEG-TEST IN, M/S, D/S, and OSC I/E pins.
*2: Applicable to the CLOCK IN, OSC1, and BLANK IN pins.
*3: Applicable to the voltage drop when the current flows into or out of one COM pin.
*4: The LCD display data of "0" and "1" are input alternately.

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable

pin

DDS1

Static supply current

D/S = "L" (Static)
Fix other input levels
at either "H" or "L"
Oscillator stopped
No load

DDS2

D/S = "H" (1/2duty)
Fix other input levels
at either "H" or "L"
Oscillator stopped
No load

LCDS1

D/S = "L" (Static)
Fix other input levels
at either "H" or "L"
Oscillator stopped
No load

LCD

LCDS2

900

D/S = "H" (1/2duty)
Fix other input levels
at either "H" or "L"
Oscillator stopped
No load

LCD

DD1

Dynamic supply current *4

= 5.5V

D/S = "L" (Static)
OSC1 is Open
OSC2 is connected to OSCR
Other inputs are "H" or "L"
No load

DD2

= 5.5V

D/S = "H" (1/2duty)
OSC1 is Open
OSC2 is connected to OSCR
Other inputs are "H" or "L"
No load

LCD1

200

= 5.5V

D/S = "L" (Static)
OSC1 is Open
OSC2 is connected to OSCR
Other inputs are "H" or "L"
No load

LCD

LCD2

= 5.5V

D/S = "H" (1/2duty)
OSC1 is Open
OSC2 is connected to OSCR
Other inputs are "H" or "L"
No load

LCD

ML9060

¡ Semiconductor

6/19

FEDL9060-01

Switching Characteristics

Parameter

Symbol

Condition

Min. Typ. Max. Unit

Applicable pin

CP1

25.6 kHz

OSC IN Clock frequency

(external input)

The clock is input to the

OSC1 pin. The pins OSC2

and OSCR are left open.

OSC I/E = "L"

OSC1

= 2.7 to 5.5V, V

LCD

= 4.5 to 16V, Tj = 40 to +85

WCP1

Clock pulse width

(external input)

OSC1

2.0

8.5

15.0 kHz

External Rf clock

frequency

(internal oscillations)

An Rf of 120k W

2% is

connected between OSC1

and OSC2. OSCR is left

open. OSC I/E = 'H"

OSC1, OSC2

OSC2

7.7

12.8 20.5 kHz

Internal Rf clock frequency

(with the built-in oscillator)

OSC1 open. OSC2 and

OSCR shorted. OSC I/E

tied to V

or any "H" level.

OSC1, OSCR,

OSC2

CP2

MHz

Data clock frequency

CLOCK IN

WCP2

100

Data clock pulse width

CLOCK IN

Data setup time

DATA IN

Data hold time

CLOCK IN

100

CLOCK to LOAD

Period

CLOCK IN

100

LOAD to CLOCK

Period

LOAD IN

WLD

100

LOAD Pulse width

LOAD IN

PLH

PHL

CLOCK IN to

DATA OUT delay time

=15pF

CLOCK IN

DATA OUT

DIO

IN to OUT delay time

No load

CLOCK IN/OUT

LOAD IN/OUT

SEG-TEST IN/OUT

BLANK IN/OUT

DCS

COM OUT to SYNC

delay time

=15pF

COM OUT

SYNC

Input signal rise time

All inputs other than

the OSCR input

Input signal fall time

ML9060

¡ Semiconductor

7/19

FEDL9060-01

TIMING DIAGRAM

OSC1

(External clock)

1/f

CP1

WCP1

DATA IN

CLOCK IN

LOAD IN

DATA OUT

WCP2

1/f

CP2

WLD

PLH

PHL

CLOCK IN

LOAD IN

SEG-TEST IN

BLANK IN

CLOCK OUT

LOAD OUT

SEG-TEST OUT

BLANK OUT

All input signals

COM OUT

SYNC

1/2V

DIO

DCS

ML9060

¡ Semiconductor

8/19

FEDL9060-01

FUNCTIONAL DESCRIPTION

The ML9060 is an LCD driver LSI with an internal shift register and a set of internal data latches
and is capable of driving LCD displays of up to 160 segments in the static mode or 320 segments
in the 1/2 duty mode. The display data is read into the shift register serially from the DATA
IN pin at the rising edge of the CLOCK IN input signal. The display data is transferred internally
to the data latches at the High level of the LOAD IN input signal and is output to the segments
via the segment drivers in this IC. The display data in the shift register is output via the DATA
OUT pin in synchronization with the falling edge of the CLOCK IN input signal. The display
data should be input in the sequence of SEG160, SEG159, ... , SEG2, SEG1 for proper display of
data.

Description of Pin Functions
· M/S
This is the input pin for selecting either the Master mode or the Slave mode. This LSI goes into
the master mode when this pin is High and enters the Slave mode when this pin is Low.

· D/S
This input pin is for selecting either the dynamic display mode at 1/2 duty (D mode - "H" input)
or the static display mode (S mode - "L" input).
Note that the internal bias resistor is made ON in the dynamic (D) mode and is turned OFF in
the static mode (S).

· OSC I/E
This is the input pin for selecting whether to use the external clock input mode, or the internal
Rf oscillation mode or the external Rf oscillation mode.
When this pin is tied to the "H" level, the internal Rf oscillation mode or the external Rf
oscillation is used. When this pin is tied to the "L" level, the external clock input is used for the
operation of the LSI.
In the slave mode of operation of this LSI, any input to this pin will be ignored. Hence, tie this
pin to V

or GND in the slave mode.

· OSC1, OSCR, OSC2
These are the pins for the oscillator for generating the common signal.

In the Master mode (M/S pin = "H"):
It is possible to select from among the three modes - internal Rf oscillation mode, external Rf
oscillation mode, and the external clock input mode. During the static display operation mode,
a common signal with 1/128th the frequency of the clock oscillator is output via the COM OUT
pin.
During the 1/2 duty dynamic display operation mode, a common signal with 1/64th the
frequency of the clock oscillator is output via the COM OUT pin.
· Internal Rf oscillation mode: Tie the OSC I/E pin to "H", short the pins OSCR and OSC2, and

leave the pin OSC1 open.

· External Rf oscillation mode: Tie the OSC I/E pin to "H", connect an external resistor Rf

between the pins OSC1 and OSC2, and leave the pin OSCR open.

· External clock input mode: Tie the OSC I/E pin to "L", leave open the pins OSCR and OSC2,

and input the external clock signal to the pin OSC1.

ML9060

¡ Semiconductor

9/19

FEDL9060-01

In the Slave mode (M/S pin = "L"):
Leave open the pins OSCR and OSC2 and connect the pin OSC1 to the COM OUT pin of the
ML9060 which has been set in the master mode. The common signal that is input to the pin OSC1
will be used as the internal common signal and is also output via a buffer from the COM OUT
pin.

· COM OUT
This is the common signal output pin. Connect this pin to the OSC1 pin of the ML9060 that is
set in the slave mode.
During operation in the master mode (M/S pin = "H") for static display, a common signal with
1/128th the frequency of the oscillator is output.
During operation in the master mode (M/S pin = "H") for 1/2 duty dynamic display, a common
signal with 1/64th the frequency of the oscillator is output.
During operation in the slave mode (M/S pin = "L"), the common signal that is input at the pin
OSC1 is output from this pin via a buffer.

· SYNC
This is the I/O pin for common signal synchronization.
This pin becomes the synchronization signal output pin during operation in the master mode
(M/S pin = "H") for 1/2 duty dynamic display.
This pin becomes the synchronization signal input pin during operation in the slave mode (M/
S pin = "L") for 1/2 duty dynamic display.
For cascade operation in the 1/2 duty display mode, connect the SYNC pins of all ML9060 ICs
used together.
During operation in the static display mode, this pin is tied to the "L" level inside the IC.
Connect this pin either to GND or leave it open.

· DATA IN
This is the display data input pin. Input the display data in the sequence of SEG160, SEG159,
... , SEG2, SEG1. The segment is turned ON when the display data is "H" and OFF when "L".

· DATA OUT
This is the display data output pin. During the static display mode of operation, the data of the
160th stage of the shift register is output from this pin. During the 1/2 duty dynamic display
mode, the data of the 320th stage of the shift register is output from this pin.

· CLOCK IN
This is the input pin for the shift clock of the display data. The display data that is input at the
DATA IN pin is input serially to the shift register at the rising edge of the CLOCK IN signal.
Also, the display data in the shift register is output from the DATA OUT pin at the falling edge
of the CLOCK IN signal.

· CLOCK OUT
This is the output pin for the shift clock of the display data. The shift clock signal that is input
to the CLOCK IN pin is output via a buffer from this pin.

· LOAD IN
This is the input pin for the display data load signal.
The display data in the shift register is output as such to the segment driver when this signal is
at the "H" level. When this signal is made "L", the shift register is isolated from the segment
drivers, and the display data of the shift register just before this pin goes "L" is retained in the
data latches and transfered to the segment drivers.

ML9060

¡ Semiconductor

10/19

FEDL9060-01

· LOAD OUT
This is the output pin for the display data load signal. The load signal that is input to the LOAD
IN pin is output from this pin via a buffer.

· SEG-TEST IN
This is the input pin for making all segments ON. When this pin is "H", all segment outputs
(SEG1 to SEG160) become ON irrespective of the display data and the Blank signal. When this
pin is made "L", each of the segment outputs (SEG1 to SEG160) become ON or OFF according
to the display data.

· SEG-TEST OUT
This is the output pin for making all segments ON. The segment ON signal that is input to at
the SEG-TEST IN pin is output via a buffer.

· BLANK IN
This is the input pin for making all segments OFF. When this pin is "H", all segment outputs
(SEG1 to SEG160) become OFF irrespective of the display data. When this pin is made "L", each
of the segment outputs (SEG1 to SEG160) becomes ON or OFF according to the display data. The
BLANK IN is valid when the segment ON signal is "L".

· BLANK OUT
This is the output pin for making all segments OFF. The segment OFF signal that is input to the
BLANK IN pin is output via a buffer.

· SEG1 to SEG160
These are the signal outputs for driving the LCD segments and are connected to the corresponding
segment pins of the LCD panel.

In the Static display mode:
The SEGn output corresponds to bit n of the display data in the data latch A. The display data
in the data latch B becomes invalid. In the segment ON condition, a signal with a phase opposite
to that of the COM OUT signal is output from these pins. In the segment OFF condition, a signal
with a phase identical to that of the COM OUT signal is output from these pins.

In the 1/2 duty dynamic display mode:
The SEGn output corresponds to bit n of the display data in the data latch A when COM A has
been selected and to bin n of the display data in the data latch B when COM B has been selected.
In the segment display ON condition, a signal opposite in phase to that of the selected COM
output is output from these pins. In the segment display OFF condition, a signal identical in
phase to that of the selected COM output is output from these pins.

· COM A, COM B
These are the outputs for LCD display and are connected to the common pins of the LCD panel.

In the Static display mode:
COM A and COM B both output a signal with the same phase as that of the COM OUT signal.

ML9060

¡ Semiconductor

11/19

FEDL9060-01

In the 1/2 duty dynamic display mode:
COM A and COM B change their states at every cycle of the COM OUT signal and repeat the
selected and non-selected modes always opposing each other in phase. A signal with the same
phase as that of the COM OUT signal is output in the selected mode. A voltage equal to 1/2V

LCD

is output in the non-selected mode.
When COM A is in the selected mode (that is, COM B is in the non-selected mode), the segment
outputs (SEG1 to SEG160) output signals corresponding to the display data in the data latch A.
When COM B is in the selected mode (that is, COM A is in the non-selected mode), the segment
outputs (SEG1 to SEG160) output signals corresponding to the display data in the data latch B.

· V

This is the power supply input pin for the logic circuits.

· V

LCD

This is the power supply input pin for the LCD drivers.

· GND
This is the ground pin for all circuits.

ML9060

¡ Semiconductor

12/19

FEDL9060-01

In the static display mode:

Segment Output and Common Output Waveforms
In the 1/2 duty display mode:

COM OUT

GND

SYNC

GND

COM A

Selected

COM B

Selected

COM A

Selected

COM B

Selected

COM A

LCD

1/2V

LCD

GND

COM B

LCD

1/2V

LCD

GND

LCD

GND

OFF

LCD

GND

OFF

LCD

GND

OFF

LCD

GND

Data latch A

Data latch B

Data latch A

Data latch B

SEGn

COM OUT

GND

COM A

LCD

GND

COM B

LCD

GND

LCD

GND

OFF

LCD

GND

SEGn

ML9060

¡ Semiconductor

13/19

FEDL9060-01

When a single ML9060 is used - 1/2 duty dynamic display mode (external Rf oscillation
mode)

APPLICATION CIRCUIT EXAMPLES

When a single ML9060 is used - Static display mode (internal Rf oscillation mode)

From the controller

ML9060

SEG-TEST IN

BLANK IN

LOAD IN

DATA IN

CLOCK IN

COM A

SYNC

LCD Panel 160 segments,

static display

D/S

M/S

OSC1

OSC2

OSCR

OSC I/E

open

GND

open

SEG160

SEG1

COM

open

COM B

From the controller

ML9060

SEG-TEST IN

BLANK IN

LOAD IN

DATA IN

CLOCK IN

COM A

SYNC

LCD Panel 320 segments,

1/2 Duty dynamic display

D/S

M/S

OSC1

OSC2

OSCR

OSC I/E

open

SEG160

SEG1

COM A

COM B

ML9060

¡ Semiconductor

14/19

FEDL9060-01

Note: Take care about the resistance and capacitance of wiring for cascade connection.

Cascade Connection - Static display mode (external clock input mode)

From the controller

ML9060

SEG-TEST IN

BLANK IN

LOAD IN

DATA IN

CLOCK IN

D/S

M/S

OSC1 OSC2 OSCR OSC I/E

SEG-TEST OUT

BLANK OUT

LOAD OUT

DATA OUT

CLOCK OUT

COM OUT

SYNC

open

160

ML9060

SEG-TEST IN

BLANK IN

LOAD IN

DATA IN

CLOCK IN

D/S

M/S

OSC1 OSC2 OSCR OSC I/E

SEG-TEST OUT

BLANK OUT

LOAD OUT

DATA OUT

CLOCK OUT

COM OUT

SYNC

open

160

GND

open

COM A

open

LCD Panel (160 x n segments)

COM

Static

External clock

COM B

open

Note: Take care about the resistance and capacitance of wiring for cascade connection.

Cascade Connection - 1/2 duty dynamic display mode (internal Rf oscillation mode)

From the controller

ML9060

SEG-TEST IN

BLANK IN

LOAD IN

DATA IN

CLOCK IN

D/S

M/S

OSC1 OSC2 OSCR OSC I/E

SEG-TEST OUT

BLANK OUT

LOAD OUT

DATA OUT

CLOCK OUT

COM OUT

SYNC

open

160

ML9060

SEG-TEST IN

BLANK IN

LOAD IN

DATA IN

CLOCK IN

D/S

M/S

OSC1 OSC2 OSCR OSC I/E

SEG-TEST OUT

BLANK OUT

LOAD OUT

DATA OUT

CLOCK OUT

COM OUT

SYNC

open

160

GND

open

COM B

open

LCD Panel (320 x n segments)

COM B

1/2 duty dynamic display

COM A

open

COM A

ML9060

¡ Semiconductor

15/19

FEDL9060-01

PAD CONFIGURATION

Pad Layout (Pattern side)

Chip size

: 14.50 ¥ 1.63mm

Chip thickness

: 625mm

30mm

Minimum bump pitch

: 80mm

Bump height

: 15mm

Bump height inside the chip : max. min.

Bump hardness

: max. 100 (HV: 25 g LOAD)

* : The substrate of the chip should either be connected to the GND level or be left open.

204

205

214

(0,0)

30mm

Passivation

Aluminum

Bump and Alignment Mark Dimensions (Pattern side)

PAD No.1 to 26, 37 to 204

: 50 ¥ 80mm

PAD No.27 to 36, 205 to 214 : 80 ¥ 50mm
Alignment marks A and B

: Shown below

ML9060

¡ Semiconductor

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FEDL9060-01

Pad Center Coordinates

Pad No.

Y-coordinate

(

mm)

X-coordinate

(

mm)

Pad name

636

6680

Pad No.

Y-coordinate

(

mm)

X-coordinate

(

mm)

Pad name

636

4008

OSC2

OSCR

OSC1

6146

5611

5077

4542

4008

3474

2939

2405

1870

1336

802

267

CLOCK IN

LOAD IN

SEG-TEST IN

BLANK IN

636

435

DATA IN

636

SYNC

COMOUT

LCD

GND

D/S

OSC I/E

M/S

802

1336

1870

2405

2939

3474

355

275

195

115

125

205

285

636

COMA

636

4542

636

5077

636

5611

636

6146

636

6680

636

7121

636

7121

636

7121

636

7121

636

7121

636

7121

636

7121

636

7121

636

7121

636

7121

636

6680

636

6600

636

6520

636

6440

NC: No Connection

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¡ Semiconductor

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FEDL9060-01

Pad No.

Y-coordinate

(

mm)

X-coordinate

(

mm)

Pad name

636

6360

COM B

Pad No.

Y-coordinate

(

mm)

X-coordinate

(

mm)

Pad name

636

2760

SEG45

100

101

6280

6200

6120

6040

5960

5880

5800

5720

5640

5560

5480

5400

5320

5240

5160

5080

5000

4920

4840

102

103

104

105

2680

2600

2520

2440

2360

2280

2200

2120

2040

1960

1880

1800

1720

1640

1560

1480

1400

1320

1240

636

SEG1

636

SEG46

636

SEG2

636

SEG47

636

SEG3

636

SEG48

636

SEG4

636

SEG49

636

SEG5

636

SEG50

636

SEG6

636

SEG51

636

SEG7

636

SEG52

636

SEG8

636

SEG53

636

SEG9

636

SEG54

636

SEG10

636

SEG55

636

SEG11

636

SEG56

636

SEG12

636

SEG57

636

SEG13

636

SEG58

636

SEG14

636

SEG59

636

SEG15

636

SEG60

636

SEG16

636

SEG61

636

SEG17

636

SEG62

636

SEG18

636

SEG63

636

SEG19

636

SEG64

106

107

108

109

110

4760

4680

4600

4520

4440

4280

4200

4120

4040

112

113

114

115

1160

1080

1000

920

840

680

600

520

440

636

SEG20

636

SEG65

636

SEG21

636

SEG66

636

SEG22

636

SEG67

636

SEG23

636

SEG68

636

SEG24

636

SEG69

636

SEG26

636

SEG71

636

SEG27

636

SEG72

636

SEG28

636

SEG73

636

SEG29

636

SEG74

116

117

118

119

120

121

3960

3880

3800

3720

3640

3560

3480

3400

3320

3240

122

123

124

125

360

280

200

120

200

280

360

636

SEG30

636

SEG75

636

SEG31

636

SEG76

636

SEG32

636

SEG77

636

SEG33

636

SEG78

636

SEG34

636

SEG79

636

SEG35

636

SEG80

636

SEG36

636

SEG81

636

SEG37

636

SEG82

636

SEG38

636

SEG83

636

SEG39

636

SEG84

126

3160

3080

3000

2920

2840

127

128

129

130

440

520

600

680

760

636

SEG40

636

SEG85

636

SEG41

636

SEG86

636

SEG42

636

SEG87

636

SEG43

636

SEG88

636

SEG44

636

SEG89

111

4360

760

636

SEG25

636

SEG70

ML9060

¡ Semiconductor

18/19

FEDL9060-01

Pad No.

Y-coordinate

(

mm)

X-coordinate

(

mm)

Pad name

131

636

840

SEG90

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

Pad No.

Y-coordinate

(

mm)

X-coordinate

(

mm)

Pad name

176

636

4440

SEG135

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

920

1000

1080

1160

1240

1320

1400

1480

1560

1640

1720

1800

1880

1960

2040

2120

2200

2280

2360

192

193

194

195

4520

4600

4680

4760

4840

4920

5000

5080

5160

5240

5320

5400

5480

5560

5640

5720

5800

5880

5960

636

SEG91

636

SEG136

636

SEG92

636

SEG137

636

SEG93

636

SEG138

636

SEG94

636

SEG139

636

SEG95

636

SEG140

636

SEG96

636

SEG141

636

SEG97

636

SEG142

636

SEG98

636

SEG143

636

SEG99

636

SEG144

636

SEG100

636

SEG145

636

SEG101

636

SEG146

636

SEG102

636

SEG147

636

SEG103

636

SEG148

636

SEG104

636

SEG149

636

SEG105

636

SEG150

636

SEG106

636

SEG151

636

SEG107

636

SEG152

636

SEG108

636

SEG153

636

SEG109

636

SEG154

151

152

153

154

155

157

158

159

160

196

197

198

199

200

2440

2520

2600

2680

2760

2920

3000

3080

3160

202

203

204

205

6040

6120

6200

6280

6360

6520

6600

6680

7121

636

SEG110

636

SEG155

636

SEG111

636

SEG156

636

SEG112

636

SEG157

636

SEG113

636

SEG158

636

SEG114

636

SEG159

636

SEG116

636

SEG117

636

SEG118

636

SEG119

285

161

162

163

164

165

166

167

168

169

170

206

207

208

209

210

211

3240

3320

3400

3480

3560

3640

3720

3800

3880

3960

212

213

214

7121

636

SEG120

205

636

SEG121

125

BLANKOUT

636

SEG122

SEG-TESTOUT

636

SEG123

LOADOUT

636

SEG124

115

CLOCKOUT

636

SEG125

195

636

SEG126

275

DATAOUT

636

SEG127

355

636

SEG128

435

6980

640

'+' ALIGN

6980

640

'+' ALIGN

636

SEG129

171

172

173

174

175

4040

4120

4200

4280

4360

636

SEG130

636

SEG131

636

SEG132

636

SEG133

636

SEG134

156

201

2840

6440

636

SEG115

636

SEG160

ML9060

¡ Semiconductor

19/19

FEDL9060-01

NOTICE

The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.

The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.

When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.

Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.

Neither indemnity against nor license of a third party's industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party's right which may result from the use thereof.

The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.

Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.

No part of the contents contained herein may be reprinted or reproduced without our prior
permission.

MS-DOS is a registered trademark of Microsoft Corporation. Other product names and
company names are trademarks or registered trademarks of their respective owners.

Printed in Japan

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9060DVWA

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ML9060DVWA